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  1. <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">

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  25. <title>ARM Options (Using the GNU Compiler Collection (GCC))</title>

  26. 

  27. <meta name="description" content="ARM Options (Using the GNU Compiler Collection (GCC))">

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  32. <link href="index.html#Top" rel="start" title="Top">

  33. <link href="Option-Index.html#Option-Index" rel="index" title="Option Index">

  34. <link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">

  35. <link href="Submodel-Options.html#Submodel-Options" rel="up" title="Submodel Options">

  36. <link href="AVR-Options.html#AVR-Options" rel="next" title="AVR Options">

  37. <link href="ARC-Options.html#ARC-Options" rel="prev" title="ARC Options">

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  65. 

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  67. </head>

  68. 

  69. <body lang="en">

  70. <a name="ARM-Options"></a>

  71. <div class="header">

  72. <p>

  73. Next: <a href="AVR-Options.html#AVR-Options" accesskey="n" rel="next">AVR Options</a>, Previous: <a href="ARC-Options.html#ARC-Options" accesskey="p" rel="prev">ARC Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>

  74. </div>

  75. <hr>

  76. <a name="ARM-Options-1"></a>

  77. <h4 class="subsection">3.19.5 ARM Options</h4>

  78. <a name="index-ARM-options"></a>

  79. 

  80. <p>These &lsquo;<samp>-m</samp>&rsquo; options are defined for the ARM port:

  81. </p>

  82. <dl compact="compact">

  83. <dt><code>-mabi=<var>name</var></code></dt>

  84. <dd><a name="index-mabi-1"></a>

  85. <p>Generate code for the specified ABI.  Permissible values are: &lsquo;<samp>apcs-gnu</samp>&rsquo;,

  86. &lsquo;<samp>atpcs</samp>&rsquo;, &lsquo;<samp>aapcs</samp>&rsquo;, &lsquo;<samp>aapcs-linux</samp>&rsquo; and &lsquo;<samp>iwmmxt</samp>&rsquo;.

  87. </p>

  88. </dd>

  89. <dt><code>-mapcs-frame</code></dt>

  90. <dd><a name="index-mapcs_002dframe"></a>

  91. <p>Generate a stack frame that is compliant with the ARM Procedure Call

  92. Standard for all functions, even if this is not strictly necessary for

  93. correct execution of the code.  Specifying <samp>-fomit-frame-pointer</samp>

  94. with this option causes the stack frames not to be generated for

  95. leaf functions.  The default is <samp>-mno-apcs-frame</samp>.

  96. This option is deprecated.

  97. </p>

  98. </dd>

  99. <dt><code>-mapcs</code></dt>

  100. <dd><a name="index-mapcs"></a>

  101. <p>This is a synonym for <samp>-mapcs-frame</samp> and is deprecated.

  102. </p>

  103. 

  104. </dd>

  105. <dt><code>-mthumb-interwork</code></dt>

  106. <dd><a name="index-mthumb_002dinterwork"></a>

  107. <p>Generate code that supports calling between the ARM and Thumb

  108. instruction sets.  Without this option, on pre-v5 architectures, the

  109. two instruction sets cannot be reliably used inside one program.  The

  110. default is <samp>-mno-thumb-interwork</samp>, since slightly larger code

  111. is generated when <samp>-mthumb-interwork</samp> is specified.  In AAPCS

  112. configurations this option is meaningless.

  113. </p>

  114. </dd>

  115. <dt><code>-mno-sched-prolog</code></dt>

  116. <dd><a name="index-mno_002dsched_002dprolog"></a>

  117. <a name="index-msched_002dprolog"></a>

  118. <p>Prevent the reordering of instructions in the function prologue, or the

  119. merging of those instruction with the instructions in the function&rsquo;s

  120. body.  This means that all functions start with a recognizable set

  121. of instructions (or in fact one of a choice from a small set of

  122. different function prologues), and this information can be used to

  123. locate the start of functions inside an executable piece of code.  The

  124. default is <samp>-msched-prolog</samp>.

  125. </p>

  126. </dd>

  127. <dt><code>-mfloat-abi=<var>name</var></code></dt>

  128. <dd><a name="index-mfloat_002dabi"></a>

  129. <p>Specifies which floating-point ABI to use.  Permissible values

  130. are: &lsquo;<samp>soft</samp>&rsquo;, &lsquo;<samp>softfp</samp>&rsquo; and &lsquo;<samp>hard</samp>&rsquo;.

  131. </p>

  132. <p>Specifying &lsquo;<samp>soft</samp>&rsquo; causes GCC to generate output containing

  133. library calls for floating-point operations.

  134. &lsquo;<samp>softfp</samp>&rsquo; allows the generation of code using hardware floating-point

  135. instructions, but still uses the soft-float calling conventions.

  136. &lsquo;<samp>hard</samp>&rsquo; allows generation of floating-point instructions

  137. and uses FPU-specific calling conventions.

  138. </p>

  139. <p>The default depends on the specific target configuration.  Note that

  140. the hard-float and soft-float ABIs are not link-compatible; you must

  141. compile your entire program with the same ABI, and link with a

  142. compatible set of libraries.

  143. </p>

  144. </dd>

  145. <dt><code>-mgeneral-regs-only</code></dt>

  146. <dd><a name="index-mgeneral_002dregs_002donly-1"></a>

  147. <p>Generate code which uses only the general-purpose registers.  This will prevent

  148. the compiler from using floating-point and Advanced SIMD registers but will not

  149. impose any restrictions on the assembler.

  150. </p>

  151. </dd>

  152. <dt><code>-mlittle-endian</code></dt>

  153. <dd><a name="index-mlittle_002dendian-2"></a>

  154. <p>Generate code for a processor running in little-endian mode.  This is

  155. the default for all standard configurations.

  156. </p>

  157. </dd>

  158. <dt><code>-mbig-endian</code></dt>

  159. <dd><a name="index-mbig_002dendian-2"></a>

  160. <p>Generate code for a processor running in big-endian mode; the default is

  161. to compile code for a little-endian processor.

  162. </p>

  163. </dd>

  164. <dt><code>-mbe8</code></dt>

  165. <dt><code>-mbe32</code></dt>

  166. <dd><a name="index-mbe8"></a>

  167. <p>When linking a big-endian image select between BE8 and BE32 formats.

  168. The option has no effect for little-endian images and is ignored.  The

  169. default is dependent on the selected target architecture.  For ARMv6

  170. and later architectures the default is BE8, for older architectures

  171. the default is BE32.  BE32 format has been deprecated by ARM.

  172. </p>

  173. </dd>

  174. <dt><code>-march=<var>name</var><span class="roman">[</span>+extension&hellip;<span class="roman">]</span></code></dt>

  175. <dd><a name="index-march-2"></a>

  176. <p>This specifies the name of the target ARM architecture.  GCC uses this

  177. name to determine what kind of instructions it can emit when generating

  178. assembly code.  This option can be used in conjunction with or instead

  179. of the <samp>-mcpu=</samp> option.

  180. </p>

  181. <p>Permissible names are:

  182. &lsquo;<samp>armv4t</samp>&rsquo;,

  183. &lsquo;<samp>armv5t</samp>&rsquo;, &lsquo;<samp>armv5te</samp>&rsquo;,

  184. &lsquo;<samp>armv6</samp>&rsquo;, &lsquo;<samp>armv6j</samp>&rsquo;, &lsquo;<samp>armv6k</samp>&rsquo;, &lsquo;<samp>armv6kz</samp>&rsquo;, &lsquo;<samp>armv6t2</samp>&rsquo;,

  185. &lsquo;<samp>armv6z</samp>&rsquo;, &lsquo;<samp>armv6zk</samp>&rsquo;,

  186. &lsquo;<samp>armv7</samp>&rsquo;, &lsquo;<samp>armv7-a</samp>&rsquo;, &lsquo;<samp>armv7ve</samp>&rsquo;, 

  187. &lsquo;<samp>armv8-a</samp>&rsquo;, &lsquo;<samp>armv8.1-a</samp>&rsquo;, &lsquo;<samp>armv8.2-a</samp>&rsquo;, &lsquo;<samp>armv8.3-a</samp>&rsquo;,

  188. &lsquo;<samp>armv8.4-a</samp>&rsquo;,

  189. &lsquo;<samp>armv8.5-a</samp>&rsquo;,

  190. &lsquo;<samp>armv8.6-a</samp>&rsquo;,

  191. &lsquo;<samp>armv7-r</samp>&rsquo;,

  192. &lsquo;<samp>armv8-r</samp>&rsquo;,

  193. &lsquo;<samp>armv6-m</samp>&rsquo;, &lsquo;<samp>armv6s-m</samp>&rsquo;,

  194. &lsquo;<samp>armv7-m</samp>&rsquo;, &lsquo;<samp>armv7e-m</samp>&rsquo;,

  195. &lsquo;<samp>armv8-m.base</samp>&rsquo;, &lsquo;<samp>armv8-m.main</samp>&rsquo;,

  196. &lsquo;<samp>armv8.1-m.main</samp>&rsquo;,

  197. &lsquo;<samp>iwmmxt</samp>&rsquo; and &lsquo;<samp>iwmmxt2</samp>&rsquo;.

  198. </p>

  199. <p>Additionally, the following architectures, which lack support for the

  200. Thumb execution state, are recognized but support is deprecated: &lsquo;<samp>armv4</samp>&rsquo;.

  201. </p>

  202. <p>Many of the architectures support extensions.  These can be added by

  203. appending &lsquo;<samp>+<var>extension</var></samp>&rsquo; to the architecture name.  Extension

  204. options are processed in order and capabilities accumulate.  An extension

  205. will also enable any necessary base extensions

  206. upon which it depends.  For example, the &lsquo;<samp>+crypto</samp>&rsquo; extension

  207. will always enable the &lsquo;<samp>+simd</samp>&rsquo; extension.  The exception to the

  208. additive construction is for extensions that are prefixed with

  209. &lsquo;<samp>+no&hellip;</samp>&rsquo;: these extensions disable the specified option and

  210. any other extensions that may depend on the presence of that

  211. extension.

  212. </p>

  213. <p>For example, &lsquo;<samp>-march=armv7-a+simd+nofp+vfpv4</samp>&rsquo; is equivalent to

  214. writing &lsquo;<samp>-march=armv7-a+vfpv4</samp>&rsquo; since the &lsquo;<samp>+simd</samp>&rsquo; option is

  215. entirely disabled by the &lsquo;<samp>+nofp</samp>&rsquo; option that follows it.

  216. </p>

  217. <p>Most extension names are generically named, but have an effect that is

  218. dependent upon the architecture to which it is applied.  For example,

  219. the &lsquo;<samp>+simd</samp>&rsquo; option can be applied to both &lsquo;<samp>armv7-a</samp>&rsquo; and

  220. &lsquo;<samp>armv8-a</samp>&rsquo; architectures, but will enable the original ARMv7-A

  221. Advanced SIMD (Neon) extensions for &lsquo;<samp>armv7-a</samp>&rsquo; and the ARMv8-A

  222. variant for &lsquo;<samp>armv8-a</samp>&rsquo;.

  223. </p>

  224. <p>The table below lists the supported extensions for each architecture.

  225. Architectures not mentioned do not support any extensions.

  226. </p>

  227. <dl compact="compact">

  228. <dt>&lsquo;<samp>armv5te</samp>&rsquo;</dt>

  229. <dt>&lsquo;<samp>armv6</samp>&rsquo;</dt>

  230. <dt>&lsquo;<samp>armv6j</samp>&rsquo;</dt>

  231. <dt>&lsquo;<samp>armv6k</samp>&rsquo;</dt>

  232. <dt>&lsquo;<samp>armv6kz</samp>&rsquo;</dt>

  233. <dt>&lsquo;<samp>armv6t2</samp>&rsquo;</dt>

  234. <dt>&lsquo;<samp>armv6z</samp>&rsquo;</dt>

  235. <dt>&lsquo;<samp>armv6zk</samp>&rsquo;</dt>

  236. <dd><dl compact="compact">

  237. <dt>&lsquo;<samp>+fp</samp>&rsquo;</dt>

  238. <dd><p>The VFPv2 floating-point instructions.  The extension &lsquo;<samp>+vfpv2</samp>&rsquo; can be

  239. used as an alias for this extension.

  240. </p>

  241. </dd>

  242. <dt>&lsquo;<samp>+nofp</samp>&rsquo;</dt>

  243. <dd><p>Disable the floating-point instructions.

  244. </p></dd>

  245. </dl>

  246. 

  247. </dd>

  248. <dt>&lsquo;<samp>armv7</samp>&rsquo;</dt>

  249. <dd><p>The common subset of the ARMv7-A, ARMv7-R and ARMv7-M architectures.

  250. </p><dl compact="compact">

  251. <dt>&lsquo;<samp>+fp</samp>&rsquo;</dt>

  252. <dd><p>The VFPv3 floating-point instructions, with 16 double-precision

  253. registers.  The extension &lsquo;<samp>+vfpv3-d16</samp>&rsquo; can be used as an alias

  254. for this extension.  Note that floating-point is not supported by the

  255. base ARMv7-M architecture, but is compatible with both the ARMv7-A and

  256. ARMv7-R architectures.

  257. </p>

  258. </dd>

  259. <dt>&lsquo;<samp>+nofp</samp>&rsquo;</dt>

  260. <dd><p>Disable the floating-point instructions.

  261. </p></dd>

  262. </dl>

  263. 

  264. </dd>

  265. <dt>&lsquo;<samp>armv7-a</samp>&rsquo;</dt>

  266. <dd><dl compact="compact">

  267. <dt>&lsquo;<samp>+mp</samp>&rsquo;</dt>

  268. <dd><p>The multiprocessing extension.

  269. </p>

  270. </dd>

  271. <dt>&lsquo;<samp>+sec</samp>&rsquo;</dt>

  272. <dd><p>The security extension.

  273. </p>

  274. </dd>

  275. <dt>&lsquo;<samp>+fp</samp>&rsquo;</dt>

  276. <dd><p>The VFPv3 floating-point instructions, with 16 double-precision

  277. registers.  The extension &lsquo;<samp>+vfpv3-d16</samp>&rsquo; can be used as an alias

  278. for this extension.

  279. </p>

  280. </dd>

  281. <dt>&lsquo;<samp>+simd</samp>&rsquo;</dt>

  282. <dd><p>The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions.

  283. The extensions &lsquo;<samp>+neon</samp>&rsquo; and &lsquo;<samp>+neon-vfpv3</samp>&rsquo; can be used as aliases

  284. for this extension.

  285. </p>

  286. </dd>

  287. <dt>&lsquo;<samp>+vfpv3</samp>&rsquo;</dt>

  288. <dd><p>The VFPv3 floating-point instructions, with 32 double-precision

  289. registers.

  290. </p>

  291. </dd>

  292. <dt>&lsquo;<samp>+vfpv3-d16-fp16</samp>&rsquo;</dt>

  293. <dd><p>The VFPv3 floating-point instructions, with 16 double-precision

  294. registers and the half-precision floating-point conversion operations.

  295. </p>

  296. </dd>

  297. <dt>&lsquo;<samp>+vfpv3-fp16</samp>&rsquo;</dt>

  298. <dd><p>The VFPv3 floating-point instructions, with 32 double-precision

  299. registers and the half-precision floating-point conversion operations.

  300. </p>

  301. </dd>

  302. <dt>&lsquo;<samp>+vfpv4-d16</samp>&rsquo;</dt>

  303. <dd><p>The VFPv4 floating-point instructions, with 16 double-precision

  304. registers.

  305. </p>

  306. </dd>

  307. <dt>&lsquo;<samp>+vfpv4</samp>&rsquo;</dt>

  308. <dd><p>The VFPv4 floating-point instructions, with 32 double-precision

  309. registers.

  310. </p>

  311. </dd>

  312. <dt>&lsquo;<samp>+neon-fp16</samp>&rsquo;</dt>

  313. <dd><p>The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions, with

  314. the half-precision floating-point conversion operations.

  315. </p>

  316. </dd>

  317. <dt>&lsquo;<samp>+neon-vfpv4</samp>&rsquo;</dt>

  318. <dd><p>The Advanced SIMD (Neon) v2 and the VFPv4 floating-point instructions.

  319. </p>

  320. </dd>

  321. <dt>&lsquo;<samp>+nosimd</samp>&rsquo;</dt>

  322. <dd><p>Disable the Advanced SIMD instructions (does not disable floating point).

  323. </p>

  324. </dd>

  325. <dt>&lsquo;<samp>+nofp</samp>&rsquo;</dt>

  326. <dd><p>Disable the floating-point and Advanced SIMD instructions.

  327. </p></dd>

  328. </dl>

  329. 

  330. </dd>

  331. <dt>&lsquo;<samp>armv7ve</samp>&rsquo;</dt>

  332. <dd><p>The extended version of the ARMv7-A architecture with support for

  333. virtualization.

  334. </p><dl compact="compact">

  335. <dt>&lsquo;<samp>+fp</samp>&rsquo;</dt>

  336. <dd><p>The VFPv4 floating-point instructions, with 16 double-precision registers.

  337. The extension &lsquo;<samp>+vfpv4-d16</samp>&rsquo; can be used as an alias for this extension.

  338. </p>

  339. </dd>

  340. <dt>&lsquo;<samp>+simd</samp>&rsquo;</dt>

  341. <dd><p>The Advanced SIMD (Neon) v2 and the VFPv4 floating-point instructions.  The

  342. extension &lsquo;<samp>+neon-vfpv4</samp>&rsquo; can be used as an alias for this extension.

  343. </p>

  344. </dd>

  345. <dt>&lsquo;<samp>+vfpv3-d16</samp>&rsquo;</dt>

  346. <dd><p>The VFPv3 floating-point instructions, with 16 double-precision

  347. registers.

  348. </p>

  349. </dd>

  350. <dt>&lsquo;<samp>+vfpv3</samp>&rsquo;</dt>

  351. <dd><p>The VFPv3 floating-point instructions, with 32 double-precision

  352. registers.

  353. </p>

  354. </dd>

  355. <dt>&lsquo;<samp>+vfpv3-d16-fp16</samp>&rsquo;</dt>

  356. <dd><p>The VFPv3 floating-point instructions, with 16 double-precision

  357. registers and the half-precision floating-point conversion operations.

  358. </p>

  359. </dd>

  360. <dt>&lsquo;<samp>+vfpv3-fp16</samp>&rsquo;</dt>

  361. <dd><p>The VFPv3 floating-point instructions, with 32 double-precision

  362. registers and the half-precision floating-point conversion operations.

  363. </p>

  364. </dd>

  365. <dt>&lsquo;<samp>+vfpv4-d16</samp>&rsquo;</dt>

  366. <dd><p>The VFPv4 floating-point instructions, with 16 double-precision

  367. registers.

  368. </p>

  369. </dd>

  370. <dt>&lsquo;<samp>+vfpv4</samp>&rsquo;</dt>

  371. <dd><p>The VFPv4 floating-point instructions, with 32 double-precision

  372. registers.

  373. </p>

  374. </dd>

  375. <dt>&lsquo;<samp>+neon</samp>&rsquo;</dt>

  376. <dd><p>The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions.

  377. The extension &lsquo;<samp>+neon-vfpv3</samp>&rsquo; can be used as an alias for this extension.

  378. </p>

  379. </dd>

  380. <dt>&lsquo;<samp>+neon-fp16</samp>&rsquo;</dt>

  381. <dd><p>The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions, with

  382. the half-precision floating-point conversion operations.

  383. </p>

  384. </dd>

  385. <dt>&lsquo;<samp>+nosimd</samp>&rsquo;</dt>

  386. <dd><p>Disable the Advanced SIMD instructions (does not disable floating point).

  387. </p>

  388. </dd>

  389. <dt>&lsquo;<samp>+nofp</samp>&rsquo;</dt>

  390. <dd><p>Disable the floating-point and Advanced SIMD instructions.

  391. </p></dd>

  392. </dl>

  393. 

  394. </dd>

  395. <dt>&lsquo;<samp>armv8-a</samp>&rsquo;</dt>

  396. <dd><dl compact="compact">

  397. <dt>&lsquo;<samp>+crc</samp>&rsquo;</dt>

  398. <dd><p>The Cyclic Redundancy Check (CRC) instructions.

  399. </p></dd>

  400. <dt>&lsquo;<samp>+simd</samp>&rsquo;</dt>

  401. <dd><p>The ARMv8-A Advanced SIMD and floating-point instructions.

  402. </p></dd>

  403. <dt>&lsquo;<samp>+crypto</samp>&rsquo;</dt>

  404. <dd><p>The cryptographic instructions.

  405. </p></dd>

  406. <dt>&lsquo;<samp>+nocrypto</samp>&rsquo;</dt>

  407. <dd><p>Disable the cryptographic instructions.

  408. </p></dd>

  409. <dt>&lsquo;<samp>+nofp</samp>&rsquo;</dt>

  410. <dd><p>Disable the floating-point, Advanced SIMD and cryptographic instructions.

  411. </p></dd>

  412. <dt>&lsquo;<samp>+sb</samp>&rsquo;</dt>

  413. <dd><p>Speculation Barrier Instruction.

  414. </p></dd>

  415. <dt>&lsquo;<samp>+predres</samp>&rsquo;</dt>

  416. <dd><p>Execution and Data Prediction Restriction Instructions.

  417. </p></dd>

  418. </dl>

  419. 

  420. </dd>

  421. <dt>&lsquo;<samp>armv8.1-a</samp>&rsquo;</dt>

  422. <dd><dl compact="compact">

  423. <dt>&lsquo;<samp>+simd</samp>&rsquo;</dt>

  424. <dd><p>The ARMv8.1-A Advanced SIMD and floating-point instructions.

  425. </p>

  426. </dd>

  427. <dt>&lsquo;<samp>+crypto</samp>&rsquo;</dt>

  428. <dd><p>The cryptographic instructions.  This also enables the Advanced SIMD and

  429. floating-point instructions.

  430. </p>

  431. </dd>

  432. <dt>&lsquo;<samp>+nocrypto</samp>&rsquo;</dt>

  433. <dd><p>Disable the cryptographic instructions.

  434. </p>

  435. </dd>

  436. <dt>&lsquo;<samp>+nofp</samp>&rsquo;</dt>

  437. <dd><p>Disable the floating-point, Advanced SIMD and cryptographic instructions.

  438. </p>

  439. </dd>

  440. <dt>&lsquo;<samp>+sb</samp>&rsquo;</dt>

  441. <dd><p>Speculation Barrier Instruction.

  442. </p>

  443. </dd>

  444. <dt>&lsquo;<samp>+predres</samp>&rsquo;</dt>

  445. <dd><p>Execution and Data Prediction Restriction Instructions.

  446. </p></dd>

  447. </dl>

  448. 

  449. </dd>

  450. <dt>&lsquo;<samp>armv8.2-a</samp>&rsquo;</dt>

  451. <dt>&lsquo;<samp>armv8.3-a</samp>&rsquo;</dt>

  452. <dd><dl compact="compact">

  453. <dt>&lsquo;<samp>+fp16</samp>&rsquo;</dt>

  454. <dd><p>The half-precision floating-point data processing instructions.

  455. This also enables the Advanced SIMD and floating-point instructions.

  456. </p>

  457. </dd>

  458. <dt>&lsquo;<samp>+fp16fml</samp>&rsquo;</dt>

  459. <dd><p>The half-precision floating-point fmla extension.  This also enables

  460. the half-precision floating-point extension and Advanced SIMD and

  461. floating-point instructions.

  462. </p>

  463. </dd>

  464. <dt>&lsquo;<samp>+simd</samp>&rsquo;</dt>

  465. <dd><p>The ARMv8.1-A Advanced SIMD and floating-point instructions.

  466. </p>

  467. </dd>

  468. <dt>&lsquo;<samp>+crypto</samp>&rsquo;</dt>

  469. <dd><p>The cryptographic instructions.  This also enables the Advanced SIMD and

  470. floating-point instructions.

  471. </p>

  472. </dd>

  473. <dt>&lsquo;<samp>+dotprod</samp>&rsquo;</dt>

  474. <dd><p>Enable the Dot Product extension.  This also enables Advanced SIMD instructions.

  475. </p>

  476. </dd>

  477. <dt>&lsquo;<samp>+nocrypto</samp>&rsquo;</dt>

  478. <dd><p>Disable the cryptographic extension.

  479. </p>

  480. </dd>

  481. <dt>&lsquo;<samp>+nofp</samp>&rsquo;</dt>

  482. <dd><p>Disable the floating-point, Advanced SIMD and cryptographic instructions.

  483. </p>

  484. </dd>

  485. <dt>&lsquo;<samp>+sb</samp>&rsquo;</dt>

  486. <dd><p>Speculation Barrier Instruction.

  487. </p>

  488. </dd>

  489. <dt>&lsquo;<samp>+predres</samp>&rsquo;</dt>

  490. <dd><p>Execution and Data Prediction Restriction Instructions.

  491. </p>

  492. </dd>

  493. <dt>&lsquo;<samp>+i8mm</samp>&rsquo;</dt>

  494. <dd><p>8-bit Integer Matrix Multiply instructions.

  495. This also enables Advanced SIMD and floating-point instructions.

  496. </p>

  497. </dd>

  498. <dt>&lsquo;<samp>+bf16</samp>&rsquo;</dt>

  499. <dd><p>Brain half-precision floating-point instructions.

  500. This also enables Advanced SIMD and floating-point instructions.

  501. </p></dd>

  502. </dl>

  503. 

  504. </dd>

  505. <dt>&lsquo;<samp>armv8.4-a</samp>&rsquo;</dt>

  506. <dd><dl compact="compact">

  507. <dt>&lsquo;<samp>+fp16</samp>&rsquo;</dt>

  508. <dd><p>The half-precision floating-point data processing instructions.

  509. This also enables the Advanced SIMD and floating-point instructions as well

  510. as the Dot Product extension and the half-precision floating-point fmla

  511. extension.

  512. </p>

  513. </dd>

  514. <dt>&lsquo;<samp>+simd</samp>&rsquo;</dt>

  515. <dd><p>The ARMv8.3-A Advanced SIMD and floating-point instructions as well as the

  516. Dot Product extension.

  517. </p>

  518. </dd>

  519. <dt>&lsquo;<samp>+crypto</samp>&rsquo;</dt>

  520. <dd><p>The cryptographic instructions.  This also enables the Advanced SIMD and

  521. floating-point instructions as well as the Dot Product extension.

  522. </p>

  523. </dd>

  524. <dt>&lsquo;<samp>+nocrypto</samp>&rsquo;</dt>

  525. <dd><p>Disable the cryptographic extension.

  526. </p>

  527. </dd>

  528. <dt>&lsquo;<samp>+nofp</samp>&rsquo;</dt>

  529. <dd><p>Disable the floating-point, Advanced SIMD and cryptographic instructions.

  530. </p>

  531. </dd>

  532. <dt>&lsquo;<samp>+sb</samp>&rsquo;</dt>

  533. <dd><p>Speculation Barrier Instruction.

  534. </p>

  535. </dd>

  536. <dt>&lsquo;<samp>+predres</samp>&rsquo;</dt>

  537. <dd><p>Execution and Data Prediction Restriction Instructions.

  538. </p>

  539. </dd>

  540. <dt>&lsquo;<samp>+i8mm</samp>&rsquo;</dt>

  541. <dd><p>8-bit Integer Matrix Multiply instructions.

  542. This also enables Advanced SIMD and floating-point instructions.

  543. </p>

  544. </dd>

  545. <dt>&lsquo;<samp>+bf16</samp>&rsquo;</dt>

  546. <dd><p>Brain half-precision floating-point instructions.

  547. This also enables Advanced SIMD and floating-point instructions.

  548. </p></dd>

  549. </dl>

  550. 

  551. </dd>

  552. <dt>&lsquo;<samp>armv8.5-a</samp>&rsquo;</dt>

  553. <dd><dl compact="compact">

  554. <dt>&lsquo;<samp>+fp16</samp>&rsquo;</dt>

  555. <dd><p>The half-precision floating-point data processing instructions.

  556. This also enables the Advanced SIMD and floating-point instructions as well

  557. as the Dot Product extension and the half-precision floating-point fmla

  558. extension.

  559. </p>

  560. </dd>

  561. <dt>&lsquo;<samp>+simd</samp>&rsquo;</dt>

  562. <dd><p>The ARMv8.3-A Advanced SIMD and floating-point instructions as well as the

  563. Dot Product extension.

  564. </p>

  565. </dd>

  566. <dt>&lsquo;<samp>+crypto</samp>&rsquo;</dt>

  567. <dd><p>The cryptographic instructions.  This also enables the Advanced SIMD and

  568. floating-point instructions as well as the Dot Product extension.

  569. </p>

  570. </dd>

  571. <dt>&lsquo;<samp>+nocrypto</samp>&rsquo;</dt>

  572. <dd><p>Disable the cryptographic extension.

  573. </p>

  574. </dd>

  575. <dt>&lsquo;<samp>+nofp</samp>&rsquo;</dt>

  576. <dd><p>Disable the floating-point, Advanced SIMD and cryptographic instructions.

  577. </p>

  578. </dd>

  579. <dt>&lsquo;<samp>+i8mm</samp>&rsquo;</dt>

  580. <dd><p>8-bit Integer Matrix Multiply instructions.

  581. This also enables Advanced SIMD and floating-point instructions.

  582. </p>

  583. </dd>

  584. <dt>&lsquo;<samp>+bf16</samp>&rsquo;</dt>

  585. <dd><p>Brain half-precision floating-point instructions.

  586. This also enables Advanced SIMD and floating-point instructions.

  587. </p></dd>

  588. </dl>

  589. 

  590. </dd>

  591. <dt>&lsquo;<samp>armv8.6-a</samp>&rsquo;</dt>

  592. <dd><dl compact="compact">

  593. <dt>&lsquo;<samp>+fp16</samp>&rsquo;</dt>

  594. <dd><p>The half-precision floating-point data processing instructions.

  595. This also enables the Advanced SIMD and floating-point instructions as well

  596. as the Dot Product extension and the half-precision floating-point fmla

  597. extension.

  598. </p>

  599. </dd>

  600. <dt>&lsquo;<samp>+simd</samp>&rsquo;</dt>

  601. <dd><p>The ARMv8.3-A Advanced SIMD and floating-point instructions as well as the

  602. Dot Product extension.

  603. </p>

  604. </dd>

  605. <dt>&lsquo;<samp>+crypto</samp>&rsquo;</dt>

  606. <dd><p>The cryptographic instructions.  This also enables the Advanced SIMD and

  607. floating-point instructions as well as the Dot Product extension.

  608. </p>

  609. </dd>

  610. <dt>&lsquo;<samp>+nocrypto</samp>&rsquo;</dt>

  611. <dd><p>Disable the cryptographic extension.

  612. </p>

  613. </dd>

  614. <dt>&lsquo;<samp>+nofp</samp>&rsquo;</dt>

  615. <dd><p>Disable the floating-point, Advanced SIMD and cryptographic instructions.

  616. </p>

  617. </dd>

  618. <dt>&lsquo;<samp>+i8mm</samp>&rsquo;</dt>

  619. <dd><p>8-bit Integer Matrix Multiply instructions.

  620. This also enables Advanced SIMD and floating-point instructions.

  621. </p>

  622. </dd>

  623. <dt>&lsquo;<samp>+bf16</samp>&rsquo;</dt>

  624. <dd><p>Brain half-precision floating-point instructions.

  625. This also enables Advanced SIMD and floating-point instructions.

  626. </p></dd>

  627. </dl>

  628. 

  629. </dd>

  630. <dt>&lsquo;<samp>armv7-r</samp>&rsquo;</dt>

  631. <dd><dl compact="compact">

  632. <dt>&lsquo;<samp>+fp.sp</samp>&rsquo;</dt>

  633. <dd><p>The single-precision VFPv3 floating-point instructions.  The extension

  634. &lsquo;<samp>+vfpv3xd</samp>&rsquo; can be used as an alias for this extension.

  635. </p>

  636. </dd>

  637. <dt>&lsquo;<samp>+fp</samp>&rsquo;</dt>

  638. <dd><p>The VFPv3 floating-point instructions with 16 double-precision registers.

  639. The extension +vfpv3-d16 can be used as an alias for this extension.

  640. </p>

  641. </dd>

  642. <dt>&lsquo;<samp>+vfpv3xd-d16-fp16</samp>&rsquo;</dt>

  643. <dd><p>The single-precision VFPv3 floating-point instructions with 16 double-precision

  644. registers and the half-precision floating-point conversion operations.

  645. </p>

  646. </dd>

  647. <dt>&lsquo;<samp>+vfpv3-d16-fp16</samp>&rsquo;</dt>

  648. <dd><p>The VFPv3 floating-point instructions with 16 double-precision

  649. registers and the half-precision floating-point conversion operations.

  650. </p>

  651. </dd>

  652. <dt>&lsquo;<samp>+nofp</samp>&rsquo;</dt>

  653. <dd><p>Disable the floating-point extension.

  654. </p>

  655. </dd>

  656. <dt>&lsquo;<samp>+idiv</samp>&rsquo;</dt>

  657. <dd><p>The ARM-state integer division instructions.

  658. </p>

  659. </dd>

  660. <dt>&lsquo;<samp>+noidiv</samp>&rsquo;</dt>

  661. <dd><p>Disable the ARM-state integer division extension.

  662. </p></dd>

  663. </dl>

  664. 

  665. </dd>

  666. <dt>&lsquo;<samp>armv7e-m</samp>&rsquo;</dt>

  667. <dd><dl compact="compact">

  668. <dt>&lsquo;<samp>+fp</samp>&rsquo;</dt>

  669. <dd><p>The single-precision VFPv4 floating-point instructions.

  670. </p>

  671. </dd>

  672. <dt>&lsquo;<samp>+fpv5</samp>&rsquo;</dt>

  673. <dd><p>The single-precision FPv5 floating-point instructions.

  674. </p>

  675. </dd>

  676. <dt>&lsquo;<samp>+fp.dp</samp>&rsquo;</dt>

  677. <dd><p>The single- and double-precision FPv5 floating-point instructions.

  678. </p>

  679. </dd>

  680. <dt>&lsquo;<samp>+nofp</samp>&rsquo;</dt>

  681. <dd><p>Disable the floating-point extensions.

  682. </p></dd>

  683. </dl>

  684. 

  685. </dd>

  686. <dt>&lsquo;<samp>armv8.1-m.main</samp>&rsquo;</dt>

  687. <dd><dl compact="compact">

  688. <dt>&lsquo;<samp>+dsp</samp>&rsquo;</dt>

  689. <dd><p>The DSP instructions.

  690. </p>

  691. </dd>

  692. <dt>&lsquo;<samp>+mve</samp>&rsquo;</dt>

  693. <dd><p>The M-Profile Vector Extension (MVE) integer instructions.

  694. </p>

  695. </dd>

  696. <dt>&lsquo;<samp>+mve.fp</samp>&rsquo;</dt>

  697. <dd><p>The M-Profile Vector Extension (MVE) integer and single precision

  698. floating-point instructions.

  699. </p>

  700. </dd>

  701. <dt>&lsquo;<samp>+fp</samp>&rsquo;</dt>

  702. <dd><p>The single-precision floating-point instructions.

  703. </p>

  704. </dd>

  705. <dt>&lsquo;<samp>+fp.dp</samp>&rsquo;</dt>

  706. <dd><p>The single- and double-precision floating-point instructions.

  707. </p>

  708. </dd>

  709. <dt>&lsquo;<samp>+nofp</samp>&rsquo;</dt>

  710. <dd><p>Disable the floating-point extension.

  711. </p>

  712. </dd>

  713. <dt>&lsquo;<samp>+cdecp0, +cdecp1, ... , +cdecp7</samp>&rsquo;</dt>

  714. <dd><p>Enable the Custom Datapath Extension (CDE) on selected coprocessors according

  715. to the numbers given in the options in the range 0 to 7.

  716. </p></dd>

  717. </dl>

  718. 

  719. </dd>

  720. <dt>&lsquo;<samp>armv8-m.main</samp>&rsquo;</dt>

  721. <dd><dl compact="compact">

  722. <dt>&lsquo;<samp>+dsp</samp>&rsquo;</dt>

  723. <dd><p>The DSP instructions.

  724. </p>

  725. </dd>

  726. <dt>&lsquo;<samp>+nodsp</samp>&rsquo;</dt>

  727. <dd><p>Disable the DSP extension.

  728. </p>

  729. </dd>

  730. <dt>&lsquo;<samp>+fp</samp>&rsquo;</dt>

  731. <dd><p>The single-precision floating-point instructions.

  732. </p>

  733. </dd>

  734. <dt>&lsquo;<samp>+fp.dp</samp>&rsquo;</dt>

  735. <dd><p>The single- and double-precision floating-point instructions.

  736. </p>

  737. </dd>

  738. <dt>&lsquo;<samp>+nofp</samp>&rsquo;</dt>

  739. <dd><p>Disable the floating-point extension.

  740. </p>

  741. </dd>

  742. <dt>&lsquo;<samp>+cdecp0, +cdecp1, ... , +cdecp7</samp>&rsquo;</dt>

  743. <dd><p>Enable the Custom Datapath Extension (CDE) on selected coprocessors according

  744. to the numbers given in the options in the range 0 to 7.

  745. </p></dd>

  746. </dl>

  747. 

  748. </dd>

  749. <dt>&lsquo;<samp>armv8-r</samp>&rsquo;</dt>

  750. <dd><dl compact="compact">

  751. <dt>&lsquo;<samp>+crc</samp>&rsquo;</dt>

  752. <dd><p>The Cyclic Redundancy Check (CRC) instructions.

  753. </p></dd>

  754. <dt>&lsquo;<samp>+fp.sp</samp>&rsquo;</dt>

  755. <dd><p>The single-precision FPv5 floating-point instructions.

  756. </p></dd>

  757. <dt>&lsquo;<samp>+simd</samp>&rsquo;</dt>

  758. <dd><p>The ARMv8-A Advanced SIMD and floating-point instructions.

  759. </p></dd>

  760. <dt>&lsquo;<samp>+crypto</samp>&rsquo;</dt>

  761. <dd><p>The cryptographic instructions.

  762. </p></dd>

  763. <dt>&lsquo;<samp>+nocrypto</samp>&rsquo;</dt>

  764. <dd><p>Disable the cryptographic instructions.

  765. </p></dd>

  766. <dt>&lsquo;<samp>+nofp</samp>&rsquo;</dt>

  767. <dd><p>Disable the floating-point, Advanced SIMD and cryptographic instructions.

  768. </p></dd>

  769. </dl>

  770. 

  771. </dd>

  772. </dl>

  773. 

  774. <p><samp>-march=native</samp> causes the compiler to auto-detect the architecture

  775. of the build computer.  At present, this feature is only supported on

  776. GNU/Linux, and not all architectures are recognized.  If the auto-detect

  777. is unsuccessful the option has no effect.

  778. </p>

  779. </dd>

  780. <dt><code>-mtune=<var>name</var></code></dt>

  781. <dd><a name="index-mtune-4"></a>

  782. <p>This option specifies the name of the target ARM processor for

  783. which GCC should tune the performance of the code.

  784. For some ARM implementations better performance can be obtained by using

  785. this option.

  786. Permissible names are: &lsquo;<samp>arm7tdmi</samp>&rsquo;, &lsquo;<samp>arm7tdmi-s</samp>&rsquo;, &lsquo;<samp>arm710t</samp>&rsquo;,

  787. &lsquo;<samp>arm720t</samp>&rsquo;, &lsquo;<samp>arm740t</samp>&rsquo;, &lsquo;<samp>strongarm</samp>&rsquo;, &lsquo;<samp>strongarm110</samp>&rsquo;,

  788. &lsquo;<samp>strongarm1100</samp>&rsquo;, 0&lsquo;<samp>strongarm1110</samp>&rsquo;, &lsquo;<samp>arm8</samp>&rsquo;, &lsquo;<samp>arm810</samp>&rsquo;,

  789. &lsquo;<samp>arm9</samp>&rsquo;, &lsquo;<samp>arm9e</samp>&rsquo;, &lsquo;<samp>arm920</samp>&rsquo;, &lsquo;<samp>arm920t</samp>&rsquo;, &lsquo;<samp>arm922t</samp>&rsquo;,

  790. &lsquo;<samp>arm946e-s</samp>&rsquo;, &lsquo;<samp>arm966e-s</samp>&rsquo;, &lsquo;<samp>arm968e-s</samp>&rsquo;, &lsquo;<samp>arm926ej-s</samp>&rsquo;,

  791. &lsquo;<samp>arm940t</samp>&rsquo;, &lsquo;<samp>arm9tdmi</samp>&rsquo;, &lsquo;<samp>arm10tdmi</samp>&rsquo;, &lsquo;<samp>arm1020t</samp>&rsquo;,

  792. &lsquo;<samp>arm1026ej-s</samp>&rsquo;, &lsquo;<samp>arm10e</samp>&rsquo;, &lsquo;<samp>arm1020e</samp>&rsquo;, &lsquo;<samp>arm1022e</samp>&rsquo;,

  793. &lsquo;<samp>arm1136j-s</samp>&rsquo;, &lsquo;<samp>arm1136jf-s</samp>&rsquo;, &lsquo;<samp>mpcore</samp>&rsquo;, &lsquo;<samp>mpcorenovfp</samp>&rsquo;,

  794. &lsquo;<samp>arm1156t2-s</samp>&rsquo;, &lsquo;<samp>arm1156t2f-s</samp>&rsquo;, &lsquo;<samp>arm1176jz-s</samp>&rsquo;, &lsquo;<samp>arm1176jzf-s</samp>&rsquo;,

  795. &lsquo;<samp>generic-armv7-a</samp>&rsquo;, &lsquo;<samp>cortex-a5</samp>&rsquo;, &lsquo;<samp>cortex-a7</samp>&rsquo;, &lsquo;<samp>cortex-a8</samp>&rsquo;,

  796. &lsquo;<samp>cortex-a9</samp>&rsquo;, &lsquo;<samp>cortex-a12</samp>&rsquo;, &lsquo;<samp>cortex-a15</samp>&rsquo;, &lsquo;<samp>cortex-a17</samp>&rsquo;,

  797. &lsquo;<samp>cortex-a32</samp>&rsquo;, &lsquo;<samp>cortex-a35</samp>&rsquo;, &lsquo;<samp>cortex-a53</samp>&rsquo;, &lsquo;<samp>cortex-a55</samp>&rsquo;,

  798. &lsquo;<samp>cortex-a57</samp>&rsquo;, &lsquo;<samp>cortex-a72</samp>&rsquo;, &lsquo;<samp>cortex-a73</samp>&rsquo;, &lsquo;<samp>cortex-a75</samp>&rsquo;,

  799. &lsquo;<samp>cortex-a76</samp>&rsquo;, &lsquo;<samp>cortex-a76ae</samp>&rsquo;, &lsquo;<samp>cortex-a77</samp>&rsquo;,

  800. &lsquo;<samp>ares</samp>&rsquo;, &lsquo;<samp>cortex-r4</samp>&rsquo;, &lsquo;<samp>cortex-r4f</samp>&rsquo;,

  801. &lsquo;<samp>cortex-r5</samp>&rsquo;, &lsquo;<samp>cortex-r7</samp>&rsquo;, &lsquo;<samp>cortex-r8</samp>&rsquo;, &lsquo;<samp>cortex-r52</samp>&rsquo;,

  802. &lsquo;<samp>cortex-m0</samp>&rsquo;, &lsquo;<samp>cortex-m0plus</samp>&rsquo;, &lsquo;<samp>cortex-m1</samp>&rsquo;, &lsquo;<samp>cortex-m3</samp>&rsquo;,

  803. &lsquo;<samp>cortex-m4</samp>&rsquo;, &lsquo;<samp>cortex-m7</samp>&rsquo;, &lsquo;<samp>cortex-m23</samp>&rsquo;, &lsquo;<samp>cortex-m33</samp>&rsquo;,

  804. &lsquo;<samp>cortex-m35p</samp>&rsquo;, &lsquo;<samp>cortex-m55</samp>&rsquo;,

  805. &lsquo;<samp>cortex-m1.small-multiply</samp>&rsquo;, &lsquo;<samp>cortex-m0.small-multiply</samp>&rsquo;,

  806. &lsquo;<samp>cortex-m0plus.small-multiply</samp>&rsquo;, &lsquo;<samp>exynos-m1</samp>&rsquo;, &lsquo;<samp>marvell-pj4</samp>&rsquo;,

  807. &lsquo;<samp>neoverse-n1</samp>&rsquo;, &lsquo;<samp>neoverse-n2</samp>&rsquo;, &lsquo;<samp>neoverse-v1</samp>&rsquo;, &lsquo;<samp>xscale</samp>&rsquo;,

  808. &lsquo;<samp>iwmmxt</samp>&rsquo;, &lsquo;<samp>iwmmxt2</samp>&rsquo;, &lsquo;<samp>ep9312</samp>&rsquo;, &lsquo;<samp>fa526</samp>&rsquo;, &lsquo;<samp>fa626</samp>&rsquo;,

  809. &lsquo;<samp>fa606te</samp>&rsquo;, &lsquo;<samp>fa626te</samp>&rsquo;, &lsquo;<samp>fmp626</samp>&rsquo;, &lsquo;<samp>fa726te</samp>&rsquo;, &lsquo;<samp>xgene1</samp>&rsquo;.

  810. </p>

  811. <p>Additionally, this option can specify that GCC should tune the performance

  812. of the code for a big.LITTLE system.  Permissible names are:

  813. &lsquo;<samp>cortex-a15.cortex-a7</samp>&rsquo;, &lsquo;<samp>cortex-a17.cortex-a7</samp>&rsquo;,

  814. &lsquo;<samp>cortex-a57.cortex-a53</samp>&rsquo;, &lsquo;<samp>cortex-a72.cortex-a53</samp>&rsquo;,

  815. &lsquo;<samp>cortex-a72.cortex-a35</samp>&rsquo;, &lsquo;<samp>cortex-a73.cortex-a53</samp>&rsquo;,

  816. &lsquo;<samp>cortex-a75.cortex-a55</samp>&rsquo;, &lsquo;<samp>cortex-a76.cortex-a55</samp>&rsquo;.

  817. </p>

  818. <p><samp>-mtune=generic-<var>arch</var></samp> specifies that GCC should tune the

  819. performance for a blend of processors within architecture <var>arch</var>.

  820. The aim is to generate code that run well on the current most popular

  821. processors, balancing between optimizations that benefit some CPUs in the

  822. range, and avoiding performance pitfalls of other CPUs.  The effects of

  823. this option may change in future GCC versions as CPU models come and go.

  824. </p>

  825. <p><samp>-mtune</samp> permits the same extension options as <samp>-mcpu</samp>, but

  826. the extension options do not affect the tuning of the generated code.

  827. </p>

  828. <p><samp>-mtune=native</samp> causes the compiler to auto-detect the CPU

  829. of the build computer.  At present, this feature is only supported on

  830. GNU/Linux, and not all architectures are recognized.  If the auto-detect is

  831. unsuccessful the option has no effect.

  832. </p>

  833. </dd>

  834. <dt><code>-mcpu=<var>name</var><span class="roman">[</span>+extension&hellip;<span class="roman">]</span></code></dt>

  835. <dd><a name="index-mcpu-2"></a>

  836. <p>This specifies the name of the target ARM processor.  GCC uses this name

  837. to derive the name of the target ARM architecture (as if specified

  838. by <samp>-march</samp>) and the ARM processor type for which to tune for

  839. performance (as if specified by <samp>-mtune</samp>).  Where this option

  840. is used in conjunction with <samp>-march</samp> or <samp>-mtune</samp>,

  841. those options take precedence over the appropriate part of this option.

  842. </p>

  843. <p>Many of the supported CPUs implement optional architectural

  844. extensions.  Where this is so the architectural extensions are

  845. normally enabled by default.  If implementations that lack the

  846. extension exist, then the extension syntax can be used to disable

  847. those extensions that have been omitted.  For floating-point and

  848. Advanced SIMD (Neon) instructions, the settings of the options

  849. <samp>-mfloat-abi</samp> and <samp>-mfpu</samp> must also be considered:

  850. floating-point and Advanced SIMD instructions will only be used if

  851. <samp>-mfloat-abi</samp> is not set to &lsquo;<samp>soft</samp>&rsquo;; and any setting of

  852. <samp>-mfpu</samp> other than &lsquo;<samp>auto</samp>&rsquo; will override the available

  853. floating-point and SIMD extension instructions.

  854. </p>

  855. <p>For example, &lsquo;<samp>cortex-a9</samp>&rsquo; can be found in three major

  856. configurations: integer only, with just a floating-point unit or with

  857. floating-point and Advanced SIMD.  The default is to enable all the

  858. instructions, but the extensions &lsquo;<samp>+nosimd</samp>&rsquo; and &lsquo;<samp>+nofp</samp>&rsquo; can

  859. be used to disable just the SIMD or both the SIMD and floating-point

  860. instructions respectively.

  861. </p>

  862. <p>Permissible names for this option are the same as those for

  863. <samp>-mtune</samp>.

  864. </p>

  865. <p>The following extension options are common to the listed CPUs:

  866. </p>

  867. <dl compact="compact">

  868. <dt>&lsquo;<samp>+nodsp</samp>&rsquo;</dt>

  869. <dd><p>Disable the DSP instructions on &lsquo;<samp>cortex-m33</samp>&rsquo;, &lsquo;<samp>cortex-m35p</samp>&rsquo;.

  870. </p>

  871. </dd>

  872. <dt>&lsquo;<samp>+nofp</samp>&rsquo;</dt>

  873. <dd><p>Disables the floating-point instructions on &lsquo;<samp>arm9e</samp>&rsquo;,

  874. &lsquo;<samp>arm946e-s</samp>&rsquo;, &lsquo;<samp>arm966e-s</samp>&rsquo;, &lsquo;<samp>arm968e-s</samp>&rsquo;, &lsquo;<samp>arm10e</samp>&rsquo;,

  875. &lsquo;<samp>arm1020e</samp>&rsquo;, &lsquo;<samp>arm1022e</samp>&rsquo;, &lsquo;<samp>arm926ej-s</samp>&rsquo;,

  876. &lsquo;<samp>arm1026ej-s</samp>&rsquo;, &lsquo;<samp>cortex-r5</samp>&rsquo;, &lsquo;<samp>cortex-r7</samp>&rsquo;, &lsquo;<samp>cortex-r8</samp>&rsquo;,

  877. &lsquo;<samp>cortex-m4</samp>&rsquo;, &lsquo;<samp>cortex-m7</samp>&rsquo;, &lsquo;<samp>cortex-m33</samp>&rsquo; and &lsquo;<samp>cortex-m35p</samp>&rsquo;.

  878. Disables the floating-point and SIMD instructions on

  879. &lsquo;<samp>generic-armv7-a</samp>&rsquo;, &lsquo;<samp>cortex-a5</samp>&rsquo;, &lsquo;<samp>cortex-a7</samp>&rsquo;,

  880. &lsquo;<samp>cortex-a8</samp>&rsquo;, &lsquo;<samp>cortex-a9</samp>&rsquo;, &lsquo;<samp>cortex-a12</samp>&rsquo;,

  881. &lsquo;<samp>cortex-a15</samp>&rsquo;, &lsquo;<samp>cortex-a17</samp>&rsquo;, &lsquo;<samp>cortex-a15.cortex-a7</samp>&rsquo;,

  882. &lsquo;<samp>cortex-a17.cortex-a7</samp>&rsquo;, &lsquo;<samp>cortex-a32</samp>&rsquo;, &lsquo;<samp>cortex-a35</samp>&rsquo;,

  883. &lsquo;<samp>cortex-a53</samp>&rsquo; and &lsquo;<samp>cortex-a55</samp>&rsquo;.

  884. </p>

  885. </dd>

  886. <dt>&lsquo;<samp>+nofp.dp</samp>&rsquo;</dt>

  887. <dd><p>Disables the double-precision component of the floating-point instructions

  888. on &lsquo;<samp>cortex-r5</samp>&rsquo;, &lsquo;<samp>cortex-r7</samp>&rsquo;, &lsquo;<samp>cortex-r8</samp>&rsquo;, &lsquo;<samp>cortex-r52</samp>&rsquo; and

  889. &lsquo;<samp>cortex-m7</samp>&rsquo;.

  890. </p>

  891. </dd>

  892. <dt>&lsquo;<samp>+nosimd</samp>&rsquo;</dt>

  893. <dd><p>Disables the SIMD (but not floating-point) instructions on

  894. &lsquo;<samp>generic-armv7-a</samp>&rsquo;, &lsquo;<samp>cortex-a5</samp>&rsquo;, &lsquo;<samp>cortex-a7</samp>&rsquo;

  895. and &lsquo;<samp>cortex-a9</samp>&rsquo;.

  896. </p>

  897. </dd>

  898. <dt>&lsquo;<samp>+crypto</samp>&rsquo;</dt>

  899. <dd><p>Enables the cryptographic instructions on &lsquo;<samp>cortex-a32</samp>&rsquo;,

  900. &lsquo;<samp>cortex-a35</samp>&rsquo;, &lsquo;<samp>cortex-a53</samp>&rsquo;, &lsquo;<samp>cortex-a55</samp>&rsquo;, &lsquo;<samp>cortex-a57</samp>&rsquo;,

  901. &lsquo;<samp>cortex-a72</samp>&rsquo;, &lsquo;<samp>cortex-a73</samp>&rsquo;, &lsquo;<samp>cortex-a75</samp>&rsquo;, &lsquo;<samp>exynos-m1</samp>&rsquo;,

  902. &lsquo;<samp>xgene1</samp>&rsquo;, &lsquo;<samp>cortex-a57.cortex-a53</samp>&rsquo;, &lsquo;<samp>cortex-a72.cortex-a53</samp>&rsquo;,

  903. &lsquo;<samp>cortex-a73.cortex-a35</samp>&rsquo;, &lsquo;<samp>cortex-a73.cortex-a53</samp>&rsquo; and

  904. &lsquo;<samp>cortex-a75.cortex-a55</samp>&rsquo;.

  905. </p></dd>

  906. </dl>

  907. 

  908. <p>Additionally the &lsquo;<samp>generic-armv7-a</samp>&rsquo; pseudo target defaults to

  909. VFPv3 with 16 double-precision registers.  It supports the following

  910. extension options: &lsquo;<samp>mp</samp>&rsquo;, &lsquo;<samp>sec</samp>&rsquo;, &lsquo;<samp>vfpv3-d16</samp>&rsquo;,

  911. &lsquo;<samp>vfpv3</samp>&rsquo;, &lsquo;<samp>vfpv3-d16-fp16</samp>&rsquo;, &lsquo;<samp>vfpv3-fp16</samp>&rsquo;,

  912. &lsquo;<samp>vfpv4-d16</samp>&rsquo;, &lsquo;<samp>vfpv4</samp>&rsquo;, &lsquo;<samp>neon</samp>&rsquo;, &lsquo;<samp>neon-vfpv3</samp>&rsquo;,

  913. &lsquo;<samp>neon-fp16</samp>&rsquo;, &lsquo;<samp>neon-vfpv4</samp>&rsquo;.  The meanings are the same as for

  914. the extensions to <samp>-march=armv7-a</samp>.

  915. </p>

  916. <p><samp>-mcpu=generic-<var>arch</var></samp> is also permissible, and is

  917. equivalent to <samp>-march=<var>arch</var> -mtune=generic-<var>arch</var></samp>.

  918. See <samp>-mtune</samp> for more information.

  919. </p>

  920. <p><samp>-mcpu=native</samp> causes the compiler to auto-detect the CPU

  921. of the build computer.  At present, this feature is only supported on

  922. GNU/Linux, and not all architectures are recognized.  If the auto-detect

  923. is unsuccessful the option has no effect.

  924. </p>

  925. </dd>

  926. <dt><code>-mfpu=<var>name</var></code></dt>

  927. <dd><a name="index-mfpu-1"></a>

  928. <p>This specifies what floating-point hardware (or hardware emulation) is

  929. available on the target.  Permissible names are: &lsquo;<samp>auto</samp>&rsquo;, &lsquo;<samp>vfpv2</samp>&rsquo;,

  930. &lsquo;<samp>vfpv3</samp>&rsquo;,

  931. &lsquo;<samp>vfpv3-fp16</samp>&rsquo;, &lsquo;<samp>vfpv3-d16</samp>&rsquo;, &lsquo;<samp>vfpv3-d16-fp16</samp>&rsquo;, &lsquo;<samp>vfpv3xd</samp>&rsquo;,

  932. &lsquo;<samp>vfpv3xd-fp16</samp>&rsquo;, &lsquo;<samp>neon-vfpv3</samp>&rsquo;, &lsquo;<samp>neon-fp16</samp>&rsquo;, &lsquo;<samp>vfpv4</samp>&rsquo;,

  933. &lsquo;<samp>vfpv4-d16</samp>&rsquo;, &lsquo;<samp>fpv4-sp-d16</samp>&rsquo;, &lsquo;<samp>neon-vfpv4</samp>&rsquo;,

  934. &lsquo;<samp>fpv5-d16</samp>&rsquo;, &lsquo;<samp>fpv5-sp-d16</samp>&rsquo;,

  935. &lsquo;<samp>fp-armv8</samp>&rsquo;, &lsquo;<samp>neon-fp-armv8</samp>&rsquo; and &lsquo;<samp>crypto-neon-fp-armv8</samp>&rsquo;.

  936. Note that &lsquo;<samp>neon</samp>&rsquo; is an alias for &lsquo;<samp>neon-vfpv3</samp>&rsquo; and &lsquo;<samp>vfp</samp>&rsquo;

  937. is an alias for &lsquo;<samp>vfpv2</samp>&rsquo;.

  938. </p>

  939. <p>The setting &lsquo;<samp>auto</samp>&rsquo; is the default and is special.  It causes the

  940. compiler to select the floating-point and Advanced SIMD instructions

  941. based on the settings of <samp>-mcpu</samp> and <samp>-march</samp>.

  942. </p>

  943. <p>If the selected floating-point hardware includes the NEON extension

  944. (e.g. <samp>-mfpu=neon</samp>), note that floating-point

  945. operations are not generated by GCC&rsquo;s auto-vectorization pass unless

  946. <samp>-funsafe-math-optimizations</samp> is also specified.  This is

  947. because NEON hardware does not fully implement the IEEE 754 standard for

  948. floating-point arithmetic (in particular denormal values are treated as

  949. zero), so the use of NEON instructions may lead to a loss of precision.

  950. </p>

  951. <p>You can also set the fpu name at function level by using the <code>target(&quot;fpu=&quot;)</code> function attributes (see <a href="ARM-Function-Attributes.html#ARM-Function-Attributes">ARM Function Attributes</a>) or pragmas (see <a href="Function-Specific-Option-Pragmas.html#Function-Specific-Option-Pragmas">Function Specific Option Pragmas</a>).

  952. </p>

  953. </dd>

  954. <dt><code>-mfp16-format=<var>name</var></code></dt>

  955. <dd><a name="index-mfp16_002dformat"></a>

  956. <p>Specify the format of the <code>__fp16</code> half-precision floating-point type.

  957. Permissible names are &lsquo;<samp>none</samp>&rsquo;, &lsquo;<samp>ieee</samp>&rsquo;, and &lsquo;<samp>alternative</samp>&rsquo;;

  958. the default is &lsquo;<samp>none</samp>&rsquo;, in which case the <code>__fp16</code> type is not

  959. defined.  See <a href="Half_002dPrecision.html#Half_002dPrecision">Half-Precision</a>, for more information.

  960. </p>

  961. </dd>

  962. <dt><code>-mstructure-size-boundary=<var>n</var></code></dt>

  963. <dd><a name="index-mstructure_002dsize_002dboundary"></a>

  964. <p>The sizes of all structures and unions are rounded up to a multiple

  965. of the number of bits set by this option.  Permissible values are 8, 32

  966. and 64.  The default value varies for different toolchains.  For the COFF

  967. targeted toolchain the default value is 8.  A value of 64 is only allowed

  968. if the underlying ABI supports it.

  969. </p>

  970. <p>Specifying a larger number can produce faster, more efficient code, but

  971. can also increase the size of the program.  Different values are potentially

  972. incompatible.  Code compiled with one value cannot necessarily expect to

  973. work with code or libraries compiled with another value, if they exchange

  974. information using structures or unions.

  975. </p>

  976. <p>This option is deprecated.

  977. </p>

  978. </dd>

  979. <dt><code>-mabort-on-noreturn</code></dt>

  980. <dd><a name="index-mabort_002don_002dnoreturn"></a>

  981. <p>Generate a call to the function <code>abort</code> at the end of a

  982. <code>noreturn</code> function.  It is executed if the function tries to

  983. return.

  984. </p>

  985. </dd>

  986. <dt><code>-mlong-calls</code></dt>

  987. <dt><code>-mno-long-calls</code></dt>

  988. <dd><a name="index-mlong_002dcalls-2"></a>

  989. <a name="index-mno_002dlong_002dcalls"></a>

  990. <p>Tells the compiler to perform function calls by first loading the

  991. address of the function into a register and then performing a subroutine

  992. call on this register.  This switch is needed if the target function

  993. lies outside of the 64-megabyte addressing range of the offset-based

  994. version of subroutine call instruction.

  995. </p>

  996. <p>Even if this switch is enabled, not all function calls are turned

  997. into long calls.  The heuristic is that static functions, functions

  998. that have the <code>short_call</code> attribute, functions that are inside

  999. the scope of a <code>#pragma no_long_calls</code> directive, and functions whose

  1000. definitions have already been compiled within the current compilation

  1001. unit are not turned into long calls.  The exceptions to this rule are

  1002. that weak function definitions, functions with the <code>long_call</code>

  1003. attribute or the <code>section</code> attribute, and functions that are within

  1004. the scope of a <code>#pragma long_calls</code> directive are always

  1005. turned into long calls.

  1006. </p>

  1007. <p>This feature is not enabled by default.  Specifying

  1008. <samp>-mno-long-calls</samp> restores the default behavior, as does

  1009. placing the function calls within the scope of a <code>#pragma

  1010. long_calls_off</code> directive.  Note these switches have no effect on how

  1011. the compiler generates code to handle function calls via function

  1012. pointers.

  1013. </p>

  1014. </dd>

  1015. <dt><code>-msingle-pic-base</code></dt>

  1016. <dd><a name="index-msingle_002dpic_002dbase"></a>

  1017. <p>Treat the register used for PIC addressing as read-only, rather than

  1018. loading it in the prologue for each function.  The runtime system is

  1019. responsible for initializing this register with an appropriate value

  1020. before execution begins.

  1021. </p>

  1022. </dd>

  1023. <dt><code>-mpic-register=<var>reg</var></code></dt>

  1024. <dd><a name="index-mpic_002dregister"></a>

  1025. <p>Specify the register to be used for PIC addressing.

  1026. For standard PIC base case, the default is any suitable register

  1027. determined by compiler.  For single PIC base case, the default is

  1028. &lsquo;<samp>R9</samp>&rsquo; if target is EABI based or stack-checking is enabled,

  1029. otherwise the default is &lsquo;<samp>R10</samp>&rsquo;.

  1030. </p>

  1031. </dd>

  1032. <dt><code>-mpic-data-is-text-relative</code></dt>

  1033. <dd><a name="index-mpic_002ddata_002dis_002dtext_002drelative"></a>

  1034. <p>Assume that the displacement between the text and data segments is fixed

  1035. at static link time.  This permits using PC-relative addressing

  1036. operations to access data known to be in the data segment.  For

  1037. non-VxWorks RTP targets, this option is enabled by default.  When

  1038. disabled on such targets, it will enable <samp>-msingle-pic-base</samp> by

  1039. default.

  1040. </p>

  1041. </dd>

  1042. <dt><code>-mpoke-function-name</code></dt>

  1043. <dd><a name="index-mpoke_002dfunction_002dname"></a>

  1044. <p>Write the name of each function into the text section, directly

  1045. preceding the function prologue.  The generated code is similar to this:

  1046. </p>

  1047. <div class="smallexample">

  1048. <pre class="smallexample">     t0

  1049.          .ascii &quot;arm_poke_function_name&quot;, 0

  1050.          .align

  1051.      t1

  1052.          .word 0xff000000 + (t1 - t0)

  1053.      arm_poke_function_name

  1054.          mov     ip, sp

  1055.          stmfd   sp!, {fp, ip, lr, pc}

  1056.          sub     fp, ip, #4

  1057. </pre></div>

  1058. 

  1059. <p>When performing a stack backtrace, code can inspect the value of

  1060. <code>pc</code> stored at <code>fp + 0</code>.  If the trace function then looks at

  1061. location <code>pc - 12</code> and the top 8 bits are set, then we know that

  1062. there is a function name embedded immediately preceding this location

  1063. and has length <code>((pc[-3]) &amp; 0xff000000)</code>.

  1064. </p>

  1065. </dd>

  1066. <dt><code>-mthumb</code></dt>

  1067. <dt><code>-marm</code></dt>

  1068. <dd><a name="index-marm"></a>

  1069. <a name="index-mthumb"></a>

  1070. 

  1071. <p>Select between generating code that executes in ARM and Thumb

  1072. states.  The default for most configurations is to generate code

  1073. that executes in ARM state, but the default can be changed by

  1074. configuring GCC with the <samp>--with-mode=</samp><var>state</var>

  1075. configure option.

  1076. </p>

  1077. <p>You can also override the ARM and Thumb mode for each function

  1078. by using the <code>target(&quot;thumb&quot;)</code> and <code>target(&quot;arm&quot;)</code> function attributes

  1079. (see <a href="ARM-Function-Attributes.html#ARM-Function-Attributes">ARM Function Attributes</a>) or pragmas (see <a href="Function-Specific-Option-Pragmas.html#Function-Specific-Option-Pragmas">Function Specific Option Pragmas</a>).

  1080. </p>

  1081. </dd>

  1082. <dt><code>-mflip-thumb</code></dt>

  1083. <dd><a name="index-mflip_002dthumb"></a>

  1084. <p>Switch ARM/Thumb modes on alternating functions.

  1085. This option is provided for regression testing of mixed Thumb/ARM code

  1086. generation, and is not intended for ordinary use in compiling code.

  1087. </p>

  1088. </dd>

  1089. <dt><code>-mtpcs-frame</code></dt>

  1090. <dd><a name="index-mtpcs_002dframe"></a>

  1091. <p>Generate a stack frame that is compliant with the Thumb Procedure Call

  1092. Standard for all non-leaf functions.  (A leaf function is one that does

  1093. not call any other functions.)  The default is <samp>-mno-tpcs-frame</samp>.

  1094. </p>

  1095. </dd>

  1096. <dt><code>-mtpcs-leaf-frame</code></dt>

  1097. <dd><a name="index-mtpcs_002dleaf_002dframe"></a>

  1098. <p>Generate a stack frame that is compliant with the Thumb Procedure Call

  1099. Standard for all leaf functions.  (A leaf function is one that does

  1100. not call any other functions.)  The default is <samp>-mno-apcs-leaf-frame</samp>.

  1101. </p>

  1102. </dd>

  1103. <dt><code>-mcallee-super-interworking</code></dt>

  1104. <dd><a name="index-mcallee_002dsuper_002dinterworking"></a>

  1105. <p>Gives all externally visible functions in the file being compiled an ARM

  1106. instruction set header which switches to Thumb mode before executing the

  1107. rest of the function.  This allows these functions to be called from

  1108. non-interworking code.  This option is not valid in AAPCS configurations

  1109. because interworking is enabled by default.

  1110. </p>

  1111. </dd>

  1112. <dt><code>-mcaller-super-interworking</code></dt>

  1113. <dd><a name="index-mcaller_002dsuper_002dinterworking"></a>

  1114. <p>Allows calls via function pointers (including virtual functions) to

  1115. execute correctly regardless of whether the target code has been

  1116. compiled for interworking or not.  There is a small overhead in the cost

  1117. of executing a function pointer if this option is enabled.  This option

  1118. is not valid in AAPCS configurations because interworking is enabled

  1119. by default.

  1120. </p>

  1121. </dd>

  1122. <dt><code>-mtp=<var>name</var></code></dt>

  1123. <dd><a name="index-mtp"></a>

  1124. <p>Specify the access model for the thread local storage pointer.  The valid

  1125. models are &lsquo;<samp>soft</samp>&rsquo;, which generates calls to <code>__aeabi_read_tp</code>,

  1126. &lsquo;<samp>cp15</samp>&rsquo;, which fetches the thread pointer from <code>cp15</code> directly

  1127. (supported in the arm6k architecture), and &lsquo;<samp>auto</samp>&rsquo;, which uses the

  1128. best available method for the selected processor.  The default setting is

  1129. &lsquo;<samp>auto</samp>&rsquo;.

  1130. </p>

  1131. </dd>

  1132. <dt><code>-mtls-dialect=<var>dialect</var></code></dt>

  1133. <dd><a name="index-mtls_002ddialect"></a>

  1134. <p>Specify the dialect to use for accessing thread local storage.  Two

  1135. <var>dialect</var>s are supported&mdash;&lsquo;<samp>gnu</samp>&rsquo; and &lsquo;<samp>gnu2</samp>&rsquo;.  The

  1136. &lsquo;<samp>gnu</samp>&rsquo; dialect selects the original GNU scheme for supporting

  1137. local and global dynamic TLS models.  The &lsquo;<samp>gnu2</samp>&rsquo; dialect

  1138. selects the GNU descriptor scheme, which provides better performance

  1139. for shared libraries.  The GNU descriptor scheme is compatible with

  1140. the original scheme, but does require new assembler, linker and

  1141. library support.  Initial and local exec TLS models are unaffected by

  1142. this option and always use the original scheme.

  1143. </p>

  1144. </dd>

  1145. <dt><code>-mword-relocations</code></dt>

  1146. <dd><a name="index-mword_002drelocations"></a>

  1147. <p>Only generate absolute relocations on word-sized values (i.e. R_ARM_ABS32).

  1148. This is enabled by default on targets (uClinux, SymbianOS) where the runtime

  1149. loader imposes this restriction, and when <samp>-fpic</samp> or <samp>-fPIC</samp>

  1150. is specified. This option conflicts with <samp>-mslow-flash-data</samp>.

  1151. </p>

  1152. </dd>

  1153. <dt><code>-mfix-cortex-m3-ldrd</code></dt>

  1154. <dd><a name="index-mfix_002dcortex_002dm3_002dldrd"></a>

  1155. <p>Some Cortex-M3 cores can cause data corruption when <code>ldrd</code> instructions

  1156. with overlapping destination and base registers are used.  This option avoids

  1157. generating these instructions.  This option is enabled by default when

  1158. <samp>-mcpu=cortex-m3</samp> is specified.

  1159. </p>

  1160. </dd>

  1161. <dt><code>-munaligned-access</code></dt>

  1162. <dt><code>-mno-unaligned-access</code></dt>

  1163. <dd><a name="index-munaligned_002daccess"></a>

  1164. <a name="index-mno_002dunaligned_002daccess"></a>

  1165. <p>Enables (or disables) reading and writing of 16- and 32- bit values

  1166. from addresses that are not 16- or 32- bit aligned.  By default

  1167. unaligned access is disabled for all pre-ARMv6, all ARMv6-M and for

  1168. ARMv8-M Baseline architectures, and enabled for all other

  1169. architectures.  If unaligned access is not enabled then words in packed

  1170. data structures are accessed a byte at a time.

  1171. </p>

  1172. <p>The ARM attribute <code>Tag_CPU_unaligned_access</code> is set in the

  1173. generated object file to either true or false, depending upon the

  1174. setting of this option.  If unaligned access is enabled then the

  1175. preprocessor symbol <code>__ARM_FEATURE_UNALIGNED</code> is also

  1176. defined.

  1177. </p>

  1178. </dd>

  1179. <dt><code>-mneon-for-64bits</code></dt>

  1180. <dd><a name="index-mneon_002dfor_002d64bits"></a>

  1181. <p>This option is deprecated and has no effect.

  1182. </p>

  1183. </dd>

  1184. <dt><code>-mslow-flash-data</code></dt>

  1185. <dd><a name="index-mslow_002dflash_002ddata"></a>

  1186. <p>Assume loading data from flash is slower than fetching instruction.

  1187. Therefore literal load is minimized for better performance.

  1188. This option is only supported when compiling for ARMv7 M-profile and

  1189. off by default. It conflicts with <samp>-mword-relocations</samp>.

  1190. </p>

  1191. </dd>

  1192. <dt><code>-masm-syntax-unified</code></dt>

  1193. <dd><a name="index-masm_002dsyntax_002dunified"></a>

  1194. <p>Assume inline assembler is using unified asm syntax.  The default is

  1195. currently off which implies divided syntax.  This option has no impact

  1196. on Thumb2. However, this may change in future releases of GCC.

  1197. Divided syntax should be considered deprecated.

  1198. </p>

  1199. </dd>

  1200. <dt><code>-mrestrict-it</code></dt>

  1201. <dd><a name="index-mrestrict_002dit"></a>

  1202. <p>Restricts generation of IT blocks to conform to the rules of ARMv8-A.

  1203. IT blocks can only contain a single 16-bit instruction from a select

  1204. set of instructions. This option is on by default for ARMv8-A Thumb mode.

  1205. </p>

  1206. </dd>

  1207. <dt><code>-mprint-tune-info</code></dt>

  1208. <dd><a name="index-mprint_002dtune_002dinfo"></a>

  1209. <p>Print CPU tuning information as comment in assembler file.  This is

  1210. an option used only for regression testing of the compiler and not

  1211. intended for ordinary use in compiling code.  This option is disabled

  1212. by default.

  1213. </p>

  1214. </dd>

  1215. <dt><code>-mverbose-cost-dump</code></dt>

  1216. <dd><a name="index-mverbose_002dcost_002ddump-1"></a>

  1217. <p>Enable verbose cost model dumping in the debug dump files.  This option is

  1218. provided for use in debugging the compiler.

  1219. </p>

  1220. </dd>

  1221. <dt><code>-mpure-code</code></dt>

  1222. <dd><a name="index-mpure_002dcode"></a>

  1223. <p>Do not allow constant data to be placed in code sections.

  1224. Additionally, when compiling for ELF object format give all text sections the

  1225. ELF processor-specific section attribute <code>SHF_ARM_PURECODE</code>.  This option

  1226. is only available when generating non-pic code for M-profile targets.

  1227. </p>

  1228. </dd>

  1229. <dt><code>-mcmse</code></dt>

  1230. <dd><a name="index-mcmse"></a>

  1231. <p>Generate secure code as per the &quot;ARMv8-M Security Extensions: Requirements on

  1232. Development Tools Engineering Specification&quot;, which can be found on

  1233. <a href="https://developer.arm.com/documentation/ecm0359818/latest/">https://developer.arm.com/documentation/ecm0359818/latest/</a>.

  1234. </p>

  1235. </dd>

  1236. <dt><code>-mfdpic</code></dt>

  1237. <dt><code>-mno-fdpic</code></dt>

  1238. <dd><a name="index-mfdpic"></a>

  1239. <a name="index-mno_002dfdpic"></a>

  1240. <p>Select the FDPIC ABI, which uses 64-bit function descriptors to

  1241. represent pointers to functions.  When the compiler is configured for

  1242. <code>arm-*-uclinuxfdpiceabi</code> targets, this option is on by default

  1243. and implies <samp>-fPIE</samp> if none of the PIC/PIE-related options is

  1244. provided.  On other targets, it only enables the FDPIC-specific code

  1245. generation features, and the user should explicitly provide the

  1246. PIC/PIE-related options as needed.

  1247. </p>

  1248. <p>Note that static linking is not supported because it would still

  1249. involve the dynamic linker when the program self-relocates.  If such

  1250. behavior is acceptable, use -static and -Wl,-dynamic-linker options.

  1251. </p>

  1252. <p>The opposite <samp>-mno-fdpic</samp> option is useful (and required) to

  1253. build the Linux kernel using the same (<code>arm-*-uclinuxfdpiceabi</code>)

  1254. toolchain as the one used to build the userland programs.

  1255. </p>

  1256. </dd>

  1257. </dl>

  1258. 

  1259. <hr>

  1260. <div class="header">

  1261. <p>

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  1263. </div>

  1264. 

  1265. 

  1266. 

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