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  25. <title>Basic PowerPC Built-in Functions Available on all Configurations (Using the GNU Compiler Collection (GCC))</title>

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  70. <a name="Basic-PowerPC-Built_002din-Functions-Available-on-all-Configurations"></a>

  71. <div class="header">

  72. <p>

  73. Next: <a href="Basic-PowerPC-Built_002din-Functions-Available-on-ISA-2_002e05.html#Basic-PowerPC-Built_002din-Functions-Available-on-ISA-2_002e05" accesskey="n" rel="next">Basic PowerPC Built-in Functions Available on ISA 2.05</a>, Up: <a href="Basic-PowerPC-Built_002din-Functions.html#Basic-PowerPC-Built_002din-Functions" accesskey="u" rel="up">Basic PowerPC Built-in Functions</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>

  74. </div>

  75. <hr>

  76. <a name="Basic-PowerPC-Built_002din-Functions-Available-on-all-Configurations-1"></a>

  77. <h4 class="subsubsection">6.60.22.1 Basic PowerPC Built-in Functions Available on all Configurations</h4>

  78. 

  79. <dl>

  80. <dt><a name="index-_005f_005fbuiltin_005fcpu_005finit"></a>Built-in Function: <em>void</em> <strong>__builtin_cpu_init</strong> <em>(void)</em></dt>

  81. <dd><p>This function is a <code>nop</code> on the PowerPC platform and is included solely

  82. to maintain API compatibility with the x86 builtins.

  83. </p></dd></dl>

  84. 

  85. <dl>

  86. <dt><a name="index-_005f_005fbuiltin_005fcpu_005fis"></a>Built-in Function: <em>int</em> <strong>__builtin_cpu_is</strong> <em>(const char *<var>cpuname</var>)</em></dt>

  87. <dd><p>This function returns a value of <code>1</code> if the run-time CPU is of type

  88. <var>cpuname</var> and returns <code>0</code> otherwise

  89. </p>

  90. <p>The <code>__builtin_cpu_is</code> function requires GLIBC 2.23 or newer

  91. which exports the hardware capability bits.  GCC defines the macro

  92. <code>__BUILTIN_CPU_SUPPORTS__</code> if the <code>__builtin_cpu_supports</code>

  93. built-in function is fully supported.

  94. </p>

  95. <p>If GCC was configured to use a GLIBC before 2.23, the built-in

  96. function <code>__builtin_cpu_is</code> always returns a 0 and the compiler

  97. issues a warning.

  98. </p>

  99. <p>The following CPU names can be detected:

  100. </p>

  101. <dl compact="compact">

  102. <dt>&lsquo;<samp>power10</samp>&rsquo;</dt>

  103. <dd><p>IBM POWER10 Server CPU.

  104. </p></dd>

  105. <dt>&lsquo;<samp>power9</samp>&rsquo;</dt>

  106. <dd><p>IBM POWER9 Server CPU.

  107. </p></dd>

  108. <dt>&lsquo;<samp>power8</samp>&rsquo;</dt>

  109. <dd><p>IBM POWER8 Server CPU.

  110. </p></dd>

  111. <dt>&lsquo;<samp>power7</samp>&rsquo;</dt>

  112. <dd><p>IBM POWER7 Server CPU.

  113. </p></dd>

  114. <dt>&lsquo;<samp>power6x</samp>&rsquo;</dt>

  115. <dd><p>IBM POWER6 Server CPU (RAW mode).

  116. </p></dd>

  117. <dt>&lsquo;<samp>power6</samp>&rsquo;</dt>

  118. <dd><p>IBM POWER6 Server CPU (Architected mode).

  119. </p></dd>

  120. <dt>&lsquo;<samp>power5+</samp>&rsquo;</dt>

  121. <dd><p>IBM POWER5+ Server CPU.

  122. </p></dd>

  123. <dt>&lsquo;<samp>power5</samp>&rsquo;</dt>

  124. <dd><p>IBM POWER5 Server CPU.

  125. </p></dd>

  126. <dt>&lsquo;<samp>ppc970</samp>&rsquo;</dt>

  127. <dd><p>IBM 970 Server CPU (ie, Apple G5).

  128. </p></dd>

  129. <dt>&lsquo;<samp>power4</samp>&rsquo;</dt>

  130. <dd><p>IBM POWER4 Server CPU.

  131. </p></dd>

  132. <dt>&lsquo;<samp>ppca2</samp>&rsquo;</dt>

  133. <dd><p>IBM A2 64-bit Embedded CPU

  134. </p></dd>

  135. <dt>&lsquo;<samp>ppc476</samp>&rsquo;</dt>

  136. <dd><p>IBM PowerPC 476FP 32-bit Embedded CPU.

  137. </p></dd>

  138. <dt>&lsquo;<samp>ppc464</samp>&rsquo;</dt>

  139. <dd><p>IBM PowerPC 464 32-bit Embedded CPU.

  140. </p></dd>

  141. <dt>&lsquo;<samp>ppc440</samp>&rsquo;</dt>

  142. <dd><p>PowerPC 440 32-bit Embedded CPU.

  143. </p></dd>

  144. <dt>&lsquo;<samp>ppc405</samp>&rsquo;</dt>

  145. <dd><p>PowerPC 405 32-bit Embedded CPU.

  146. </p></dd>

  147. <dt>&lsquo;<samp>ppc-cell-be</samp>&rsquo;</dt>

  148. <dd><p>IBM PowerPC Cell Broadband Engine Architecture CPU.

  149. </p></dd>

  150. </dl>

  151. 

  152. <p>Here is an example:

  153. </p><div class="smallexample">

  154. <pre class="smallexample">#ifdef __BUILTIN_CPU_SUPPORTS__

  155.   if (__builtin_cpu_is (&quot;power8&quot;))

  156.     {

  157.        do_power8 (); // POWER8 specific implementation.

  158.     }

  159.   else

  160. #endif

  161.     {

  162.        do_generic (); // Generic implementation.

  163.     }

  164. </pre></div>

  165. </dd></dl>

  166. 

  167. <dl>

  168. <dt><a name="index-_005f_005fbuiltin_005fcpu_005fsupports"></a>Built-in Function: <em>int</em> <strong>__builtin_cpu_supports</strong> <em>(const char *<var>feature</var>)</em></dt>

  169. <dd><p>This function returns a value of <code>1</code> if the run-time CPU supports the HWCAP

  170. feature <var>feature</var> and returns <code>0</code> otherwise.

  171. </p>

  172. <p>The <code>__builtin_cpu_supports</code> function requires GLIBC 2.23 or

  173. newer which exports the hardware capability bits.  GCC defines the

  174. macro <code>__BUILTIN_CPU_SUPPORTS__</code> if the

  175. <code>__builtin_cpu_supports</code> built-in function is fully supported.

  176. </p>

  177. <p>If GCC was configured to use a GLIBC before 2.23, the built-in

  178. function <code>__builtin_cpu_suports</code> always returns a 0 and the

  179. compiler issues a warning.

  180. </p>

  181. <p>The following features can be

  182. detected:

  183. </p>

  184. <dl compact="compact">

  185. <dt>&lsquo;<samp>4xxmac</samp>&rsquo;</dt>

  186. <dd><p>4xx CPU has a Multiply Accumulator.

  187. </p></dd>

  188. <dt>&lsquo;<samp>altivec</samp>&rsquo;</dt>

  189. <dd><p>CPU has a SIMD/Vector Unit.

  190. </p></dd>

  191. <dt>&lsquo;<samp>arch_2_05</samp>&rsquo;</dt>

  192. <dd><p>CPU supports ISA 2.05 (eg, POWER6)

  193. </p></dd>

  194. <dt>&lsquo;<samp>arch_2_06</samp>&rsquo;</dt>

  195. <dd><p>CPU supports ISA 2.06 (eg, POWER7)

  196. </p></dd>

  197. <dt>&lsquo;<samp>arch_2_07</samp>&rsquo;</dt>

  198. <dd><p>CPU supports ISA 2.07 (eg, POWER8)

  199. </p></dd>

  200. <dt>&lsquo;<samp>arch_3_00</samp>&rsquo;</dt>

  201. <dd><p>CPU supports ISA 3.0 (eg, POWER9)

  202. </p></dd>

  203. <dt>&lsquo;<samp>arch_3_1</samp>&rsquo;</dt>

  204. <dd><p>CPU supports ISA 3.1 (eg, POWER10)

  205. </p></dd>

  206. <dt>&lsquo;<samp>archpmu</samp>&rsquo;</dt>

  207. <dd><p>CPU supports the set of compatible performance monitoring events.

  208. </p></dd>

  209. <dt>&lsquo;<samp>booke</samp>&rsquo;</dt>

  210. <dd><p>CPU supports the Embedded ISA category.

  211. </p></dd>

  212. <dt>&lsquo;<samp>cellbe</samp>&rsquo;</dt>

  213. <dd><p>CPU has a CELL broadband engine.

  214. </p></dd>

  215. <dt>&lsquo;<samp>darn</samp>&rsquo;</dt>

  216. <dd><p>CPU supports the <code>darn</code> (deliver a random number) instruction.

  217. </p></dd>

  218. <dt>&lsquo;<samp>dfp</samp>&rsquo;</dt>

  219. <dd><p>CPU has a decimal floating point unit.

  220. </p></dd>

  221. <dt>&lsquo;<samp>dscr</samp>&rsquo;</dt>

  222. <dd><p>CPU supports the data stream control register.

  223. </p></dd>

  224. <dt>&lsquo;<samp>ebb</samp>&rsquo;</dt>

  225. <dd><p>CPU supports event base branching.

  226. </p></dd>

  227. <dt>&lsquo;<samp>efpdouble</samp>&rsquo;</dt>

  228. <dd><p>CPU has a SPE double precision floating point unit.

  229. </p></dd>

  230. <dt>&lsquo;<samp>efpsingle</samp>&rsquo;</dt>

  231. <dd><p>CPU has a SPE single precision floating point unit.

  232. </p></dd>

  233. <dt>&lsquo;<samp>fpu</samp>&rsquo;</dt>

  234. <dd><p>CPU has a floating point unit.

  235. </p></dd>

  236. <dt>&lsquo;<samp>htm</samp>&rsquo;</dt>

  237. <dd><p>CPU has hardware transaction memory instructions.

  238. </p></dd>

  239. <dt>&lsquo;<samp>htm-nosc</samp>&rsquo;</dt>

  240. <dd><p>Kernel aborts hardware transactions when a syscall is made.

  241. </p></dd>

  242. <dt>&lsquo;<samp>htm-no-suspend</samp>&rsquo;</dt>

  243. <dd><p>CPU supports hardware transaction memory but does not support the

  244. <code>tsuspend.</code> instruction.

  245. </p></dd>

  246. <dt>&lsquo;<samp>ic_snoop</samp>&rsquo;</dt>

  247. <dd><p>CPU supports icache snooping capabilities.

  248. </p></dd>

  249. <dt>&lsquo;<samp>ieee128</samp>&rsquo;</dt>

  250. <dd><p>CPU supports 128-bit IEEE binary floating point instructions.

  251. </p></dd>

  252. <dt>&lsquo;<samp>isel</samp>&rsquo;</dt>

  253. <dd><p>CPU supports the integer select instruction.

  254. </p></dd>

  255. <dt>&lsquo;<samp>mma</samp>&rsquo;</dt>

  256. <dd><p>CPU supports the matrix-multiply assist instructions.

  257. </p></dd>

  258. <dt>&lsquo;<samp>mmu</samp>&rsquo;</dt>

  259. <dd><p>CPU has a memory management unit.

  260. </p></dd>

  261. <dt>&lsquo;<samp>notb</samp>&rsquo;</dt>

  262. <dd><p>CPU does not have a timebase (eg, 601 and 403gx).

  263. </p></dd>

  264. <dt>&lsquo;<samp>pa6t</samp>&rsquo;</dt>

  265. <dd><p>CPU supports the PA Semi 6T CORE ISA.

  266. </p></dd>

  267. <dt>&lsquo;<samp>power4</samp>&rsquo;</dt>

  268. <dd><p>CPU supports ISA 2.00 (eg, POWER4)

  269. </p></dd>

  270. <dt>&lsquo;<samp>power5</samp>&rsquo;</dt>

  271. <dd><p>CPU supports ISA 2.02 (eg, POWER5)

  272. </p></dd>

  273. <dt>&lsquo;<samp>power5+</samp>&rsquo;</dt>

  274. <dd><p>CPU supports ISA 2.03 (eg, POWER5+)

  275. </p></dd>

  276. <dt>&lsquo;<samp>power6x</samp>&rsquo;</dt>

  277. <dd><p>CPU supports ISA 2.05 (eg, POWER6) extended opcodes mffgpr and mftgpr.

  278. </p></dd>

  279. <dt>&lsquo;<samp>ppc32</samp>&rsquo;</dt>

  280. <dd><p>CPU supports 32-bit mode execution.

  281. </p></dd>

  282. <dt>&lsquo;<samp>ppc601</samp>&rsquo;</dt>

  283. <dd><p>CPU supports the old POWER ISA (eg, 601)

  284. </p></dd>

  285. <dt>&lsquo;<samp>ppc64</samp>&rsquo;</dt>

  286. <dd><p>CPU supports 64-bit mode execution.

  287. </p></dd>

  288. <dt>&lsquo;<samp>ppcle</samp>&rsquo;</dt>

  289. <dd><p>CPU supports a little-endian mode that uses address swizzling.

  290. </p></dd>

  291. <dt>&lsquo;<samp>scv</samp>&rsquo;</dt>

  292. <dd><p>Kernel supports system call vectored.

  293. </p></dd>

  294. <dt>&lsquo;<samp>smt</samp>&rsquo;</dt>

  295. <dd><p>CPU support simultaneous multi-threading.

  296. </p></dd>

  297. <dt>&lsquo;<samp>spe</samp>&rsquo;</dt>

  298. <dd><p>CPU has a signal processing extension unit.

  299. </p></dd>

  300. <dt>&lsquo;<samp>tar</samp>&rsquo;</dt>

  301. <dd><p>CPU supports the target address register.

  302. </p></dd>

  303. <dt>&lsquo;<samp>true_le</samp>&rsquo;</dt>

  304. <dd><p>CPU supports true little-endian mode.

  305. </p></dd>

  306. <dt>&lsquo;<samp>ucache</samp>&rsquo;</dt>

  307. <dd><p>CPU has unified I/D cache.

  308. </p></dd>

  309. <dt>&lsquo;<samp>vcrypto</samp>&rsquo;</dt>

  310. <dd><p>CPU supports the vector cryptography instructions.

  311. </p></dd>

  312. <dt>&lsquo;<samp>vsx</samp>&rsquo;</dt>

  313. <dd><p>CPU supports the vector-scalar extension.

  314. </p></dd>

  315. </dl>

  316. 

  317. <p>Here is an example:

  318. </p><div class="smallexample">

  319. <pre class="smallexample">#ifdef __BUILTIN_CPU_SUPPORTS__

  320.   if (__builtin_cpu_supports (&quot;fpu&quot;))

  321.     {

  322.        asm(&quot;fadd %0,%1,%2&quot; : &quot;=d&quot;(dst) : &quot;d&quot;(src1), &quot;d&quot;(src2));

  323.     }

  324.   else

  325. #endif

  326.     {

  327.        dst = __fadd (src1, src2); // Software FP addition function.

  328.     }

  329. </pre></div>

  330. </dd></dl>

  331. 

  332. <p>The following built-in functions are also available on all PowerPC

  333. processors:

  334. </p><div class="smallexample">

  335. <pre class="smallexample">uint64_t __builtin_ppc_get_timebase ();

  336. unsigned long __builtin_ppc_mftb ();

  337. double __builtin_unpack_ibm128 (__ibm128, int);

  338. __ibm128 __builtin_pack_ibm128 (double, double);

  339. double __builtin_mffs (void);

  340. void __builtin_mtfsf (const int, double);

  341. void __builtin_mtfsb0 (const int);

  342. void __builtin_mtfsb1 (const int);

  343. void __builtin_set_fpscr_rn (int);

  344. </pre></div>

  345. 

  346. <p>The <code>__builtin_ppc_get_timebase</code> and <code>__builtin_ppc_mftb</code>

  347. functions generate instructions to read the Time Base Register.  The

  348. <code>__builtin_ppc_get_timebase</code> function may generate multiple

  349. instructions and always returns the 64 bits of the Time Base Register.

  350. The <code>__builtin_ppc_mftb</code> function always generates one instruction and

  351. returns the Time Base Register value as an unsigned long, throwing away

  352. the most significant word on 32-bit environments.  The <code>__builtin_mffs</code>

  353. return the value of the FPSCR register.  Note, ISA 3.0 supports the

  354. <code>__builtin_mffsl()</code> which permits software to read the control and

  355. non-sticky status bits in the FSPCR without the higher latency associated with

  356. accessing the sticky status bits.  The <code>__builtin_mtfsf</code> takes a constant

  357. 8-bit integer field mask and a double precision floating point argument

  358. and generates the <code>mtfsf</code> (extended mnemonic) instruction to write new

  359. values to selected fields of the FPSCR.  The

  360. <code>__builtin_mtfsb0</code> and <code>__builtin_mtfsb1</code> take the bit to change

  361. as an argument.  The valid bit range is between 0 and 31.  The builtins map to

  362. the <code>mtfsb0</code> and <code>mtfsb1</code> instructions which take the argument and

  363. add 32.  Hence these instructions only modify the FPSCR[32:63] bits by

  364. changing the specified bit to a zero or one respectively.  The

  365. <code>__builtin_set_fpscr_rn</code> builtin allows changing both of the floating

  366. point rounding mode bits.  The argument is a 2-bit value.  The argument can

  367. either be a <code>const int</code> or stored in a variable. The builtin uses

  368. the ISA 3.0

  369. instruction <code>mffscrn</code> if available, otherwise it reads the FPSCR, masks

  370. the current rounding mode bits out and OR&rsquo;s in the new value.

  371. </p>

  372. <hr>

  373. <div class="header">

  374. <p>

  375. Next: <a href="Basic-PowerPC-Built_002din-Functions-Available-on-ISA-2_002e05.html#Basic-PowerPC-Built_002din-Functions-Available-on-ISA-2_002e05" accesskey="n" rel="next">Basic PowerPC Built-in Functions Available on ISA 2.05</a>, Up: <a href="Basic-PowerPC-Built_002din-Functions.html#Basic-PowerPC-Built_002din-Functions" accesskey="u" rel="up">Basic PowerPC Built-in Functions</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>

  376. </div>

  377. 

  378. 

  379. 

  380. </body>

  381. </html>