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  25. <title>PowerPC Function Attributes (Using the GNU Compiler Collection (GCC))</title>

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  34. <link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">

  35. <link href="Function-Attributes.html#Function-Attributes" rel="up" title="Function Attributes">

  36. <link href="RISC_002dV-Function-Attributes.html#RISC_002dV-Function-Attributes" rel="next" title="RISC-V Function Attributes">

  37. <link href="Nvidia-PTX-Function-Attributes.html#Nvidia-PTX-Function-Attributes" rel="prev" title="Nvidia PTX Function Attributes">

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  68. 

  69. <body lang="en">

  70. <a name="PowerPC-Function-Attributes"></a>

  71. <div class="header">

  72. <p>

  73. Next: <a href="RISC_002dV-Function-Attributes.html#RISC_002dV-Function-Attributes" accesskey="n" rel="next">RISC-V Function Attributes</a>, Previous: <a href="Nvidia-PTX-Function-Attributes.html#Nvidia-PTX-Function-Attributes" accesskey="p" rel="prev">Nvidia PTX Function Attributes</a>, Up: <a href="Function-Attributes.html#Function-Attributes" accesskey="u" rel="up">Function Attributes</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>

  74. </div>

  75. <hr>

  76. <a name="PowerPC-Function-Attributes-1"></a>

  77. <h4 class="subsection">6.33.26 PowerPC Function Attributes</h4>

  78. 

  79. <p>These function attributes are supported by the PowerPC back end:

  80. </p>

  81. <dl compact="compact">

  82. <dt><code>longcall</code></dt>

  83. <dt><code>shortcall</code></dt>

  84. <dd><a name="index-indirect-calls_002c-PowerPC"></a>

  85. <a name="index-longcall-function-attribute_002c-PowerPC"></a>

  86. <a name="index-shortcall-function-attribute_002c-PowerPC"></a>

  87. <p>The <code>longcall</code> attribute

  88. indicates that the function might be far away from the call site and

  89. require a different (more expensive) calling sequence.  The

  90. <code>shortcall</code> attribute indicates that the function is always close

  91. enough for the shorter calling sequence to be used.  These attributes

  92. override both the <samp>-mlongcall</samp> switch and

  93. the <code>#pragma longcall</code> setting.

  94. </p>

  95. <p>See <a href="RS_002f6000-and-PowerPC-Options.html#RS_002f6000-and-PowerPC-Options">RS/6000 and PowerPC Options</a>, for more information on whether long

  96. calls are necessary.

  97. </p>

  98. </dd>

  99. <dt><code>target (<var>options</var>)</code></dt>

  100. <dd><a name="index-target-function-attribute-3"></a>

  101. <p>As discussed in <a href="Common-Function-Attributes.html#Common-Function-Attributes">Common Function Attributes</a>, this attribute 

  102. allows specification of target-specific compilation options.

  103. </p>

  104. <p>On the PowerPC, the following options are allowed:

  105. </p>

  106. <dl compact="compact">

  107. <dt>&lsquo;<samp>altivec</samp>&rsquo;</dt>

  108. <dt>&lsquo;<samp>no-altivec</samp>&rsquo;</dt>

  109. <dd><a name="index-target_0028_0022altivec_0022_0029-function-attribute_002c-PowerPC"></a>

  110. <p>Generate code that uses (does not use) AltiVec instructions.  In

  111. 32-bit code, you cannot enable AltiVec instructions unless

  112. <samp>-mabi=altivec</samp> is used on the command line.

  113. </p>

  114. </dd>

  115. <dt>&lsquo;<samp>cmpb</samp>&rsquo;</dt>

  116. <dt>&lsquo;<samp>no-cmpb</samp>&rsquo;</dt>

  117. <dd><a name="index-target_0028_0022cmpb_0022_0029-function-attribute_002c-PowerPC"></a>

  118. <p>Generate code that uses (does not use) the compare bytes instruction

  119. implemented on the POWER6 processor and other processors that support

  120. the PowerPC V2.05 architecture.

  121. </p>

  122. </dd>

  123. <dt>&lsquo;<samp>dlmzb</samp>&rsquo;</dt>

  124. <dt>&lsquo;<samp>no-dlmzb</samp>&rsquo;</dt>

  125. <dd><a name="index-target_0028_0022dlmzb_0022_0029-function-attribute_002c-PowerPC"></a>

  126. <p>Generate code that uses (does not use) the string-search &lsquo;<samp>dlmzb</samp>&rsquo;

  127. instruction on the IBM 405, 440, 464 and 476 processors.  This instruction is

  128. generated by default when targeting those processors.

  129. </p>

  130. </dd>

  131. <dt>&lsquo;<samp>fprnd</samp>&rsquo;</dt>

  132. <dt>&lsquo;<samp>no-fprnd</samp>&rsquo;</dt>

  133. <dd><a name="index-target_0028_0022fprnd_0022_0029-function-attribute_002c-PowerPC"></a>

  134. <p>Generate code that uses (does not use) the FP round to integer

  135. instructions implemented on the POWER5+ processor and other processors

  136. that support the PowerPC V2.03 architecture.

  137. </p>

  138. </dd>

  139. <dt>&lsquo;<samp>hard-dfp</samp>&rsquo;</dt>

  140. <dt>&lsquo;<samp>no-hard-dfp</samp>&rsquo;</dt>

  141. <dd><a name="index-target_0028_0022hard_002ddfp_0022_0029-function-attribute_002c-PowerPC"></a>

  142. <p>Generate code that uses (does not use) the decimal floating-point

  143. instructions implemented on some POWER processors.

  144. </p>

  145. </dd>

  146. <dt>&lsquo;<samp>isel</samp>&rsquo;</dt>

  147. <dt>&lsquo;<samp>no-isel</samp>&rsquo;</dt>

  148. <dd><a name="index-target_0028_0022isel_0022_0029-function-attribute_002c-PowerPC"></a>

  149. <p>Generate code that uses (does not use) ISEL instruction.

  150. </p>

  151. </dd>

  152. <dt>&lsquo;<samp>mfcrf</samp>&rsquo;</dt>

  153. <dt>&lsquo;<samp>no-mfcrf</samp>&rsquo;</dt>

  154. <dd><a name="index-target_0028_0022mfcrf_0022_0029-function-attribute_002c-PowerPC"></a>

  155. <p>Generate code that uses (does not use) the move from condition

  156. register field instruction implemented on the POWER4 processor and

  157. other processors that support the PowerPC V2.01 architecture.

  158. </p>

  159. </dd>

  160. <dt>&lsquo;<samp>mulhw</samp>&rsquo;</dt>

  161. <dt>&lsquo;<samp>no-mulhw</samp>&rsquo;</dt>

  162. <dd><a name="index-target_0028_0022mulhw_0022_0029-function-attribute_002c-PowerPC"></a>

  163. <p>Generate code that uses (does not use) the half-word multiply and

  164. multiply-accumulate instructions on the IBM 405, 440, 464 and 476 processors.

  165. These instructions are generated by default when targeting those

  166. processors.

  167. </p>

  168. </dd>

  169. <dt>&lsquo;<samp>multiple</samp>&rsquo;</dt>

  170. <dt>&lsquo;<samp>no-multiple</samp>&rsquo;</dt>

  171. <dd><a name="index-target_0028_0022multiple_0022_0029-function-attribute_002c-PowerPC"></a>

  172. <p>Generate code that uses (does not use) the load multiple word

  173. instructions and the store multiple word instructions.

  174. </p>

  175. </dd>

  176. <dt>&lsquo;<samp>update</samp>&rsquo;</dt>

  177. <dt>&lsquo;<samp>no-update</samp>&rsquo;</dt>

  178. <dd><a name="index-target_0028_0022update_0022_0029-function-attribute_002c-PowerPC"></a>

  179. <p>Generate code that uses (does not use) the load or store instructions

  180. that update the base register to the address of the calculated memory

  181. location.

  182. </p>

  183. </dd>

  184. <dt>&lsquo;<samp>popcntb</samp>&rsquo;</dt>

  185. <dt>&lsquo;<samp>no-popcntb</samp>&rsquo;</dt>

  186. <dd><a name="index-target_0028_0022popcntb_0022_0029-function-attribute_002c-PowerPC"></a>

  187. <p>Generate code that uses (does not use) the popcount and double-precision

  188. FP reciprocal estimate instruction implemented on the POWER5

  189. processor and other processors that support the PowerPC V2.02

  190. architecture.

  191. </p>

  192. </dd>

  193. <dt>&lsquo;<samp>popcntd</samp>&rsquo;</dt>

  194. <dt>&lsquo;<samp>no-popcntd</samp>&rsquo;</dt>

  195. <dd><a name="index-target_0028_0022popcntd_0022_0029-function-attribute_002c-PowerPC"></a>

  196. <p>Generate code that uses (does not use) the popcount instruction

  197. implemented on the POWER7 processor and other processors that support

  198. the PowerPC V2.06 architecture.

  199. </p>

  200. </dd>

  201. <dt>&lsquo;<samp>powerpc-gfxopt</samp>&rsquo;</dt>

  202. <dt>&lsquo;<samp>no-powerpc-gfxopt</samp>&rsquo;</dt>

  203. <dd><a name="index-target_0028_0022powerpc_002dgfxopt_0022_0029-function-attribute_002c-PowerPC"></a>

  204. <p>Generate code that uses (does not use) the optional PowerPC

  205. architecture instructions in the Graphics group, including

  206. floating-point select.

  207. </p>

  208. </dd>

  209. <dt>&lsquo;<samp>powerpc-gpopt</samp>&rsquo;</dt>

  210. <dt>&lsquo;<samp>no-powerpc-gpopt</samp>&rsquo;</dt>

  211. <dd><a name="index-target_0028_0022powerpc_002dgpopt_0022_0029-function-attribute_002c-PowerPC"></a>

  212. <p>Generate code that uses (does not use) the optional PowerPC

  213. architecture instructions in the General Purpose group, including

  214. floating-point square root.

  215. </p>

  216. </dd>

  217. <dt>&lsquo;<samp>recip-precision</samp>&rsquo;</dt>

  218. <dt>&lsquo;<samp>no-recip-precision</samp>&rsquo;</dt>

  219. <dd><a name="index-target_0028_0022recip_002dprecision_0022_0029-function-attribute_002c-PowerPC"></a>

  220. <p>Assume (do not assume) that the reciprocal estimate instructions

  221. provide higher-precision estimates than is mandated by the PowerPC

  222. ABI.

  223. </p>

  224. </dd>

  225. <dt>&lsquo;<samp>string</samp>&rsquo;</dt>

  226. <dt>&lsquo;<samp>no-string</samp>&rsquo;</dt>

  227. <dd><a name="index-target_0028_0022string_0022_0029-function-attribute_002c-PowerPC"></a>

  228. <p>Generate code that uses (does not use) the load string instructions

  229. and the store string word instructions to save multiple registers and

  230. do small block moves.

  231. </p>

  232. </dd>

  233. <dt>&lsquo;<samp>vsx</samp>&rsquo;</dt>

  234. <dt>&lsquo;<samp>no-vsx</samp>&rsquo;</dt>

  235. <dd><a name="index-target_0028_0022vsx_0022_0029-function-attribute_002c-PowerPC"></a>

  236. <p>Generate code that uses (does not use) vector/scalar (VSX)

  237. instructions, and also enable the use of built-in functions that allow

  238. more direct access to the VSX instruction set.  In 32-bit code, you

  239. cannot enable VSX or AltiVec instructions unless

  240. <samp>-mabi=altivec</samp> is used on the command line.

  241. </p>

  242. </dd>

  243. <dt>&lsquo;<samp>friz</samp>&rsquo;</dt>

  244. <dt>&lsquo;<samp>no-friz</samp>&rsquo;</dt>

  245. <dd><a name="index-target_0028_0022friz_0022_0029-function-attribute_002c-PowerPC"></a>

  246. <p>Generate (do not generate) the <code>friz</code> instruction when the

  247. <samp>-funsafe-math-optimizations</samp> option is used to optimize

  248. rounding a floating-point value to 64-bit integer and back to floating

  249. point.  The <code>friz</code> instruction does not return the same value if

  250. the floating-point number is too large to fit in an integer.

  251. </p>

  252. </dd>

  253. <dt>&lsquo;<samp>avoid-indexed-addresses</samp>&rsquo;</dt>

  254. <dt>&lsquo;<samp>no-avoid-indexed-addresses</samp>&rsquo;</dt>

  255. <dd><a name="index-target_0028_0022avoid_002dindexed_002daddresses_0022_0029-function-attribute_002c-PowerPC"></a>

  256. <p>Generate code that tries to avoid (not avoid) the use of indexed load

  257. or store instructions.

  258. </p>

  259. </dd>

  260. <dt>&lsquo;<samp>paired</samp>&rsquo;</dt>

  261. <dt>&lsquo;<samp>no-paired</samp>&rsquo;</dt>

  262. <dd><a name="index-target_0028_0022paired_0022_0029-function-attribute_002c-PowerPC"></a>

  263. <p>Generate code that uses (does not use) the generation of PAIRED simd

  264. instructions.

  265. </p>

  266. </dd>

  267. <dt>&lsquo;<samp>longcall</samp>&rsquo;</dt>

  268. <dt>&lsquo;<samp>no-longcall</samp>&rsquo;</dt>

  269. <dd><a name="index-target_0028_0022longcall_0022_0029-function-attribute_002c-PowerPC"></a>

  270. <p>Generate code that assumes (does not assume) that all calls are far

  271. away so that a longer more expensive calling sequence is required.

  272. </p>

  273. </dd>

  274. <dt>&lsquo;<samp>cpu=<var>CPU</var></samp>&rsquo;</dt>

  275. <dd><a name="index-target_0028_0022cpu_003dCPU_0022_0029-function-attribute_002c-PowerPC"></a>

  276. <p>Specify the architecture to generate code for when compiling the

  277. function.  If you select the <code>target(&quot;cpu=power7&quot;)</code> attribute when

  278. generating 32-bit code, VSX and AltiVec instructions are not generated

  279. unless you use the <samp>-mabi=altivec</samp> option on the command line.

  280. </p>

  281. </dd>

  282. <dt>&lsquo;<samp>tune=<var>TUNE</var></samp>&rsquo;</dt>

  283. <dd><a name="index-target_0028_0022tune_003dTUNE_0022_0029-function-attribute_002c-PowerPC"></a>

  284. <p>Specify the architecture to tune for when compiling the function.  If

  285. you do not specify the <code>target(&quot;tune=<var>TUNE</var>&quot;)</code> attribute and

  286. you do specify the <code>target(&quot;cpu=<var>CPU</var>&quot;)</code> attribute,

  287. compilation tunes for the <var>CPU</var> architecture, and not the

  288. default tuning specified on the command line.

  289. </p></dd>

  290. </dl>

  291. 

  292. <p>On the PowerPC, the inliner does not inline a

  293. function that has different target options than the caller, unless the

  294. callee has a subset of the target options of the caller.

  295. </p></dd>

  296. </dl>

  297. 

  298. <hr>

  299. <div class="header">

  300. <p>

  301. Next: <a href="RISC_002dV-Function-Attributes.html#RISC_002dV-Function-Attributes" accesskey="n" rel="next">RISC-V Function Attributes</a>, Previous: <a href="Nvidia-PTX-Function-Attributes.html#Nvidia-PTX-Function-Attributes" accesskey="p" rel="prev">Nvidia PTX Function Attributes</a>, Up: <a href="Function-Attributes.html#Function-Attributes" accesskey="u" rel="up">Function Attributes</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>

  302. </div>

  303. 

  304. 

  305. 

  306. </body>

  307. </html>