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  1. <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">

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  25. <title>RS/6000 and PowerPC Options (Using the GNU Compiler Collection (GCC))</title>

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  33. <link href="Option-Index.html#Option-Index" rel="index" title="Option Index">

  34. <link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">

  35. <link href="Submodel-Options.html#Submodel-Options" rel="up" title="Submodel Options">

  36. <link href="RX-Options.html#RX-Options" rel="next" title="RX Options">

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  67. </head>

  68. 

  69. <body lang="en">

  70. <a name="RS_002f6000-and-PowerPC-Options"></a>

  71. <div class="header">

  72. <p>

  73. Next: <a href="RX-Options.html#RX-Options" accesskey="n" rel="next">RX Options</a>, Previous: <a href="RL78-Options.html#RL78-Options" accesskey="p" rel="prev">RL78 Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>

  74. </div>

  75. <hr>

  76. <a name="IBM-RS_002f6000-and-PowerPC-Options"></a>

  77. <h4 class="subsection">3.19.44 IBM RS/6000 and PowerPC Options</h4>

  78. <a name="index-RS_002f6000-and-PowerPC-Options"></a>

  79. <a name="index-IBM-RS_002f6000-and-PowerPC-Options"></a>

  80. 

  81. <p>These &lsquo;<samp>-m</samp>&rsquo; options are defined for the IBM RS/6000 and PowerPC:

  82. </p><dl compact="compact">

  83. <dt><code>-mpowerpc-gpopt</code></dt>

  84. <dt><code>-mno-powerpc-gpopt</code></dt>

  85. <dt><code>-mpowerpc-gfxopt</code></dt>

  86. <dt><code>-mno-powerpc-gfxopt</code></dt>

  87. <dt><code>-mpowerpc64</code></dt>

  88. <dt><code>-mno-powerpc64</code></dt>

  89. <dt><code>-mmfcrf</code></dt>

  90. <dt><code>-mno-mfcrf</code></dt>

  91. <dt><code>-mpopcntb</code></dt>

  92. <dt><code>-mno-popcntb</code></dt>

  93. <dt><code>-mpopcntd</code></dt>

  94. <dt><code>-mno-popcntd</code></dt>

  95. <dt><code>-mfprnd</code></dt>

  96. <dt><code>-mno-fprnd</code></dt>

  97. <dt><code>-mcmpb</code></dt>

  98. <dt><code>-mno-cmpb</code></dt>

  99. <dt><code>-mhard-dfp</code></dt>

  100. <dt><code>-mno-hard-dfp</code></dt>

  101. <dd><a name="index-mpowerpc_002dgpopt"></a>

  102. <a name="index-mno_002dpowerpc_002dgpopt"></a>

  103. <a name="index-mpowerpc_002dgfxopt"></a>

  104. <a name="index-mno_002dpowerpc_002dgfxopt"></a>

  105. <a name="index-mpowerpc64"></a>

  106. <a name="index-mno_002dpowerpc64"></a>

  107. <a name="index-mmfcrf"></a>

  108. <a name="index-mno_002dmfcrf"></a>

  109. <a name="index-mpopcntb"></a>

  110. <a name="index-mno_002dpopcntb"></a>

  111. <a name="index-mpopcntd"></a>

  112. <a name="index-mno_002dpopcntd"></a>

  113. <a name="index-mfprnd"></a>

  114. <a name="index-mno_002dfprnd"></a>

  115. <a name="index-mcmpb"></a>

  116. <a name="index-mno_002dcmpb"></a>

  117. <a name="index-mhard_002ddfp"></a>

  118. <a name="index-mno_002dhard_002ddfp"></a>

  119. <p>You use these options to specify which instructions are available on the

  120. processor you are using.  The default value of these options is

  121. determined when configuring GCC.  Specifying the

  122. <samp>-mcpu=<var>cpu_type</var></samp> overrides the specification of these

  123. options.  We recommend you use the <samp>-mcpu=<var>cpu_type</var></samp> option

  124. rather than the options listed above.

  125. </p>

  126. <p>Specifying <samp>-mpowerpc-gpopt</samp> allows

  127. GCC to use the optional PowerPC architecture instructions in the

  128. General Purpose group, including floating-point square root.  Specifying

  129. <samp>-mpowerpc-gfxopt</samp> allows GCC to

  130. use the optional PowerPC architecture instructions in the Graphics

  131. group, including floating-point select.

  132. </p>

  133. <p>The <samp>-mmfcrf</samp> option allows GCC to generate the move from

  134. condition register field instruction implemented on the POWER4

  135. processor and other processors that support the PowerPC V2.01

  136. architecture.

  137. The <samp>-mpopcntb</samp> option allows GCC to generate the popcount and

  138. double-precision FP reciprocal estimate instruction implemented on the

  139. POWER5 processor and other processors that support the PowerPC V2.02

  140. architecture.

  141. The <samp>-mpopcntd</samp> option allows GCC to generate the popcount

  142. instruction implemented on the POWER7 processor and other processors

  143. that support the PowerPC V2.06 architecture.

  144. The <samp>-mfprnd</samp> option allows GCC to generate the FP round to

  145. integer instructions implemented on the POWER5+ processor and other

  146. processors that support the PowerPC V2.03 architecture.

  147. The <samp>-mcmpb</samp> option allows GCC to generate the compare bytes

  148. instruction implemented on the POWER6 processor and other processors

  149. that support the PowerPC V2.05 architecture.

  150. The <samp>-mhard-dfp</samp> option allows GCC to generate the decimal

  151. floating-point instructions implemented on some POWER processors.

  152. </p>

  153. <p>The <samp>-mpowerpc64</samp> option allows GCC to generate the additional

  154. 64-bit instructions that are found in the full PowerPC64 architecture

  155. and to treat GPRs as 64-bit, doubleword quantities.  GCC defaults to

  156. <samp>-mno-powerpc64</samp>.

  157. </p>

  158. </dd>

  159. <dt><code>-mcpu=<var>cpu_type</var></code></dt>

  160. <dd><a name="index-mcpu-9"></a>

  161. <p>Set architecture type, register usage, and

  162. instruction scheduling parameters for machine type <var>cpu_type</var>.

  163. Supported values for <var>cpu_type</var> are &lsquo;<samp>401</samp>&rsquo;, &lsquo;<samp>403</samp>&rsquo;,

  164. &lsquo;<samp>405</samp>&rsquo;, &lsquo;<samp>405fp</samp>&rsquo;, &lsquo;<samp>440</samp>&rsquo;, &lsquo;<samp>440fp</samp>&rsquo;, &lsquo;<samp>464</samp>&rsquo;, &lsquo;<samp>464fp</samp>&rsquo;,

  165. &lsquo;<samp>476</samp>&rsquo;, &lsquo;<samp>476fp</samp>&rsquo;, &lsquo;<samp>505</samp>&rsquo;, &lsquo;<samp>601</samp>&rsquo;, &lsquo;<samp>602</samp>&rsquo;, &lsquo;<samp>603</samp>&rsquo;,

  166. &lsquo;<samp>603e</samp>&rsquo;, &lsquo;<samp>604</samp>&rsquo;, &lsquo;<samp>604e</samp>&rsquo;, &lsquo;<samp>620</samp>&rsquo;, &lsquo;<samp>630</samp>&rsquo;, &lsquo;<samp>740</samp>&rsquo;,

  167. &lsquo;<samp>7400</samp>&rsquo;, &lsquo;<samp>7450</samp>&rsquo;, &lsquo;<samp>750</samp>&rsquo;, &lsquo;<samp>801</samp>&rsquo;, &lsquo;<samp>821</samp>&rsquo;, &lsquo;<samp>823</samp>&rsquo;,

  168. &lsquo;<samp>860</samp>&rsquo;, &lsquo;<samp>970</samp>&rsquo;, &lsquo;<samp>8540</samp>&rsquo;, &lsquo;<samp>a2</samp>&rsquo;, &lsquo;<samp>e300c2</samp>&rsquo;,

  169. &lsquo;<samp>e300c3</samp>&rsquo;, &lsquo;<samp>e500mc</samp>&rsquo;, &lsquo;<samp>e500mc64</samp>&rsquo;, &lsquo;<samp>e5500</samp>&rsquo;,

  170. &lsquo;<samp>e6500</samp>&rsquo;, &lsquo;<samp>ec603e</samp>&rsquo;, &lsquo;<samp>G3</samp>&rsquo;, &lsquo;<samp>G4</samp>&rsquo;, &lsquo;<samp>G5</samp>&rsquo;,

  171. &lsquo;<samp>titan</samp>&rsquo;, &lsquo;<samp>power3</samp>&rsquo;, &lsquo;<samp>power4</samp>&rsquo;, &lsquo;<samp>power5</samp>&rsquo;, &lsquo;<samp>power5+</samp>&rsquo;,

  172. &lsquo;<samp>power6</samp>&rsquo;, &lsquo;<samp>power6x</samp>&rsquo;, &lsquo;<samp>power7</samp>&rsquo;, &lsquo;<samp>power8</samp>&rsquo;,

  173. &lsquo;<samp>power9</samp>&rsquo;, &lsquo;<samp>future</samp>&rsquo;, &lsquo;<samp>powerpc</samp>&rsquo;, &lsquo;<samp>powerpc64</samp>&rsquo;,

  174. &lsquo;<samp>powerpc64le</samp>&rsquo;, &lsquo;<samp>rs64</samp>&rsquo;, and &lsquo;<samp>native</samp>&rsquo;.

  175. </p>

  176. <p><samp>-mcpu=powerpc</samp>, <samp>-mcpu=powerpc64</samp>, and

  177. <samp>-mcpu=powerpc64le</samp> specify pure 32-bit PowerPC (either

  178. endian), 64-bit big endian PowerPC and 64-bit little endian PowerPC

  179. architecture machine types, with an appropriate, generic processor

  180. model assumed for scheduling purposes.

  181. </p>

  182. <p>Specifying &lsquo;<samp>native</samp>&rsquo; as cpu type detects and selects the

  183. architecture option that corresponds to the host processor of the

  184. system performing the compilation.

  185. <samp>-mcpu=native</samp> has no effect if GCC does not recognize the

  186. processor.

  187. </p>

  188. <p>The other options specify a specific processor.  Code generated under

  189. those options runs best on that processor, and may not run at all on

  190. others.

  191. </p>

  192. <p>The <samp>-mcpu</samp> options automatically enable or disable the

  193. following options:

  194. </p>

  195. <div class="smallexample">

  196. <pre class="smallexample">-maltivec  -mfprnd  -mhard-float  -mmfcrf  -mmultiple 

  197. -mpopcntb  -mpopcntd  -mpowerpc64 

  198. -mpowerpc-gpopt  -mpowerpc-gfxopt 

  199. -mmulhw  -mdlmzb  -mmfpgpr  -mvsx 

  200. -mcrypto  -mhtm  -mpower8-fusion  -mpower8-vector 

  201. -mquad-memory  -mquad-memory-atomic  -mfloat128 

  202. -mfloat128-hardware -mprefixed -mpcrel -mmma

  203. </pre></div>

  204. 

  205. <p>The particular options set for any particular CPU varies between

  206. compiler versions, depending on what setting seems to produce optimal

  207. code for that CPU; it doesn&rsquo;t necessarily reflect the actual hardware&rsquo;s

  208. capabilities.  If you wish to set an individual option to a particular

  209. value, you may specify it after the <samp>-mcpu</samp> option, like

  210. <samp>-mcpu=970 -mno-altivec</samp>.

  211. </p>

  212. <p>On AIX, the <samp>-maltivec</samp> and <samp>-mpowerpc64</samp> options are

  213. not enabled or disabled by the <samp>-mcpu</samp> option at present because

  214. AIX does not have full support for these options.  You may still

  215. enable or disable them individually if you&rsquo;re sure it&rsquo;ll work in your

  216. environment.

  217. </p>

  218. </dd>

  219. <dt><code>-mtune=<var>cpu_type</var></code></dt>

  220. <dd><a name="index-mtune-12"></a>

  221. <p>Set the instruction scheduling parameters for machine type

  222. <var>cpu_type</var>, but do not set the architecture type or register usage,

  223. as <samp>-mcpu=<var>cpu_type</var></samp> does.  The same

  224. values for <var>cpu_type</var> are used for <samp>-mtune</samp> as for

  225. <samp>-mcpu</samp>.  If both are specified, the code generated uses the

  226. architecture and registers set by <samp>-mcpu</samp>, but the

  227. scheduling parameters set by <samp>-mtune</samp>.

  228. </p>

  229. </dd>

  230. <dt><code>-mcmodel=small</code></dt>

  231. <dd><a name="index-mcmodel_003dsmall-1"></a>

  232. <p>Generate PowerPC64 code for the small model: The TOC is limited to

  233. 64k.

  234. </p>

  235. </dd>

  236. <dt><code>-mcmodel=medium</code></dt>

  237. <dd><a name="index-mcmodel_003dmedium"></a>

  238. <p>Generate PowerPC64 code for the medium model: The TOC and other static

  239. data may be up to a total of 4G in size.  This is the default for 64-bit

  240. Linux.

  241. </p>

  242. </dd>

  243. <dt><code>-mcmodel=large</code></dt>

  244. <dd><a name="index-mcmodel_003dlarge-1"></a>

  245. <p>Generate PowerPC64 code for the large model: The TOC may be up to 4G

  246. in size.  Other data and code is only limited by the 64-bit address

  247. space.

  248. </p>

  249. </dd>

  250. <dt><code>-maltivec</code></dt>

  251. <dt><code>-mno-altivec</code></dt>

  252. <dd><a name="index-maltivec"></a>

  253. <a name="index-mno_002daltivec"></a>

  254. <p>Generate code that uses (does not use) AltiVec instructions, and also

  255. enable the use of built-in functions that allow more direct access to

  256. the AltiVec instruction set.  You may also need to set

  257. <samp>-mabi=altivec</samp> to adjust the current ABI with AltiVec ABI

  258. enhancements.

  259. </p>

  260. <p>When <samp>-maltivec</samp> is used, the element order for AltiVec intrinsics

  261. such as <code>vec_splat</code>, <code>vec_extract</code>, and <code>vec_insert</code> 

  262. match array element order corresponding to the endianness of the

  263. target.  That is, element zero identifies the leftmost element in a

  264. vector register when targeting a big-endian platform, and identifies

  265. the rightmost element in a vector register when targeting a

  266. little-endian platform.

  267. </p>

  268. </dd>

  269. <dt><code>-mvrsave</code></dt>

  270. <dt><code>-mno-vrsave</code></dt>

  271. <dd><a name="index-mvrsave"></a>

  272. <a name="index-mno_002dvrsave"></a>

  273. <p>Generate VRSAVE instructions when generating AltiVec code.

  274. </p>

  275. </dd>

  276. <dt><code>-msecure-plt</code></dt>

  277. <dd><a name="index-msecure_002dplt"></a>

  278. <p>Generate code that allows <code>ld</code> and <code>ld.so</code>

  279. to build executables and shared

  280. libraries with non-executable <code>.plt</code> and <code>.got</code> sections.

  281. This is a PowerPC

  282. 32-bit SYSV ABI option.

  283. </p>

  284. </dd>

  285. <dt><code>-mbss-plt</code></dt>

  286. <dd><a name="index-mbss_002dplt"></a>

  287. <p>Generate code that uses a BSS <code>.plt</code> section that <code>ld.so</code>

  288. fills in, and

  289. requires <code>.plt</code> and <code>.got</code>

  290. sections that are both writable and executable.

  291. This is a PowerPC 32-bit SYSV ABI option.

  292. </p>

  293. </dd>

  294. <dt><code>-misel</code></dt>

  295. <dt><code>-mno-isel</code></dt>

  296. <dd><a name="index-misel"></a>

  297. <a name="index-mno_002disel"></a>

  298. <p>This switch enables or disables the generation of ISEL instructions.

  299. </p>

  300. </dd>

  301. <dt><code>-mvsx</code></dt>

  302. <dt><code>-mno-vsx</code></dt>

  303. <dd><a name="index-mvsx"></a>

  304. <a name="index-mno_002dvsx"></a>

  305. <p>Generate code that uses (does not use) vector/scalar (VSX)

  306. instructions, and also enable the use of built-in functions that allow

  307. more direct access to the VSX instruction set.

  308. </p>

  309. </dd>

  310. <dt><code>-mcrypto</code></dt>

  311. <dt><code>-mno-crypto</code></dt>

  312. <dd><a name="index-mcrypto"></a>

  313. <a name="index-mno_002dcrypto"></a>

  314. <p>Enable the use (disable) of the built-in functions that allow direct

  315. access to the cryptographic instructions that were added in version

  316. 2.07 of the PowerPC ISA.

  317. </p>

  318. </dd>

  319. <dt><code>-mhtm</code></dt>

  320. <dt><code>-mno-htm</code></dt>

  321. <dd><a name="index-mhtm"></a>

  322. <a name="index-mno_002dhtm"></a>

  323. <p>Enable (disable) the use of the built-in functions that allow direct

  324. access to the Hardware Transactional Memory (HTM) instructions that

  325. were added in version 2.07 of the PowerPC ISA.

  326. </p>

  327. </dd>

  328. <dt><code>-mpower8-fusion</code></dt>

  329. <dt><code>-mno-power8-fusion</code></dt>

  330. <dd><a name="index-mpower8_002dfusion"></a>

  331. <a name="index-mno_002dpower8_002dfusion"></a>

  332. <p>Generate code that keeps (does not keeps) some integer operations

  333. adjacent so that the instructions can be fused together on power8 and

  334. later processors.

  335. </p>

  336. </dd>

  337. <dt><code>-mpower8-vector</code></dt>

  338. <dt><code>-mno-power8-vector</code></dt>

  339. <dd><a name="index-mpower8_002dvector"></a>

  340. <a name="index-mno_002dpower8_002dvector"></a>

  341. <p>Generate code that uses (does not use) the vector and scalar

  342. instructions that were added in version 2.07 of the PowerPC ISA.  Also

  343. enable the use of built-in functions that allow more direct access to

  344. the vector instructions.

  345. </p>

  346. </dd>

  347. <dt><code>-mquad-memory</code></dt>

  348. <dt><code>-mno-quad-memory</code></dt>

  349. <dd><a name="index-mquad_002dmemory"></a>

  350. <a name="index-mno_002dquad_002dmemory"></a>

  351. <p>Generate code that uses (does not use) the non-atomic quad word memory

  352. instructions.  The <samp>-mquad-memory</samp> option requires use of

  353. 64-bit mode.

  354. </p>

  355. </dd>

  356. <dt><code>-mquad-memory-atomic</code></dt>

  357. <dt><code>-mno-quad-memory-atomic</code></dt>

  358. <dd><a name="index-mquad_002dmemory_002datomic"></a>

  359. <a name="index-mno_002dquad_002dmemory_002datomic"></a>

  360. <p>Generate code that uses (does not use) the atomic quad word memory

  361. instructions.  The <samp>-mquad-memory-atomic</samp> option requires use of

  362. 64-bit mode.

  363. </p>

  364. </dd>

  365. <dt><code>-mfloat128</code></dt>

  366. <dt><code>-mno-float128</code></dt>

  367. <dd><a name="index-mfloat128"></a>

  368. <a name="index-mno_002dfloat128"></a>

  369. <p>Enable/disable the <var>__float128</var> keyword for IEEE 128-bit floating point

  370. and use either software emulation for IEEE 128-bit floating point or

  371. hardware instructions.

  372. </p>

  373. <p>The VSX instruction set (<samp>-mvsx</samp>, <samp>-mcpu=power7</samp>,

  374. <samp>-mcpu=power8</samp>), or <samp>-mcpu=power9</samp> must be enabled to

  375. use the IEEE 128-bit floating point support.  The IEEE 128-bit

  376. floating point support only works on PowerPC Linux systems.

  377. </p>

  378. <p>The default for <samp>-mfloat128</samp> is enabled on PowerPC Linux

  379. systems using the VSX instruction set, and disabled on other systems.

  380. </p>

  381. <p>If you use the ISA 3.0 instruction set (<samp>-mpower9-vector</samp> or

  382. <samp>-mcpu=power9</samp>) on a 64-bit system, the IEEE 128-bit floating

  383. point support will also enable the generation of ISA 3.0 IEEE 128-bit

  384. floating point instructions.  Otherwise, if you do not specify to

  385. generate ISA 3.0 instructions or you are targeting a 32-bit big endian

  386. system, IEEE 128-bit floating point will be done with software

  387. emulation.

  388. </p>

  389. </dd>

  390. <dt><code>-mfloat128-hardware</code></dt>

  391. <dt><code>-mno-float128-hardware</code></dt>

  392. <dd><a name="index-mfloat128_002dhardware"></a>

  393. <a name="index-mno_002dfloat128_002dhardware"></a>

  394. <p>Enable/disable using ISA 3.0 hardware instructions to support the

  395. <var>__float128</var> data type.

  396. </p>

  397. <p>The default for <samp>-mfloat128-hardware</samp> is enabled on PowerPC

  398. Linux systems using the ISA 3.0 instruction set, and disabled on other

  399. systems.

  400. </p>

  401. </dd>

  402. <dt><code>-m32</code></dt>

  403. <dt><code>-m64</code></dt>

  404. <dd><a name="index-m32-1"></a>

  405. <a name="index-m64-1"></a>

  406. <p>Generate code for 32-bit or 64-bit environments of Darwin and SVR4

  407. targets (including GNU/Linux).  The 32-bit environment sets int, long

  408. and pointer to 32 bits and generates code that runs on any PowerPC

  409. variant.  The 64-bit environment sets int to 32 bits and long and

  410. pointer to 64 bits, and generates code for PowerPC64, as for

  411. <samp>-mpowerpc64</samp>.

  412. </p>

  413. </dd>

  414. <dt><code>-mfull-toc</code></dt>

  415. <dt><code>-mno-fp-in-toc</code></dt>

  416. <dt><code>-mno-sum-in-toc</code></dt>

  417. <dt><code>-mminimal-toc</code></dt>

  418. <dd><a name="index-mfull_002dtoc"></a>

  419. <a name="index-mno_002dfp_002din_002dtoc"></a>

  420. <a name="index-mno_002dsum_002din_002dtoc"></a>

  421. <a name="index-mminimal_002dtoc"></a>

  422. <p>Modify generation of the TOC (Table Of Contents), which is created for

  423. every executable file.  The <samp>-mfull-toc</samp> option is selected by

  424. default.  In that case, GCC allocates at least one TOC entry for

  425. each unique non-automatic variable reference in your program.  GCC

  426. also places floating-point constants in the TOC.  However, only

  427. 16,384 entries are available in the TOC.

  428. </p>

  429. <p>If you receive a linker error message that saying you have overflowed

  430. the available TOC space, you can reduce the amount of TOC space used

  431. with the <samp>-mno-fp-in-toc</samp> and <samp>-mno-sum-in-toc</samp> options.

  432. <samp>-mno-fp-in-toc</samp> prevents GCC from putting floating-point

  433. constants in the TOC and <samp>-mno-sum-in-toc</samp> forces GCC to

  434. generate code to calculate the sum of an address and a constant at

  435. run time instead of putting that sum into the TOC.  You may specify one

  436. or both of these options.  Each causes GCC to produce very slightly

  437. slower and larger code at the expense of conserving TOC space.

  438. </p>

  439. <p>If you still run out of space in the TOC even when you specify both of

  440. these options, specify <samp>-mminimal-toc</samp> instead.  This option causes

  441. GCC to make only one TOC entry for every file.  When you specify this

  442. option, GCC produces code that is slower and larger but which

  443. uses extremely little TOC space.  You may wish to use this option

  444. only on files that contain less frequently-executed code.

  445. </p>

  446. </dd>

  447. <dt><code>-maix64</code></dt>

  448. <dt><code>-maix32</code></dt>

  449. <dd><a name="index-maix64"></a>

  450. <a name="index-maix32"></a>

  451. <p>Enable 64-bit AIX ABI and calling convention: 64-bit pointers, 64-bit

  452. <code>long</code> type, and the infrastructure needed to support them.

  453. Specifying <samp>-maix64</samp> implies <samp>-mpowerpc64</samp>,

  454. while <samp>-maix32</samp> disables the 64-bit ABI and

  455. implies <samp>-mno-powerpc64</samp>.  GCC defaults to <samp>-maix32</samp>.

  456. </p>

  457. </dd>

  458. <dt><code>-mxl-compat</code></dt>

  459. <dt><code>-mno-xl-compat</code></dt>

  460. <dd><a name="index-mxl_002dcompat"></a>

  461. <a name="index-mno_002dxl_002dcompat"></a>

  462. <p>Produce code that conforms more closely to IBM XL compiler semantics

  463. when using AIX-compatible ABI.  Pass floating-point arguments to

  464. prototyped functions beyond the register save area (RSA) on the stack

  465. in addition to argument FPRs.  Do not assume that most significant

  466. double in 128-bit long double value is properly rounded when comparing

  467. values and converting to double.  Use XL symbol names for long double

  468. support routines.

  469. </p>

  470. <p>The AIX calling convention was extended but not initially documented to

  471. handle an obscure K&amp;R C case of calling a function that takes the

  472. address of its arguments with fewer arguments than declared.  IBM XL

  473. compilers access floating-point arguments that do not fit in the

  474. RSA from the stack when a subroutine is compiled without

  475. optimization.  Because always storing floating-point arguments on the

  476. stack is inefficient and rarely needed, this option is not enabled by

  477. default and only is necessary when calling subroutines compiled by IBM

  478. XL compilers without optimization.

  479. </p>

  480. </dd>

  481. <dt><code>-mpe</code></dt>

  482. <dd><a name="index-mpe"></a>

  483. <p>Support <em>IBM RS/6000 SP</em> <em>Parallel Environment</em> (PE).  Link an

  484. application written to use message passing with special startup code to

  485. enable the application to run.  The system must have PE installed in the

  486. standard location (<samp>/usr/lpp/ppe.poe/</samp>), or the <samp>specs</samp> file

  487. must be overridden with the <samp>-specs=</samp> option to specify the

  488. appropriate directory location.  The Parallel Environment does not

  489. support threads, so the <samp>-mpe</samp> option and the <samp>-pthread</samp>

  490. option are incompatible.

  491. </p>

  492. </dd>

  493. <dt><code>-malign-natural</code></dt>

  494. <dt><code>-malign-power</code></dt>

  495. <dd><a name="index-malign_002dnatural"></a>

  496. <a name="index-malign_002dpower"></a>

  497. <p>On AIX, 32-bit Darwin, and 64-bit PowerPC GNU/Linux, the option

  498. <samp>-malign-natural</samp> overrides the ABI-defined alignment of larger

  499. types, such as floating-point doubles, on their natural size-based boundary.

  500. The option <samp>-malign-power</samp> instructs GCC to follow the ABI-specified

  501. alignment rules.  GCC defaults to the standard alignment defined in the ABI.

  502. </p>

  503. <p>On 64-bit Darwin, natural alignment is the default, and <samp>-malign-power</samp>

  504. is not supported.

  505. </p>

  506. </dd>

  507. <dt><code>-msoft-float</code></dt>

  508. <dt><code>-mhard-float</code></dt>

  509. <dd><a name="index-msoft_002dfloat-10"></a>

  510. <a name="index-mhard_002dfloat-6"></a>

  511. <p>Generate code that does not use (uses) the floating-point register set.

  512. Software floating-point emulation is provided if you use the

  513. <samp>-msoft-float</samp> option, and pass the option to GCC when linking.

  514. </p>

  515. </dd>

  516. <dt><code>-mmultiple</code></dt>

  517. <dt><code>-mno-multiple</code></dt>

  518. <dd><a name="index-mmultiple"></a>

  519. <a name="index-mno_002dmultiple"></a>

  520. <p>Generate code that uses (does not use) the load multiple word

  521. instructions and the store multiple word instructions.  These

  522. instructions are generated by default on POWER systems, and not

  523. generated on PowerPC systems.  Do not use <samp>-mmultiple</samp> on little-endian

  524. PowerPC systems, since those instructions do not work when the

  525. processor is in little-endian mode.  The exceptions are PPC740 and

  526. PPC750 which permit these instructions in little-endian mode.

  527. </p>

  528. </dd>

  529. <dt><code>-mupdate</code></dt>

  530. <dt><code>-mno-update</code></dt>

  531. <dd><a name="index-mupdate"></a>

  532. <a name="index-mno_002dupdate"></a>

  533. <p>Generate code that uses (does not use) the load or store instructions

  534. that update the base register to the address of the calculated memory

  535. location.  These instructions are generated by default.  If you use

  536. <samp>-mno-update</samp>, there is a small window between the time that the

  537. stack pointer is updated and the address of the previous frame is

  538. stored, which means code that walks the stack frame across interrupts or

  539. signals may get corrupted data.

  540. </p>

  541. </dd>

  542. <dt><code>-mavoid-indexed-addresses</code></dt>

  543. <dt><code>-mno-avoid-indexed-addresses</code></dt>

  544. <dd><a name="index-mavoid_002dindexed_002daddresses"></a>

  545. <a name="index-mno_002davoid_002dindexed_002daddresses"></a>

  546. <p>Generate code that tries to avoid (not avoid) the use of indexed load

  547. or store instructions. These instructions can incur a performance

  548. penalty on Power6 processors in certain situations, such as when

  549. stepping through large arrays that cross a 16M boundary.  This option

  550. is enabled by default when targeting Power6 and disabled otherwise.

  551. </p>

  552. </dd>

  553. <dt><code>-mfused-madd</code></dt>

  554. <dt><code>-mno-fused-madd</code></dt>

  555. <dd><a name="index-mfused_002dmadd-2"></a>

  556. <a name="index-mno_002dfused_002dmadd-2"></a>

  557. <p>Generate code that uses (does not use) the floating-point multiply and

  558. accumulate instructions.  These instructions are generated by default

  559. if hardware floating point is used.  The machine-dependent

  560. <samp>-mfused-madd</samp> option is now mapped to the machine-independent

  561. <samp>-ffp-contract=fast</samp> option, and <samp>-mno-fused-madd</samp> is

  562. mapped to <samp>-ffp-contract=off</samp>.

  563. </p>

  564. </dd>

  565. <dt><code>-mmulhw</code></dt>

  566. <dt><code>-mno-mulhw</code></dt>

  567. <dd><a name="index-mmulhw"></a>

  568. <a name="index-mno_002dmulhw"></a>

  569. <p>Generate code that uses (does not use) the half-word multiply and

  570. multiply-accumulate instructions on the IBM 405, 440, 464 and 476 processors.

  571. These instructions are generated by default when targeting those

  572. processors.

  573. </p>

  574. </dd>

  575. <dt><code>-mdlmzb</code></dt>

  576. <dt><code>-mno-dlmzb</code></dt>

  577. <dd><a name="index-mdlmzb"></a>

  578. <a name="index-mno_002ddlmzb"></a>

  579. <p>Generate code that uses (does not use) the string-search &lsquo;<samp>dlmzb</samp>&rsquo;

  580. instruction on the IBM 405, 440, 464 and 476 processors.  This instruction is

  581. generated by default when targeting those processors.

  582. </p>

  583. </dd>

  584. <dt><code>-mno-bit-align</code></dt>

  585. <dt><code>-mbit-align</code></dt>

  586. <dd><a name="index-mno_002dbit_002dalign"></a>

  587. <a name="index-mbit_002dalign"></a>

  588. <p>On System V.4 and embedded PowerPC systems do not (do) force structures

  589. and unions that contain bit-fields to be aligned to the base type of the

  590. bit-field.

  591. </p>

  592. <p>For example, by default a structure containing nothing but 8

  593. <code>unsigned</code> bit-fields of length 1 is aligned to a 4-byte

  594. boundary and has a size of 4 bytes.  By using <samp>-mno-bit-align</samp>,

  595. the structure is aligned to a 1-byte boundary and is 1 byte in

  596. size.

  597. </p>

  598. </dd>

  599. <dt><code>-mno-strict-align</code></dt>

  600. <dt><code>-mstrict-align</code></dt>

  601. <dd><a name="index-mno_002dstrict_002dalign-2"></a>

  602. <a name="index-mstrict_002dalign-3"></a>

  603. <p>On System V.4 and embedded PowerPC systems do not (do) assume that

  604. unaligned memory references are handled by the system.

  605. </p>

  606. </dd>

  607. <dt><code>-mrelocatable</code></dt>

  608. <dt><code>-mno-relocatable</code></dt>

  609. <dd><a name="index-mrelocatable"></a>

  610. <a name="index-mno_002drelocatable"></a>

  611. <p>Generate code that allows (does not allow) a static executable to be

  612. relocated to a different address at run time.  A simple embedded

  613. PowerPC system loader should relocate the entire contents of

  614. <code>.got2</code> and 4-byte locations listed in the <code>.fixup</code> section,

  615. a table of 32-bit addresses generated by this option.  For this to

  616. work, all objects linked together must be compiled with

  617. <samp>-mrelocatable</samp> or <samp>-mrelocatable-lib</samp>.

  618. <samp>-mrelocatable</samp> code aligns the stack to an 8-byte boundary.

  619. </p>

  620. </dd>

  621. <dt><code>-mrelocatable-lib</code></dt>

  622. <dt><code>-mno-relocatable-lib</code></dt>

  623. <dd><a name="index-mrelocatable_002dlib"></a>

  624. <a name="index-mno_002drelocatable_002dlib"></a>

  625. <p>Like <samp>-mrelocatable</samp>, <samp>-mrelocatable-lib</samp> generates a

  626. <code>.fixup</code> section to allow static executables to be relocated at

  627. run time, but <samp>-mrelocatable-lib</samp> does not use the smaller stack

  628. alignment of <samp>-mrelocatable</samp>.  Objects compiled with

  629. <samp>-mrelocatable-lib</samp> may be linked with objects compiled with

  630. any combination of the <samp>-mrelocatable</samp> options.

  631. </p>

  632. </dd>

  633. <dt><code>-mno-toc</code></dt>

  634. <dt><code>-mtoc</code></dt>

  635. <dd><a name="index-mno_002dtoc"></a>

  636. <a name="index-mtoc"></a>

  637. <p>On System V.4 and embedded PowerPC systems do not (do) assume that

  638. register 2 contains a pointer to a global area pointing to the addresses

  639. used in the program.

  640. </p>

  641. </dd>

  642. <dt><code>-mlittle</code></dt>

  643. <dt><code>-mlittle-endian</code></dt>

  644. <dd><a name="index-mlittle"></a>

  645. <a name="index-mlittle_002dendian-10"></a>

  646. <p>On System V.4 and embedded PowerPC systems compile code for the

  647. processor in little-endian mode.  The <samp>-mlittle-endian</samp> option is

  648. the same as <samp>-mlittle</samp>.

  649. </p>

  650. </dd>

  651. <dt><code>-mbig</code></dt>

  652. <dt><code>-mbig-endian</code></dt>

  653. <dd><a name="index-mbig"></a>

  654. <a name="index-mbig_002dendian-10"></a>

  655. <p>On System V.4 and embedded PowerPC systems compile code for the

  656. processor in big-endian mode.  The <samp>-mbig-endian</samp> option is

  657. the same as <samp>-mbig</samp>.

  658. </p>

  659. </dd>

  660. <dt><code>-mdynamic-no-pic</code></dt>

  661. <dd><a name="index-mdynamic_002dno_002dpic"></a>

  662. <p>On Darwin and Mac OS X systems, compile code so that it is not

  663. relocatable, but that its external references are relocatable.  The

  664. resulting code is suitable for applications, but not shared

  665. libraries.

  666. </p>

  667. </dd>

  668. <dt><code>-msingle-pic-base</code></dt>

  669. <dd><a name="index-msingle_002dpic_002dbase-1"></a>

  670. <p>Treat the register used for PIC addressing as read-only, rather than

  671. loading it in the prologue for each function.  The runtime system is

  672. responsible for initializing this register with an appropriate value

  673. before execution begins.

  674. </p>

  675. </dd>

  676. <dt><code>-mprioritize-restricted-insns=<var>priority</var></code></dt>

  677. <dd><a name="index-mprioritize_002drestricted_002dinsns"></a>

  678. <p>This option controls the priority that is assigned to

  679. dispatch-slot restricted instructions during the second scheduling

  680. pass.  The argument <var>priority</var> takes the value &lsquo;<samp>0</samp>&rsquo;, &lsquo;<samp>1</samp>&rsquo;,

  681. or &lsquo;<samp>2</samp>&rsquo; to assign no, highest, or second-highest (respectively) 

  682. priority to dispatch-slot restricted

  683. instructions.

  684. </p>

  685. </dd>

  686. <dt><code>-msched-costly-dep=<var>dependence_type</var></code></dt>

  687. <dd><a name="index-msched_002dcostly_002ddep"></a>

  688. <p>This option controls which dependences are considered costly

  689. by the target during instruction scheduling.  The argument

  690. <var>dependence_type</var> takes one of the following values:

  691. </p>

  692. <dl compact="compact">

  693. <dt>&lsquo;<samp>no</samp>&rsquo;</dt>

  694. <dd><p>No dependence is costly.

  695. </p>

  696. </dd>

  697. <dt>&lsquo;<samp>all</samp>&rsquo;</dt>

  698. <dd><p>All dependences are costly.

  699. </p>

  700. </dd>

  701. <dt>&lsquo;<samp>true_store_to_load</samp>&rsquo;</dt>

  702. <dd><p>A true dependence from store to load is costly.

  703. </p>

  704. </dd>

  705. <dt>&lsquo;<samp>store_to_load</samp>&rsquo;</dt>

  706. <dd><p>Any dependence from store to load is costly.

  707. </p>

  708. </dd>

  709. <dt><var>number</var></dt>

  710. <dd><p>Any dependence for which the latency is greater than or equal to 

  711. <var>number</var> is costly.

  712. </p></dd>

  713. </dl>

  714. 

  715. </dd>

  716. <dt><code>-minsert-sched-nops=<var>scheme</var></code></dt>

  717. <dd><a name="index-minsert_002dsched_002dnops"></a>

  718. <p>This option controls which NOP insertion scheme is used during

  719. the second scheduling pass.  The argument <var>scheme</var> takes one of the

  720. following values:

  721. </p>

  722. <dl compact="compact">

  723. <dt>&lsquo;<samp>no</samp>&rsquo;</dt>

  724. <dd><p>Don&rsquo;t insert NOPs.

  725. </p>

  726. </dd>

  727. <dt>&lsquo;<samp>pad</samp>&rsquo;</dt>

  728. <dd><p>Pad with NOPs any dispatch group that has vacant issue slots,

  729. according to the scheduler&rsquo;s grouping.

  730. </p>

  731. </dd>

  732. <dt>&lsquo;<samp>regroup_exact</samp>&rsquo;</dt>

  733. <dd><p>Insert NOPs to force costly dependent insns into

  734. separate groups.  Insert exactly as many NOPs as needed to force an insn

  735. to a new group, according to the estimated processor grouping.

  736. </p>

  737. </dd>

  738. <dt><var>number</var></dt>

  739. <dd><p>Insert NOPs to force costly dependent insns into

  740. separate groups.  Insert <var>number</var> NOPs to force an insn to a new group.

  741. </p></dd>

  742. </dl>

  743. 

  744. </dd>

  745. <dt><code>-mcall-sysv</code></dt>

  746. <dd><a name="index-mcall_002dsysv"></a>

  747. <p>On System V.4 and embedded PowerPC systems compile code using calling

  748. conventions that adhere to the March 1995 draft of the System V

  749. Application Binary Interface, PowerPC processor supplement.  This is the

  750. default unless you configured GCC using &lsquo;<samp>powerpc-*-eabiaix</samp>&rsquo;.

  751. </p>

  752. </dd>

  753. <dt><code>-mcall-sysv-eabi</code></dt>

  754. <dt><code>-mcall-eabi</code></dt>

  755. <dd><a name="index-mcall_002dsysv_002deabi"></a>

  756. <a name="index-mcall_002deabi"></a>

  757. <p>Specify both <samp>-mcall-sysv</samp> and <samp>-meabi</samp> options.

  758. </p>

  759. </dd>

  760. <dt><code>-mcall-sysv-noeabi</code></dt>

  761. <dd><a name="index-mcall_002dsysv_002dnoeabi"></a>

  762. <p>Specify both <samp>-mcall-sysv</samp> and <samp>-mno-eabi</samp> options.

  763. </p>

  764. </dd>

  765. <dt><code>-mcall-aixdesc</code></dt>

  766. <dd><a name="index-m"></a>

  767. <p>On System V.4 and embedded PowerPC systems compile code for the AIX

  768. operating system.

  769. </p>

  770. </dd>

  771. <dt><code>-mcall-linux</code></dt>

  772. <dd><a name="index-mcall_002dlinux"></a>

  773. <p>On System V.4 and embedded PowerPC systems compile code for the

  774. Linux-based GNU system.

  775. </p>

  776. </dd>

  777. <dt><code>-mcall-freebsd</code></dt>

  778. <dd><a name="index-mcall_002dfreebsd"></a>

  779. <p>On System V.4 and embedded PowerPC systems compile code for the

  780. FreeBSD operating system.

  781. </p>

  782. </dd>

  783. <dt><code>-mcall-netbsd</code></dt>

  784. <dd><a name="index-mcall_002dnetbsd"></a>

  785. <p>On System V.4 and embedded PowerPC systems compile code for the

  786. NetBSD operating system.

  787. </p>

  788. </dd>

  789. <dt><code>-mcall-openbsd</code></dt>

  790. <dd><a name="index-mcall_002dnetbsd-1"></a>

  791. <p>On System V.4 and embedded PowerPC systems compile code for the

  792. OpenBSD operating system.

  793. </p>

  794. </dd>

  795. <dt><code>-mtraceback=<var>traceback_type</var></code></dt>

  796. <dd><a name="index-mtraceback"></a>

  797. <p>Select the type of traceback table. Valid values for <var>traceback_type</var>

  798. are &lsquo;<samp>full</samp>&rsquo;, &lsquo;<samp>part</samp>&rsquo;, and &lsquo;<samp>no</samp>&rsquo;.

  799. </p>

  800. </dd>

  801. <dt><code>-maix-struct-return</code></dt>

  802. <dd><a name="index-maix_002dstruct_002dreturn"></a>

  803. <p>Return all structures in memory (as specified by the AIX ABI).

  804. </p>

  805. </dd>

  806. <dt><code>-msvr4-struct-return</code></dt>

  807. <dd><a name="index-msvr4_002dstruct_002dreturn"></a>

  808. <p>Return structures smaller than 8 bytes in registers (as specified by the

  809. SVR4 ABI).

  810. </p>

  811. </dd>

  812. <dt><code>-mabi=<var>abi-type</var></code></dt>

  813. <dd><a name="index-mabi-4"></a>

  814. <p>Extend the current ABI with a particular extension, or remove such extension.

  815. Valid values are &lsquo;<samp>altivec</samp>&rsquo;, &lsquo;<samp>no-altivec</samp>&rsquo;,

  816. &lsquo;<samp>ibmlongdouble</samp>&rsquo;, &lsquo;<samp>ieeelongdouble</samp>&rsquo;,

  817. &lsquo;<samp>elfv1</samp>&rsquo;, &lsquo;<samp>elfv2</samp>&rsquo;.

  818. </p>

  819. </dd>

  820. <dt><code>-mabi=ibmlongdouble</code></dt>

  821. <dd><a name="index-mabi_003dibmlongdouble"></a>

  822. <p>Change the current ABI to use IBM extended-precision long double.

  823. This is not likely to work if your system defaults to using IEEE

  824. extended-precision long double.  If you change the long double type

  825. from IEEE extended-precision, the compiler will issue a warning unless

  826. you use the <samp>-Wno-psabi</samp> option.  Requires <samp>-mlong-double-128</samp>

  827. to be enabled.

  828. </p>

  829. </dd>

  830. <dt><code>-mabi=ieeelongdouble</code></dt>

  831. <dd><a name="index-mabi_003dieeelongdouble"></a>

  832. <p>Change the current ABI to use IEEE extended-precision long double.

  833. This is not likely to work if your system defaults to using IBM

  834. extended-precision long double.  If you change the long double type

  835. from IBM extended-precision, the compiler will issue a warning unless

  836. you use the <samp>-Wno-psabi</samp> option.  Requires <samp>-mlong-double-128</samp>

  837. to be enabled.

  838. </p>

  839. </dd>

  840. <dt><code>-mabi=elfv1</code></dt>

  841. <dd><a name="index-mabi_003delfv1"></a>

  842. <p>Change the current ABI to use the ELFv1 ABI.

  843. This is the default ABI for big-endian PowerPC 64-bit Linux.

  844. Overriding the default ABI requires special system support and is

  845. likely to fail in spectacular ways.

  846. </p>

  847. </dd>

  848. <dt><code>-mabi=elfv2</code></dt>

  849. <dd><a name="index-mabi_003delfv2"></a>

  850. <p>Change the current ABI to use the ELFv2 ABI.

  851. This is the default ABI for little-endian PowerPC 64-bit Linux.

  852. Overriding the default ABI requires special system support and is

  853. likely to fail in spectacular ways.

  854. </p>

  855. </dd>

  856. <dt><code>-mgnu-attribute</code></dt>

  857. <dt><code>-mno-gnu-attribute</code></dt>

  858. <dd><a name="index-mgnu_002dattribute"></a>

  859. <a name="index-mno_002dgnu_002dattribute"></a>

  860. <p>Emit .gnu_attribute assembly directives to set tag/value pairs in a

  861. .gnu.attributes section that specify ABI variations in function

  862. parameters or return values.

  863. </p>

  864. </dd>

  865. <dt><code>-mprototype</code></dt>

  866. <dt><code>-mno-prototype</code></dt>

  867. <dd><a name="index-mprototype"></a>

  868. <a name="index-mno_002dprototype"></a>

  869. <p>On System V.4 and embedded PowerPC systems assume that all calls to

  870. variable argument functions are properly prototyped.  Otherwise, the

  871. compiler must insert an instruction before every non-prototyped call to

  872. set or clear bit 6 of the condition code register (<code>CR</code>) to

  873. indicate whether floating-point values are passed in the floating-point

  874. registers in case the function takes variable arguments.  With

  875. <samp>-mprototype</samp>, only calls to prototyped variable argument functions

  876. set or clear the bit.

  877. </p>

  878. </dd>

  879. <dt><code>-msim</code></dt>

  880. <dd><a name="index-msim-8"></a>

  881. <p>On embedded PowerPC systems, assume that the startup module is called

  882. <samp>sim-crt0.o</samp> and that the standard C libraries are <samp>libsim.a</samp> and

  883. <samp>libc.a</samp>.  This is the default for &lsquo;<samp>powerpc-*-eabisim</samp>&rsquo;

  884. configurations.

  885. </p>

  886. </dd>

  887. <dt><code>-mmvme</code></dt>

  888. <dd><a name="index-mmvme"></a>

  889. <p>On embedded PowerPC systems, assume that the startup module is called

  890. <samp>crt0.o</samp> and the standard C libraries are <samp>libmvme.a</samp> and

  891. <samp>libc.a</samp>.

  892. </p>

  893. </dd>

  894. <dt><code>-mads</code></dt>

  895. <dd><a name="index-mads"></a>

  896. <p>On embedded PowerPC systems, assume that the startup module is called

  897. <samp>crt0.o</samp> and the standard C libraries are <samp>libads.a</samp> and

  898. <samp>libc.a</samp>.

  899. </p>

  900. </dd>

  901. <dt><code>-myellowknife</code></dt>

  902. <dd><a name="index-myellowknife"></a>

  903. <p>On embedded PowerPC systems, assume that the startup module is called

  904. <samp>crt0.o</samp> and the standard C libraries are <samp>libyk.a</samp> and

  905. <samp>libc.a</samp>.

  906. </p>

  907. </dd>

  908. <dt><code>-mvxworks</code></dt>

  909. <dd><a name="index-mvxworks"></a>

  910. <p>On System V.4 and embedded PowerPC systems, specify that you are

  911. compiling for a VxWorks system.

  912. </p>

  913. </dd>

  914. <dt><code>-memb</code></dt>

  915. <dd><a name="index-memb"></a>

  916. <p>On embedded PowerPC systems, set the <code>PPC_EMB</code> bit in the ELF flags

  917. header to indicate that &lsquo;<samp>eabi</samp>&rsquo; extended relocations are used.

  918. </p>

  919. </dd>

  920. <dt><code>-meabi</code></dt>

  921. <dt><code>-mno-eabi</code></dt>

  922. <dd><a name="index-meabi"></a>

  923. <a name="index-mno_002deabi"></a>

  924. <p>On System V.4 and embedded PowerPC systems do (do not) adhere to the

  925. Embedded Applications Binary Interface (EABI), which is a set of

  926. modifications to the System V.4 specifications.  Selecting <samp>-meabi</samp>

  927. means that the stack is aligned to an 8-byte boundary, a function

  928. <code>__eabi</code> is called from <code>main</code> to set up the EABI

  929. environment, and the <samp>-msdata</samp> option can use both <code>r2</code> and

  930. <code>r13</code> to point to two separate small data areas.  Selecting

  931. <samp>-mno-eabi</samp> means that the stack is aligned to a 16-byte boundary,

  932. no EABI initialization function is called from <code>main</code>, and the

  933. <samp>-msdata</samp> option only uses <code>r13</code> to point to a single

  934. small data area.  The <samp>-meabi</samp> option is on by default if you

  935. configured GCC using one of the &lsquo;<samp>powerpc*-*-eabi*</samp>&rsquo; options.

  936. </p>

  937. </dd>

  938. <dt><code>-msdata=eabi</code></dt>

  939. <dd><a name="index-msdata_003deabi"></a>

  940. <p>On System V.4 and embedded PowerPC systems, put small initialized

  941. <code>const</code> global and static data in the <code>.sdata2</code> section, which

  942. is pointed to by register <code>r2</code>.  Put small initialized

  943. non-<code>const</code> global and static data in the <code>.sdata</code> section,

  944. which is pointed to by register <code>r13</code>.  Put small uninitialized

  945. global and static data in the <code>.sbss</code> section, which is adjacent to

  946. the <code>.sdata</code> section.  The <samp>-msdata=eabi</samp> option is

  947. incompatible with the <samp>-mrelocatable</samp> option.  The

  948. <samp>-msdata=eabi</samp> option also sets the <samp>-memb</samp> option.

  949. </p>

  950. </dd>

  951. <dt><code>-msdata=sysv</code></dt>

  952. <dd><a name="index-msdata_003dsysv"></a>

  953. <p>On System V.4 and embedded PowerPC systems, put small global and static

  954. data in the <code>.sdata</code> section, which is pointed to by register

  955. <code>r13</code>.  Put small uninitialized global and static data in the

  956. <code>.sbss</code> section, which is adjacent to the <code>.sdata</code> section.

  957. The <samp>-msdata=sysv</samp> option is incompatible with the

  958. <samp>-mrelocatable</samp> option.

  959. </p>

  960. </dd>

  961. <dt><code>-msdata=default</code></dt>

  962. <dt><code>-msdata</code></dt>

  963. <dd><a name="index-msdata_003ddefault-1"></a>

  964. <a name="index-msdata-2"></a>

  965. <p>On System V.4 and embedded PowerPC systems, if <samp>-meabi</samp> is used,

  966. compile code the same as <samp>-msdata=eabi</samp>, otherwise compile code the

  967. same as <samp>-msdata=sysv</samp>.

  968. </p>

  969. </dd>

  970. <dt><code>-msdata=data</code></dt>

  971. <dd><a name="index-msdata_003ddata"></a>

  972. <p>On System V.4 and embedded PowerPC systems, put small global

  973. data in the <code>.sdata</code> section.  Put small uninitialized global

  974. data in the <code>.sbss</code> section.  Do not use register <code>r13</code>

  975. to address small data however.  This is the default behavior unless

  976. other <samp>-msdata</samp> options are used.

  977. </p>

  978. </dd>

  979. <dt><code>-msdata=none</code></dt>

  980. <dt><code>-mno-sdata</code></dt>

  981. <dd><a name="index-msdata_003dnone-2"></a>

  982. <a name="index-mno_002dsdata-2"></a>

  983. <p>On embedded PowerPC systems, put all initialized global and static data

  984. in the <code>.data</code> section, and all uninitialized data in the

  985. <code>.bss</code> section.

  986. </p>

  987. </dd>

  988. <dt><code>-mreadonly-in-sdata</code></dt>

  989. <dd><a name="index-mreadonly_002din_002dsdata"></a>

  990. <a name="index-mno_002dreadonly_002din_002dsdata"></a>

  991. <p>Put read-only objects in the <code>.sdata</code> section as well.  This is the

  992. default.

  993. </p>

  994. </dd>

  995. <dt><code>-mblock-move-inline-limit=<var>num</var></code></dt>

  996. <dd><a name="index-mblock_002dmove_002dinline_002dlimit"></a>

  997. <p>Inline all block moves (such as calls to <code>memcpy</code> or structure

  998. copies) less than or equal to <var>num</var> bytes.  The minimum value for

  999. <var>num</var> is 32 bytes on 32-bit targets and 64 bytes on 64-bit

  1000. targets.  The default value is target-specific.

  1001. </p>

  1002. </dd>

  1003. <dt><code>-mblock-compare-inline-limit=<var>num</var></code></dt>

  1004. <dd><a name="index-mblock_002dcompare_002dinline_002dlimit"></a>

  1005. <p>Generate non-looping inline code for all block compares (such as calls

  1006. to <code>memcmp</code> or structure compares) less than or equal to <var>num</var>

  1007. bytes. If <var>num</var> is 0, all inline expansion (non-loop and loop) of

  1008. block compare is disabled. The default value is target-specific.

  1009. </p>

  1010. </dd>

  1011. <dt><code>-mblock-compare-inline-loop-limit=<var>num</var></code></dt>

  1012. <dd><a name="index-mblock_002dcompare_002dinline_002dloop_002dlimit"></a>

  1013. <p>Generate an inline expansion using loop code for all block compares that

  1014. are less than or equal to <var>num</var> bytes, but greater than the limit

  1015. for non-loop inline block compare expansion. If the block length is not

  1016. constant, at most <var>num</var> bytes will be compared before <code>memcmp</code>

  1017. is called to compare the remainder of the block. The default value is

  1018. target-specific.

  1019. </p>

  1020. </dd>

  1021. <dt><code>-mstring-compare-inline-limit=<var>num</var></code></dt>

  1022. <dd><a name="index-mstring_002dcompare_002dinline_002dlimit"></a>

  1023. <p>Compare at most <var>num</var> string bytes with inline code.

  1024. If the difference or end of string is not found at the

  1025. end of the inline compare a call to <code>strcmp</code> or <code>strncmp</code> will

  1026. take care of the rest of the comparison. The default is 64 bytes.

  1027. </p>

  1028. </dd>

  1029. <dt><code>-G <var>num</var></code></dt>

  1030. <dd><a name="index-G-4"></a>

  1031. <a name="index-smaller-data-references-_0028PowerPC_0029"></a>

  1032. <a name="index-_002esdata_002f_002esdata2-references-_0028PowerPC_0029"></a>

  1033. <p>On embedded PowerPC systems, put global and static items less than or

  1034. equal to <var>num</var> bytes into the small data or BSS sections instead of

  1035. the normal data or BSS section.  By default, <var>num</var> is 8.  The

  1036. <samp>-G <var>num</var></samp> switch is also passed to the linker.

  1037. All modules should be compiled with the same <samp>-G <var>num</var></samp> value.

  1038. </p>

  1039. </dd>

  1040. <dt><code>-mregnames</code></dt>

  1041. <dt><code>-mno-regnames</code></dt>

  1042. <dd><a name="index-mregnames"></a>

  1043. <a name="index-mno_002dregnames"></a>

  1044. <p>On System V.4 and embedded PowerPC systems do (do not) emit register

  1045. names in the assembly language output using symbolic forms.

  1046. </p>

  1047. </dd>

  1048. <dt><code>-mlongcall</code></dt>

  1049. <dt><code>-mno-longcall</code></dt>

  1050. <dd><a name="index-mlongcall"></a>

  1051. <a name="index-mno_002dlongcall"></a>

  1052. <p>By default assume that all calls are far away so that a longer and more

  1053. expensive calling sequence is required.  This is required for calls

  1054. farther than 32 megabytes (33,554,432 bytes) from the current location.

  1055. A short call is generated if the compiler knows

  1056. the call cannot be that far away.  This setting can be overridden by

  1057. the <code>shortcall</code> function attribute, or by <code>#pragma

  1058. longcall(0)</code>.

  1059. </p>

  1060. <p>Some linkers are capable of detecting out-of-range calls and generating

  1061. glue code on the fly.  On these systems, long calls are unnecessary and

  1062. generate slower code.  As of this writing, the AIX linker can do this,

  1063. as can the GNU linker for PowerPC/64.  It is planned to add this feature

  1064. to the GNU linker for 32-bit PowerPC systems as well.

  1065. </p>

  1066. <p>On PowerPC64 ELFv2 and 32-bit PowerPC systems with newer GNU linkers,

  1067. GCC can generate long calls using an inline PLT call sequence (see

  1068. <samp>-mpltseq</samp>).  PowerPC with <samp>-mbss-plt</samp> and PowerPC64

  1069. ELFv1 (big-endian) do not support inline PLT calls.

  1070. </p>

  1071. <p>On Darwin/PPC systems, <code>#pragma longcall</code> generates <code>jbsr

  1072. callee, L42</code>, plus a <em>branch island</em> (glue code).  The two target

  1073. addresses represent the callee and the branch island.  The

  1074. Darwin/PPC linker prefers the first address and generates a <code>bl

  1075. callee</code> if the PPC <code>bl</code> instruction reaches the callee directly;

  1076. otherwise, the linker generates <code>bl L42</code> to call the branch

  1077. island.  The branch island is appended to the body of the

  1078. calling function; it computes the full 32-bit address of the callee

  1079. and jumps to it.

  1080. </p>

  1081. <p>On Mach-O (Darwin) systems, this option directs the compiler emit to

  1082. the glue for every direct call, and the Darwin linker decides whether

  1083. to use or discard it.

  1084. </p>

  1085. <p>In the future, GCC may ignore all longcall specifications

  1086. when the linker is known to generate glue.

  1087. </p>

  1088. </dd>

  1089. <dt><code>-mpltseq</code></dt>

  1090. <dt><code>-mno-pltseq</code></dt>

  1091. <dd><a name="index-mpltseq"></a>

  1092. <a name="index-mno_002dpltseq"></a>

  1093. <p>Implement (do not implement) -fno-plt and long calls using an inline

  1094. PLT call sequence that supports lazy linking and long calls to

  1095. functions in dlopen&rsquo;d shared libraries.  Inline PLT calls are only

  1096. supported on PowerPC64 ELFv2 and 32-bit PowerPC systems with newer GNU

  1097. linkers, and are enabled by default if the support is detected when

  1098. configuring GCC, and, in the case of 32-bit PowerPC, if GCC is

  1099. configured with <samp>--enable-secureplt</samp>.  <samp>-mpltseq</samp> code

  1100. and <samp>-mbss-plt</samp> 32-bit PowerPC relocatable objects may not be

  1101. linked together.

  1102. </p>

  1103. </dd>

  1104. <dt><code>-mtls-markers</code></dt>

  1105. <dt><code>-mno-tls-markers</code></dt>

  1106. <dd><a name="index-mtls_002dmarkers"></a>

  1107. <a name="index-mno_002dtls_002dmarkers"></a>

  1108. <p>Mark (do not mark) calls to <code>__tls_get_addr</code> with a relocation

  1109. specifying the function argument.  The relocation allows the linker to

  1110. reliably associate function call with argument setup instructions for

  1111. TLS optimization, which in turn allows GCC to better schedule the

  1112. sequence.

  1113. </p>

  1114. </dd>

  1115. <dt><code>-mrecip</code></dt>

  1116. <dt><code>-mno-recip</code></dt>

  1117. <dd><a name="index-mrecip"></a>

  1118. <p>This option enables use of the reciprocal estimate and

  1119. reciprocal square root estimate instructions with additional

  1120. Newton-Raphson steps to increase precision instead of doing a divide or

  1121. square root and divide for floating-point arguments.  You should use

  1122. the <samp>-ffast-math</samp> option when using <samp>-mrecip</samp> (or at

  1123. least <samp>-funsafe-math-optimizations</samp>,

  1124. <samp>-ffinite-math-only</samp>, <samp>-freciprocal-math</samp> and

  1125. <samp>-fno-trapping-math</samp>).  Note that while the throughput of the

  1126. sequence is generally higher than the throughput of the non-reciprocal

  1127. instruction, the precision of the sequence can be decreased by up to 2

  1128. ulp (i.e. the inverse of 1.0 equals 0.99999994) for reciprocal square

  1129. roots.

  1130. </p>

  1131. </dd>

  1132. <dt><code>-mrecip=<var>opt</var></code></dt>

  1133. <dd><a name="index-mrecip_003dopt"></a>

  1134. <p>This option controls which reciprocal estimate instructions

  1135. may be used.  <var>opt</var> is a comma-separated list of options, which may

  1136. be preceded by a <code>!</code> to invert the option:

  1137. </p>

  1138. <dl compact="compact">

  1139. <dt>&lsquo;<samp>all</samp>&rsquo;</dt>

  1140. <dd><p>Enable all estimate instructions.

  1141. </p>

  1142. </dd>

  1143. <dt>&lsquo;<samp>default</samp>&rsquo;</dt>

  1144. <dd><p>Enable the default instructions, equivalent to <samp>-mrecip</samp>.

  1145. </p>

  1146. </dd>

  1147. <dt>&lsquo;<samp>none</samp>&rsquo;</dt>

  1148. <dd><p>Disable all estimate instructions, equivalent to <samp>-mno-recip</samp>.

  1149. </p>

  1150. </dd>

  1151. <dt>&lsquo;<samp>div</samp>&rsquo;</dt>

  1152. <dd><p>Enable the reciprocal approximation instructions for both 

  1153. single and double precision.

  1154. </p>

  1155. </dd>

  1156. <dt>&lsquo;<samp>divf</samp>&rsquo;</dt>

  1157. <dd><p>Enable the single-precision reciprocal approximation instructions.

  1158. </p>

  1159. </dd>

  1160. <dt>&lsquo;<samp>divd</samp>&rsquo;</dt>

  1161. <dd><p>Enable the double-precision reciprocal approximation instructions.

  1162. </p>

  1163. </dd>

  1164. <dt>&lsquo;<samp>rsqrt</samp>&rsquo;</dt>

  1165. <dd><p>Enable the reciprocal square root approximation instructions for both

  1166. single and double precision.

  1167. </p>

  1168. </dd>

  1169. <dt>&lsquo;<samp>rsqrtf</samp>&rsquo;</dt>

  1170. <dd><p>Enable the single-precision reciprocal square root approximation instructions.

  1171. </p>

  1172. </dd>

  1173. <dt>&lsquo;<samp>rsqrtd</samp>&rsquo;</dt>

  1174. <dd><p>Enable the double-precision reciprocal square root approximation instructions.

  1175. </p>

  1176. </dd>

  1177. </dl>

  1178. 

  1179. <p>So, for example, <samp>-mrecip=all,!rsqrtd</samp> enables

  1180. all of the reciprocal estimate instructions, except for the

  1181. <code>FRSQRTE</code>, <code>XSRSQRTEDP</code>, and <code>XVRSQRTEDP</code> instructions

  1182. which handle the double-precision reciprocal square root calculations.

  1183. </p>

  1184. </dd>

  1185. <dt><code>-mrecip-precision</code></dt>

  1186. <dt><code>-mno-recip-precision</code></dt>

  1187. <dd><a name="index-mrecip_002dprecision"></a>

  1188. <p>Assume (do not assume) that the reciprocal estimate instructions

  1189. provide higher-precision estimates than is mandated by the PowerPC

  1190. ABI.  Selecting <samp>-mcpu=power6</samp>, <samp>-mcpu=power7</samp> or

  1191. <samp>-mcpu=power8</samp> automatically selects <samp>-mrecip-precision</samp>.

  1192. The double-precision square root estimate instructions are not generated by

  1193. default on low-precision machines, since they do not provide an

  1194. estimate that converges after three steps.

  1195. </p>

  1196. </dd>

  1197. <dt><code>-mveclibabi=<var>type</var></code></dt>

  1198. <dd><a name="index-mveclibabi"></a>

  1199. <p>Specifies the ABI type to use for vectorizing intrinsics using an

  1200. external library.  The only type supported at present is &lsquo;<samp>mass</samp>&rsquo;,

  1201. which specifies to use IBM&rsquo;s Mathematical Acceleration Subsystem

  1202. (MASS) libraries for vectorizing intrinsics using external libraries.

  1203. GCC currently emits calls to <code>acosd2</code>, <code>acosf4</code>,

  1204. <code>acoshd2</code>, <code>acoshf4</code>, <code>asind2</code>, <code>asinf4</code>,

  1205. <code>asinhd2</code>, <code>asinhf4</code>, <code>atan2d2</code>, <code>atan2f4</code>,

  1206. <code>atand2</code>, <code>atanf4</code>, <code>atanhd2</code>, <code>atanhf4</code>,

  1207. <code>cbrtd2</code>, <code>cbrtf4</code>, <code>cosd2</code>, <code>cosf4</code>,

  1208. <code>coshd2</code>, <code>coshf4</code>, <code>erfcd2</code>, <code>erfcf4</code>,

  1209. <code>erfd2</code>, <code>erff4</code>, <code>exp2d2</code>, <code>exp2f4</code>,

  1210. <code>expd2</code>, <code>expf4</code>, <code>expm1d2</code>, <code>expm1f4</code>,

  1211. <code>hypotd2</code>, <code>hypotf4</code>, <code>lgammad2</code>, <code>lgammaf4</code>,

  1212. <code>log10d2</code>, <code>log10f4</code>, <code>log1pd2</code>, <code>log1pf4</code>,

  1213. <code>log2d2</code>, <code>log2f4</code>, <code>logd2</code>, <code>logf4</code>,

  1214. <code>powd2</code>, <code>powf4</code>, <code>sind2</code>, <code>sinf4</code>, <code>sinhd2</code>,

  1215. <code>sinhf4</code>, <code>sqrtd2</code>, <code>sqrtf4</code>, <code>tand2</code>,

  1216. <code>tanf4</code>, <code>tanhd2</code>, and <code>tanhf4</code> when generating code

  1217. for power7.  Both <samp>-ftree-vectorize</samp> and

  1218. <samp>-funsafe-math-optimizations</samp> must also be enabled.  The MASS

  1219. libraries must be specified at link time.

  1220. </p>

  1221. </dd>

  1222. <dt><code>-mfriz</code></dt>

  1223. <dt><code>-mno-friz</code></dt>

  1224. <dd><a name="index-mfriz"></a>

  1225. <p>Generate (do not generate) the <code>friz</code> instruction when the

  1226. <samp>-funsafe-math-optimizations</samp> option is used to optimize

  1227. rounding of floating-point values to 64-bit integer and back to floating

  1228. point.  The <code>friz</code> instruction does not return the same value if

  1229. the floating-point number is too large to fit in an integer.

  1230. </p>

  1231. </dd>

  1232. <dt><code>-mpointers-to-nested-functions</code></dt>

  1233. <dt><code>-mno-pointers-to-nested-functions</code></dt>

  1234. <dd><a name="index-mpointers_002dto_002dnested_002dfunctions"></a>

  1235. <p>Generate (do not generate) code to load up the static chain register

  1236. (<code>r11</code>) when calling through a pointer on AIX and 64-bit Linux

  1237. systems where a function pointer points to a 3-word descriptor giving

  1238. the function address, TOC value to be loaded in register <code>r2</code>, and

  1239. static chain value to be loaded in register <code>r11</code>.  The

  1240. <samp>-mpointers-to-nested-functions</samp> is on by default.  You cannot

  1241. call through pointers to nested functions or pointers

  1242. to functions compiled in other languages that use the static chain if

  1243. you use <samp>-mno-pointers-to-nested-functions</samp>.

  1244. </p>

  1245. </dd>

  1246. <dt><code>-msave-toc-indirect</code></dt>

  1247. <dt><code>-mno-save-toc-indirect</code></dt>

  1248. <dd><a name="index-msave_002dtoc_002dindirect"></a>

  1249. <p>Generate (do not generate) code to save the TOC value in the reserved

  1250. stack location in the function prologue if the function calls through

  1251. a pointer on AIX and 64-bit Linux systems.  If the TOC value is not

  1252. saved in the prologue, it is saved just before the call through the

  1253. pointer.  The <samp>-mno-save-toc-indirect</samp> option is the default.

  1254. </p>

  1255. </dd>

  1256. <dt><code>-mcompat-align-parm</code></dt>

  1257. <dt><code>-mno-compat-align-parm</code></dt>

  1258. <dd><a name="index-mcompat_002dalign_002dparm"></a>

  1259. <p>Generate (do not generate) code to pass structure parameters with a

  1260. maximum alignment of 64 bits, for compatibility with older versions

  1261. of GCC.

  1262. </p>

  1263. <p>Older versions of GCC (prior to 4.9.0) incorrectly did not align a

  1264. structure parameter on a 128-bit boundary when that structure contained

  1265. a member requiring 128-bit alignment.  This is corrected in more

  1266. recent versions of GCC.  This option may be used to generate code

  1267. that is compatible with functions compiled with older versions of

  1268. GCC.

  1269. </p>

  1270. <p>The <samp>-mno-compat-align-parm</samp> option is the default.

  1271. </p>

  1272. </dd>

  1273. <dt><code>-mstack-protector-guard=<var>guard</var></code></dt>

  1274. <dt><code>-mstack-protector-guard-reg=<var>reg</var></code></dt>

  1275. <dt><code>-mstack-protector-guard-offset=<var>offset</var></code></dt>

  1276. <dt><code>-mstack-protector-guard-symbol=<var>symbol</var></code></dt>

  1277. <dd><a name="index-mstack_002dprotector_002dguard-2"></a>

  1278. <a name="index-mstack_002dprotector_002dguard_002dreg-2"></a>

  1279. <a name="index-mstack_002dprotector_002dguard_002doffset-2"></a>

  1280. <a name="index-mstack_002dprotector_002dguard_002dsymbol"></a>

  1281. <p>Generate stack protection code using canary at <var>guard</var>.  Supported

  1282. locations are &lsquo;<samp>global</samp>&rsquo; for global canary or &lsquo;<samp>tls</samp>&rsquo; for per-thread

  1283. canary in the TLS block (the default with GNU libc version 2.4 or later).

  1284. </p>

  1285. <p>With the latter choice the options

  1286. <samp>-mstack-protector-guard-reg=<var>reg</var></samp> and

  1287. <samp>-mstack-protector-guard-offset=<var>offset</var></samp> furthermore specify

  1288. which register to use as base register for reading the canary, and from what

  1289. offset from that base register. The default for those is as specified in the

  1290. relevant ABI.  <samp>-mstack-protector-guard-symbol=<var>symbol</var></samp> overrides

  1291. the offset with a symbol reference to a canary in the TLS block.

  1292. </p>

  1293. </dd>

  1294. <dt><code>-mpcrel</code></dt>

  1295. <dt><code>-mno-pcrel</code></dt>

  1296. <dd><a name="index-mpcrel-1"></a>

  1297. <a name="index-mno_002dpcrel"></a>

  1298. <p>Generate (do not generate) pc-relative addressing when the option

  1299. <samp>-mcpu=future</samp> is used.  The <samp>-mpcrel</samp> option requires

  1300. that the medium code model (<samp>-mcmodel=medium</samp>) and prefixed

  1301. addressing (<samp>-mprefixed</samp>) options are enabled.

  1302. </p>

  1303. </dd>

  1304. <dt><code>-mprefixed</code></dt>

  1305. <dt><code>-mno-prefixed</code></dt>

  1306. <dd><a name="index-mprefixed"></a>

  1307. <a name="index-mno_002dprefixed"></a>

  1308. <p>Generate (do not generate) addressing modes using prefixed load and

  1309. store instructions when the option <samp>-mcpu=future</samp> is used.

  1310. </p>

  1311. </dd>

  1312. <dt><code>-mmma</code></dt>

  1313. <dt><code>-mno-mma</code></dt>

  1314. <dd><a name="index-mmma"></a>

  1315. <a name="index-mno_002dmma"></a>

  1316. <p>Generate (do not generate) the MMA instructions when the option

  1317. <samp>-mcpu=future</samp> is used.

  1318. </p></dd>

  1319. </dl>

  1320. 

  1321. <hr>

  1322. <div class="header">

  1323. <p>

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  1325. </div>

  1326. 

  1327. 

  1328. 

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