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  67. <a name="Order-of-Allocation-of-Registers"></a>
  68. <h4 class="subsection">18.7.2 Order of Allocation of Registers</h4>
  69. <a name="index-order-of-register-allocation"></a>
  70. <a name="index-register-allocation-order"></a>
  71. <p>Registers are allocated in order.
  72. </p>
  73. <dl>
  74. <dt><a name="index-REG_005fALLOC_005fORDER"></a>Macro: <strong>REG_ALLOC_ORDER</strong></dt>
  75. <dd><p>If defined, an initializer for a vector of integers, containing the
  76. numbers of hard registers in the order in which GCC should prefer
  77. to use them (from most preferred to least).
  78. </p>
  79. <p>If this macro is not defined, registers are used lowest numbered first
  80. (all else being equal).
  81. </p>
  82. <p>One use of this macro is on machines where the highest numbered
  83. registers must always be saved and the save-multiple-registers
  84. instruction supports only sequences of consecutive registers. On such
  85. machines, define <code>REG_ALLOC_ORDER</code> to be an initializer that lists
  86. the highest numbered allocable register first.
  87. </p></dd></dl>
  88. <dl>
  89. <dt><a name="index-ADJUST_005fREG_005fALLOC_005fORDER"></a>Macro: <strong>ADJUST_REG_ALLOC_ORDER</strong></dt>
  90. <dd><p>A C statement (sans semicolon) to choose the order in which to allocate
  91. hard registers for pseudo-registers local to a basic block.
  92. </p>
  93. <p>Store the desired register order in the array <code>reg_alloc_order</code>.
  94. Element 0 should be the register to allocate first; element 1, the next
  95. register; and so on.
  96. </p>
  97. <p>The macro body should not assume anything about the contents of
  98. <code>reg_alloc_order</code> before execution of the macro.
  99. </p>
  100. <p>On most machines, it is not necessary to define this macro.
  101. </p></dd></dl>
  102. <dl>
  103. <dt><a name="index-HONOR_005fREG_005fALLOC_005fORDER"></a>Macro: <strong>HONOR_REG_ALLOC_ORDER</strong></dt>
  104. <dd><p>Normally, IRA tries to estimate the costs for saving a register in the
  105. prologue and restoring it in the epilogue. This discourages it from
  106. using call-saved registers. If a machine wants to ensure that IRA
  107. allocates registers in the order given by REG_ALLOC_ORDER even if some
  108. call-saved registers appear earlier than call-used ones, then define this
  109. macro as a C expression to nonzero. Default is 0.
  110. </p></dd></dl>
  111. <dl>
  112. <dt><a name="index-IRA_005fHARD_005fREGNO_005fADD_005fCOST_005fMULTIPLIER"></a>Macro: <strong>IRA_HARD_REGNO_ADD_COST_MULTIPLIER</strong> <em>(<var>regno</var>)</em></dt>
  113. <dd><p>In some case register allocation order is not enough for the
  114. Integrated Register Allocator (<acronym>IRA</acronym>) to generate a good code.
  115. If this macro is defined, it should return a floating point value
  116. based on <var>regno</var>. The cost of using <var>regno</var> for a pseudo will
  117. be increased by approximately the pseudo&rsquo;s usage frequency times the
  118. value returned by this macro. Not defining this macro is equivalent
  119. to having it always return <code>0.0</code>.
  120. </p>
  121. <p>On most machines, it is not necessary to define this macro.
  122. </p></dd></dl>
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