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  20. <title>Condition Code (GNU Compiler Collection (GCC) Internals)</title>
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  64. Next: <a href="Costs.html#Costs" accesskey="n" rel="next">Costs</a>, Previous: <a href="Anchored-Addresses.html#Anchored-Addresses" accesskey="p" rel="prev">Anchored Addresses</a>, Up: <a href="Target-Macros.html#Target-Macros" accesskey="u" rel="up">Target Macros</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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  67. <a name="Condition-Code-Status"></a>
  68. <h3 class="section">18.15 Condition Code Status</h3>
  69. <a name="index-condition-code-status"></a>
  70. <p>The macros in this section can be split in two families, according to the
  71. two ways of representing condition codes in GCC.
  72. </p>
  73. <p>The first representation is the so called <code>(cc0)</code> representation
  74. (see <a href="Jump-Patterns.html#Jump-Patterns">Jump Patterns</a>), where all instructions can have an implicit
  75. clobber of the condition codes. The second is the condition code
  76. register representation, which provides better schedulability for
  77. architectures that do have a condition code register, but on which
  78. most instructions do not affect it. The latter category includes
  79. most RISC machines.
  80. </p>
  81. <p>The implicit clobbering poses a strong restriction on the placement of
  82. the definition and use of the condition code. In the past the definition
  83. and use were always adjacent. However, recent changes to support trapping
  84. arithmatic may result in the definition and user being in different blocks.
  85. Thus, there may be a <code>NOTE_INSN_BASIC_BLOCK</code> between them. Additionally,
  86. the definition may be the source of exception handling edges.
  87. </p>
  88. <p>These restrictions can prevent important
  89. optimizations on some machines. For example, on the IBM RS/6000, there
  90. is a delay for taken branches unless the condition code register is set
  91. three instructions earlier than the conditional branch. The instruction
  92. scheduler cannot perform this optimization if it is not permitted to
  93. separate the definition and use of the condition code register.
  94. </p>
  95. <p>For this reason, it is possible and suggested to use a register to
  96. represent the condition code for new ports. If there is a specific
  97. condition code register in the machine, use a hard register. If the
  98. condition code or comparison result can be placed in any general register,
  99. or if there are multiple condition registers, use a pseudo register.
  100. Registers used to store the condition code value will usually have a mode
  101. that is in class <code>MODE_CC</code>.
  102. </p>
  103. <p>Alternatively, you can use <code>BImode</code> if the comparison operator is
  104. specified already in the compare instruction. In this case, you are not
  105. interested in most macros in this section.
  106. </p>
  107. <table class="menu" border="0" cellspacing="0">
  108. <tr><td align="left" valign="top">&bull; <a href="CC0-Condition-Codes.html#CC0-Condition-Codes" accesskey="1">CC0 Condition Codes</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Old style representation of condition codes.
  109. </td></tr>
  110. <tr><td align="left" valign="top">&bull; <a href="MODE_005fCC-Condition-Codes.html#MODE_005fCC-Condition-Codes" accesskey="2">MODE_CC Condition Codes</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Modern representation of condition codes.
  111. </td></tr>
  112. </table>
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