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<a name="Defining-coprocessor-specifics-for-MIPS-targets_002e"></a>
<h3 class="section">18.26 Defining coprocessor specifics for MIPS targets.</h3>
<a name="index-MIPS-coprocessor_002ddefinition-macros"></a>

<p>The MIPS specification allows MIPS implementations to have as many as 4
coprocessors, each with as many as 32 private registers.  GCC supports
accessing these registers and transferring values between the registers
and memory using asm-ized variables.  For example:
</p>
<div class="smallexample">
<pre class="smallexample">  register unsigned int cp0count asm (&quot;c0r1&quot;);
  unsigned int d;

  d = cp0count + 3;
</pre></div>

<p>(&ldquo;c0r1&rdquo; is the default name of register 1 in coprocessor 0; alternate
names may be added as described below, or the default names may be
overridden entirely in <code>SUBTARGET_CONDITIONAL_REGISTER_USAGE</code>.)
</p>
<p>Coprocessor registers are assumed to be epilogue-used; sets to them will
be preserved even if it does not appear that the register is used again
later in the function.
</p>
<p>Another note: according to the MIPS spec, coprocessor 1 (if present) is
the FPU.  One accesses COP1 registers through standard mips
floating-point support; they are not included in this mechanism.
</p>


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