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  60. Previous: <a href="MIPS-Register-packet-Format.html#MIPS-Register-packet-Format" accesskey="p" rel="prev">MIPS Register packet Format</a>, Up: <a href="MIPS_002dSpecific-Protocol-Details.html#MIPS_002dSpecific-Protocol-Details" accesskey="u" rel="up">MIPS-Specific Protocol Details</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Concept-Index.html#Concept-Index" title="Index" rel="index">Index</a>]</p>
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  63. <a name="MIPS-Breakpoint-Kinds-1"></a>
  64. <h4 class="subsubsection">E.5.2.2 <acronym>MIPS</acronym> Breakpoint Kinds</h4>
  65. <a name="index-breakpoint-kinds_002c-MIPS"></a>
  66. <p>These breakpoint kinds are defined for the &lsquo;<samp>Z0</samp>&rsquo; and &lsquo;<samp>Z1</samp>&rsquo; packets.
  67. </p>
  68. <dl compact="compact">
  69. <dt><span class="roman">2</span></dt>
  70. <dd><p>16-bit <acronym>MIPS16</acronym> mode breakpoint.
  71. </p>
  72. </dd>
  73. <dt><span class="roman">3</span></dt>
  74. <dd><p>16-bit <acronym>microMIPS</acronym> mode breakpoint.
  75. </p>
  76. </dd>
  77. <dt><span class="roman">4</span></dt>
  78. <dd><p>32-bit standard <acronym>MIPS</acronym> mode breakpoint.
  79. </p>
  80. </dd>
  81. <dt><span class="roman">5</span></dt>
  82. <dd><p>32-bit <acronym>microMIPS</acronym> mode breakpoint.
  83. </p>
  84. </dd>
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