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- <a name="RISC_002dV-Features"></a>
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- Next: <a href="RX-Features.html#RX-Features" accesskey="n" rel="next">RX Features</a>, Previous: <a href="PowerPC-Features.html#PowerPC-Features" accesskey="p" rel="prev">PowerPC Features</a>, Up: <a href="Standard-Target-Features.html#Standard-Target-Features" accesskey="u" rel="up">Standard Target Features</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Concept-Index.html#Concept-Index" title="Index" rel="index">Index</a>]</p>
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- <a name="RISC_002dV-Features-1"></a>
- <h4 class="subsection">G.5.12 RISC-V Features</h4>
- <a name="index-target-descriptions_002c-RISC_002dV-Features"></a>
-
- <p>The ‘<samp>org.gnu.gdb.riscv.cpu</samp>’ feature is required for RISC-V
- targets. It should contain the registers ‘<samp>x0</samp>’ through
- ‘<samp>x31</samp>’, and ‘<samp>pc</samp>’. Either the architectural names (‘<samp>x0</samp>’,
- ‘<samp>x1</samp>’, etc) can be used, or the ABI names (‘<samp>zero</samp>’, ‘<samp>ra</samp>’,
- etc).
- </p>
- <p>The ‘<samp>org.gnu.gdb.riscv.fpu</samp>’ feature is optional. If present, it
- should contain registers ‘<samp>f0</samp>’ through ‘<samp>f31</samp>’, ‘<samp>fflags</samp>’,
- ‘<samp>frm</samp>’, and ‘<samp>fcsr</samp>’. As with the cpu feature, either the
- architectural register names, or the ABI names can be used.
- </p>
- <p>The ‘<samp>org.gnu.gdb.riscv.virtual</samp>’ feature is optional. If present,
- it should contain registers that are not backed by real registers on
- the target, but are instead virtual, where the register value is
- derived from other target state. In many ways these are like
- <small>GDB</small>s pseudo-registers, except implemented by the target.
- Currently the only register expected in this set is the one byte
- ‘<samp>priv</samp>’ register that contains the target’s privilege level in the
- least significant two bits.
- </p>
- <p>The ‘<samp>org.gnu.gdb.riscv.csr</samp>’ feature is optional. If present, it
- should contain all of the target’s standard CSRs. Standard CSRs are
- those defined in the RISC-V specification documents. There is some
- overlap between this feature and the fpu feature; the ‘<samp>fflags</samp>’,
- ‘<samp>frm</samp>’, and ‘<samp>fcsr</samp>’ registers could be in either feature. The
- expectation is that these registers will be in the fpu feature if the
- target has floating point hardware, but can be moved into the csr
- feature if the target has the floating point control registers, but no
- other floating point hardware.
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