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<a name="M68HC11_002f68HC12"></a>
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<hr>
<a name="ld-and-the-Motorola-68HC11-and-68HC12-families"></a>
<h3 class="section">4.2 <code>ld</code> and the Motorola 68HC11 and 68HC12 families</h3>

<a name="index-M68HC11-and-68HC12-support"></a>

<a name="Linker-Relaxation"></a>
<h4 class="subsection">4.2.1 Linker Relaxation</h4>

<p>For the Motorola 68HC11, <code>ld</code> can perform these global
optimizations when you specify the &lsquo;<samp>--relax</samp>&rsquo; command-line option.
</p>
<dl compact="compact">
<dd><a name="index-relaxing-on-M68HC11"></a>
</dd>
<dt><em>relaxing address modes</em></dt>
<dd><p><code>ld</code> finds all <code>jsr</code> and <code>jmp</code> instructions whose
targets are within eight bits, and turns them into eight-bit
program-counter relative <code>bsr</code> and <code>bra</code> instructions,
respectively.
</p>
<p><code>ld</code> also looks at all 16-bit extended addressing modes and
transforms them in a direct addressing mode when the address is in
page 0 (between 0 and 0x0ff).
</p>
</dd>
<dt><em>relaxing gcc instruction group</em></dt>
<dd><p>When <code>gcc</code> is called with <samp>-mrelax</samp>, it can emit group
of instructions that the linker can optimize to use a 68HC11 direct
addressing mode. These instructions consists of <code>bclr</code> or
<code>bset</code> instructions.
</p>
</dd>
</dl>

<a name="Trampoline-Generation"></a>
<h4 class="subsection">4.2.2 Trampoline Generation</h4>

<a name="index-trampoline-generation-on-M68HC11"></a>
<a name="index-trampoline-generation-on-M68HC12"></a>
<p>For 68HC11 and 68HC12, <code>ld</code> can generate trampoline code to
call a far function using a normal <code>jsr</code> instruction. The linker
will also change the relocation to some far function to use the
trampoline address instead of the function address. This is typically the
case when a pointer to a function is taken. The pointer will in fact
point to the function trampoline.
</p>


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