|
|
@@ -26,11 +26,11 @@ |
|
|
|
|
|
|
|
//Adapted to PT8211, Frank Bösing, Ben-Rheinland |
|
|
|
|
|
|
|
#if !defined(__IMXRT1052__) && !defined(__IMXRT1062__) |
|
|
|
|
|
|
|
#include <Arduino.h> |
|
|
|
#include "output_pt8211.h" |
|
|
|
#include "memcpy_audio.h" |
|
|
|
#include "utility/imxrt_hw.h" |
|
|
|
|
|
|
|
audio_block_t * AudioOutputPT8211::block_left_1st = NULL; |
|
|
|
audio_block_t * AudioOutputPT8211::block_right_1st = NULL; |
|
|
@@ -40,9 +40,9 @@ uint16_t AudioOutputPT8211::block_left_offset = 0; |
|
|
|
uint16_t AudioOutputPT8211::block_right_offset = 0; |
|
|
|
bool AudioOutputPT8211::update_responsibility = false; |
|
|
|
#if defined(AUDIO_PT8211_OVERSAMPLING) |
|
|
|
DMAMEM static uint32_t i2s_tx_buffer[AUDIO_BLOCK_SAMPLES*4]; |
|
|
|
static uint32_t i2s_tx_buffer[AUDIO_BLOCK_SAMPLES*4]; |
|
|
|
#else |
|
|
|
DMAMEM static uint32_t i2s_tx_buffer[AUDIO_BLOCK_SAMPLES]; |
|
|
|
static uint32_t i2s_tx_buffer[AUDIO_BLOCK_SAMPLES]; |
|
|
|
#endif |
|
|
|
DMAChannel AudioOutputPT8211::dma(false); |
|
|
|
|
|
|
@@ -55,9 +55,9 @@ void AudioOutputPT8211::begin(void) |
|
|
|
|
|
|
|
// TODO: should we set & clear the I2S_TCSR_SR bit here? |
|
|
|
config_i2s(); |
|
|
|
#if defined(KINETISK) |
|
|
|
CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0 |
|
|
|
|
|
|
|
#if defined(KINETISK) |
|
|
|
dma.TCD->SADDR = i2s_tx_buffer; |
|
|
|
dma.TCD->SOFF = 2; |
|
|
|
dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1); |
|
|
@@ -69,13 +69,33 @@ void AudioOutputPT8211::begin(void) |
|
|
|
dma.TCD->DLASTSGA = 0; |
|
|
|
dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; |
|
|
|
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; |
|
|
|
#endif |
|
|
|
dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX); |
|
|
|
update_responsibility = update_setup(); |
|
|
|
dma.enable(); |
|
|
|
|
|
|
|
dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX); |
|
|
|
I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE | I2S_TCSR_FR; |
|
|
|
|
|
|
|
#elif defined(__IMXRT1052__) || defined(__IMXRT1062__) |
|
|
|
|
|
|
|
CORE_PIN6_CONFIG = 3; //1:TX_DATA0 |
|
|
|
|
|
|
|
dma.TCD->SADDR = i2s_tx_buffer; |
|
|
|
dma.TCD->SOFF = 2; |
|
|
|
dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1); |
|
|
|
dma.TCD->NBYTES_MLNO = 2; |
|
|
|
dma.TCD->SLAST = -sizeof(i2s_tx_buffer); |
|
|
|
dma.TCD->DOFF = 0; |
|
|
|
dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; |
|
|
|
dma.TCD->DLASTSGA = 0; |
|
|
|
dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; |
|
|
|
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; |
|
|
|
dma.TCD->DADDR = (void *)((uint32_t)&I2S1_TDR0); |
|
|
|
dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_TX); |
|
|
|
|
|
|
|
I2S1_RCSR |= I2S_RCSR_RE; |
|
|
|
I2S1_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE; |
|
|
|
#endif |
|
|
|
update_responsibility = update_setup(); |
|
|
|
dma.attachInterrupt(isr); |
|
|
|
dma.enable(); |
|
|
|
} |
|
|
|
|
|
|
|
void AudioOutputPT8211::isr(void) |
|
|
@@ -105,7 +125,7 @@ void AudioOutputPT8211::isr(void) |
|
|
|
blockR = AudioOutputPT8211::block_right_1st; |
|
|
|
offsetL = AudioOutputPT8211::block_left_offset; |
|
|
|
offsetR = AudioOutputPT8211::block_right_offset; |
|
|
|
|
|
|
|
|
|
|
|
#if defined(AUDIO_PT8211_OVERSAMPLING) |
|
|
|
static int32_t oldL = 0; |
|
|
|
static int32_t oldR = 0; |
|
|
@@ -134,12 +154,12 @@ void AudioOutputPT8211::isr(void) |
|
|
|
for (int i=0; i< AUDIO_BLOCK_SAMPLES / 2; i++, offsetL++, offsetR++) { |
|
|
|
int32_t valL = blockL->data[offsetL]; |
|
|
|
int32_t valR = blockR->data[offsetR]; |
|
|
|
|
|
|
|
|
|
|
|
int32_t combL[3] = {0}; |
|
|
|
static int32_t combLOld[2] = {0}; |
|
|
|
int32_t combR[3] = {0}; |
|
|
|
static int32_t combROld[2] = {0}; |
|
|
|
|
|
|
|
|
|
|
|
combL[0] = valL - oldL; |
|
|
|
combR[0] = valR - oldR; |
|
|
|
combL[1] = combL[0] - combLOld[0]; |
|
|
@@ -186,7 +206,7 @@ void AudioOutputPT8211::isr(void) |
|
|
|
offsetL += AUDIO_BLOCK_SAMPLES / 2; |
|
|
|
offsetR += AUDIO_BLOCK_SAMPLES / 2; |
|
|
|
#endif //defined(AUDIO_PT8211_OVERSAMPLING) |
|
|
|
|
|
|
|
|
|
|
|
} else if (blockL) { |
|
|
|
#if defined(AUDIO_PT8211_OVERSAMPLING) |
|
|
|
#if defined(AUDIO_PT8211_INTERPOLATION_LINEAR) |
|
|
@@ -210,14 +230,14 @@ void AudioOutputPT8211::isr(void) |
|
|
|
|
|
|
|
int32_t combL[3] = {0}; |
|
|
|
static int32_t combLOld[2] = {0}; |
|
|
|
|
|
|
|
|
|
|
|
combL[0] = valL - oldL; |
|
|
|
combL[1] = combL[0] - combLOld[0]; |
|
|
|
combL[2] = combL[1] - combLOld[1]; |
|
|
|
// combL[2] now holds input val |
|
|
|
combLOld[0] = combL[0]; |
|
|
|
combLOld[1] = combL[1]; |
|
|
|
|
|
|
|
|
|
|
|
for (int j = 0; j < 4; j++) { |
|
|
|
int32_t integrateL[3]; |
|
|
|
static int32_t integrateLOld[3] = {0}; |
|
|
@@ -230,7 +250,7 @@ void AudioOutputPT8211::isr(void) |
|
|
|
integrateLOld[1] = integrateL[1]; |
|
|
|
integrateLOld[2] = integrateL[2]; |
|
|
|
} |
|
|
|
|
|
|
|
|
|
|
|
// fill right channel with zeros: |
|
|
|
*(dest+1) = 0; |
|
|
|
*(dest+3) = 0; |
|
|
@@ -242,7 +262,7 @@ void AudioOutputPT8211::isr(void) |
|
|
|
#else |
|
|
|
#error no interpolation method defined for oversampling. |
|
|
|
#endif //defined(AUDIO_PT8211_INTERPOLATION_LINEAR) |
|
|
|
#else |
|
|
|
#else |
|
|
|
memcpy_tointerleaveL(dest, blockL->data + offsetL); |
|
|
|
offsetL += (AUDIO_BLOCK_SAMPLES / 2); |
|
|
|
#endif //defined(AUDIO_PT8211_OVERSAMPLING) |
|
|
@@ -269,14 +289,14 @@ void AudioOutputPT8211::isr(void) |
|
|
|
|
|
|
|
int32_t combR[3] = {0}; |
|
|
|
static int32_t combROld[2] = {0}; |
|
|
|
|
|
|
|
|
|
|
|
combR[0] = valR - oldR; |
|
|
|
combR[1] = combR[0] - combROld[0]; |
|
|
|
combR[2] = combR[1] - combROld[1]; |
|
|
|
// combR[2] now holds input val |
|
|
|
combROld[0] = combR[0]; |
|
|
|
combROld[1] = combR[1]; |
|
|
|
|
|
|
|
|
|
|
|
for (int j = 0; j < 4; j++) { |
|
|
|
int32_t integrateR[3]; |
|
|
|
static int32_t integrateROld[3] = {0}; |
|
|
@@ -289,7 +309,7 @@ void AudioOutputPT8211::isr(void) |
|
|
|
integrateROld[1] = integrateR[1]; |
|
|
|
integrateROld[2] = integrateR[2]; |
|
|
|
} |
|
|
|
|
|
|
|
|
|
|
|
// fill left channel with zeros: |
|
|
|
*(dest+0) = 0; |
|
|
|
*(dest+2) = 0; |
|
|
@@ -309,7 +329,7 @@ void AudioOutputPT8211::isr(void) |
|
|
|
#if defined(AUDIO_PT8211_OVERSAMPLING) |
|
|
|
memset(dest,0,AUDIO_BLOCK_SAMPLES*8); |
|
|
|
#else |
|
|
|
memset(dest,0,AUDIO_BLOCK_SAMPLES*2); |
|
|
|
memset(dest,0,AUDIO_BLOCK_SAMPLES*2); |
|
|
|
#endif |
|
|
|
return; |
|
|
|
} |
|
|
@@ -378,7 +398,7 @@ void AudioOutputPT8211::update(void) |
|
|
|
} |
|
|
|
} |
|
|
|
|
|
|
|
|
|
|
|
#if defined(KINETISK) |
|
|
|
// MCLK needs to be 48e6 / 1088 * 256 = 11.29411765 MHz -> 44.117647 kHz sample rate |
|
|
|
// |
|
|
|
#if F_CPU == 96000000 || F_CPU == 48000000 || F_CPU == 24000000 |
|
|
@@ -425,9 +445,11 @@ void AudioOutputPT8211::update(void) |
|
|
|
#define MCLK_SRC 0 // system clock |
|
|
|
#endif |
|
|
|
#endif |
|
|
|
#endif |
|
|
|
|
|
|
|
void AudioOutputPT8211::config_i2s(void) |
|
|
|
{ |
|
|
|
#if defined(KINETISK) |
|
|
|
SIM_SCGC6 |= SIM_SCGC6_I2S; |
|
|
|
SIM_SCGC7 |= SIM_SCGC7_DMA; |
|
|
|
SIM_SCGC6 |= SIM_SCGC6_DMAMUX; |
|
|
@@ -457,8 +479,65 @@ void AudioOutputPT8211::config_i2s(void) |
|
|
|
// configure pin mux for 3 clock signals |
|
|
|
CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK) |
|
|
|
CORE_PIN9_CONFIG = PORT_PCR_MUX(6); // pin 9, PTC3, I2S0_TX_BCLK |
|
|
|
#if 0 |
|
|
|
CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK |
|
|
|
//CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK |
|
|
|
|
|
|
|
#elif ( defined(__IMXRT1052__) || defined(__IMXRT1062__) ) |
|
|
|
|
|
|
|
CCM_CCGR5 |= CCM_CCGR5_SAI1(CCM_CCGR_ON); |
|
|
|
//PLL: |
|
|
|
int fs = AUDIO_SAMPLE_RATE_EXACT; |
|
|
|
// PLL between 27*24 = 648MHz und 54*24=1296MHz |
|
|
|
int n1 = 4; //SAI prescaler 4 => (n1*n2) = multiple of 4 |
|
|
|
int n2 = 1 + (24000000 * 27) / (fs * 256 * n1); |
|
|
|
|
|
|
|
double C = ((double)fs * 256 * n1 * n2) / 24000000; |
|
|
|
int c0 = C; |
|
|
|
int c2 = 10000; |
|
|
|
int c1 = C * c2 - (c0 * c2); |
|
|
|
set_audioClock(c0, c1, c2); |
|
|
|
|
|
|
|
// clear SAI1_CLK register locations |
|
|
|
CCM_CSCMR1 = (CCM_CSCMR1 & ~(CCM_CSCMR1_SAI1_CLK_SEL_MASK)) |
|
|
|
| CCM_CSCMR1_SAI1_CLK_SEL(2); // &0x03 // (0,1,2): PLL3PFD0, PLL5, PLL4 |
|
|
|
CCM_CS1CDR = (CCM_CS1CDR & ~(CCM_CS1CDR_SAI1_CLK_PRED_MASK | CCM_CS1CDR_SAI1_CLK_PODF_MASK)) |
|
|
|
| CCM_CS1CDR_SAI1_CLK_PRED(n1-1) // &0x07 |
|
|
|
| CCM_CS1CDR_SAI1_CLK_PODF(n2-1); // &0x3f |
|
|
|
|
|
|
|
IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1 & ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK)) |
|
|
|
| (IOMUXC_GPR_GPR1_SAI1_MCLK_DIR | IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(0)); //Select MCLK |
|
|
|
|
|
|
|
if (I2S1_TCSR & I2S_TCSR_TE) return; |
|
|
|
|
|
|
|
// CORE_PIN23_CONFIG = 3; //1:MCLK |
|
|
|
CORE_PIN21_CONFIG = 3; //1:RX_BCLK |
|
|
|
CORE_PIN20_CONFIG = 3; //1:RX_SYNC |
|
|
|
// CORE_PIN6_CONFIG = 3; //1:TX_DATA0 |
|
|
|
// CORE_PIN7_CONFIG = 3; //1:RX_DATA0 |
|
|
|
|
|
|
|
int rsync = 0; |
|
|
|
int tsync = 1; |
|
|
|
#if defined(AUDIO_PT8211_OVERSAMPLING) |
|
|
|
int div = 0; |
|
|
|
#else |
|
|
|
int div = 3; |
|
|
|
#endif |
|
|
|
// configure transmitter |
|
|
|
I2S1_TMR = 0; |
|
|
|
I2S1_TCR1 = I2S_TCR1_RFW(0); |
|
|
|
I2S1_TCR2 = I2S_TCR2_SYNC(tsync) | I2S_TCR2_BCP | I2S_TCR2_MSEL(1) | I2S_TCR2_BCD | I2S_TCR2_DIV(div); |
|
|
|
I2S1_TCR3 = I2S_TCR3_TCE; |
|
|
|
// I2S1_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(15) | I2S_TCR4_MF | I2S_TCR4_FSE | I2S_TCR4_FSP | I2S_TCR4_FSD; //TDA1543 |
|
|
|
I2S1_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(15) | I2S_TCR4_MF /*| I2S_TCR4_FSE*/ | I2S_TCR4_FSP | I2S_TCR4_FSD; //PT8211 |
|
|
|
I2S1_TCR5 = I2S_TCR5_WNW(15) | I2S_TCR5_W0W(15) | I2S_TCR5_FBT(15); |
|
|
|
|
|
|
|
I2S1_RMR = 0; |
|
|
|
//I2S1_RCSR = (1<<25); //Reset |
|
|
|
I2S1_RCR1 = I2S_RCR1_RFW(0); |
|
|
|
I2S1_RCR2 = I2S_RCR2_SYNC(rsync) | I2S_RCR2_BCP | I2S_RCR2_MSEL(1) | I2S_TCR2_BCD | I2S_TCR2_DIV(div); |
|
|
|
I2S1_RCR3 = I2S_RCR3_RCE; |
|
|
|
// I2S1_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(15) | I2S_TCR4_MF | I2S_TCR4_FSE | I2S_TCR4_FSP | I2S_TCR4_FSD; //TDA1543 |
|
|
|
I2S1_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(15) | I2S_RCR4_MF /*| I2S_RCR4_FSE*/ | I2S_RCR4_FSP | I2S_RCR4_FSD; //PT8211 |
|
|
|
I2S1_RCR5 = I2S_RCR5_WNW(15) | I2S_RCR5_W0W(15) | I2S_RCR5_FBT(15); |
|
|
|
|
|
|
|
#endif |
|
|
|
} |
|
|
|
#endif |