Fix simultaneous input & output on I2S2

input_i2s2.cpp

 	// TODO: should we set & clear the I2S_RCSR_SR bit here?
 	AudioOutputI2S2::config_i2s();
 
-	CORE_PIN5_CONFIG = 2;  //2:RX_DATA0
-	IOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 0;
+	CORE_PIN5_CONFIG = 2;  //EMC_08, 2=SAI2_RX_DATA, page 434
+	IOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 0; // 0=GPIO_EMC_08_ALT2, page 876
 
 	dma.TCD->SADDR = (void *)((uint32_t)&I2S2_RDR0+2);
 	dma.TCD->SOFF = 0;
 	dma.TCD->BITER_ELINKNO = sizeof(i2s2_rx_buffer) / 2;
 	dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
 	dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI2_RX);
+	dma.enable();
 
-	I2S2_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE;
-	I2S2_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE;
+	I2S2_RCSR = I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR; // page 2099
+	I2S2_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; // page 2087
 
 	update_responsibility = update_setup();
-	dma.enable();
 	dma.attachInterrupt(isr);
-	//pinMode(13, OUTPUT);
 }
 
 void AudioInputI2S2::isr(void)
 	int16_t *dest_left, *dest_right;
 	audio_block_t *left, *right;
 
-	//digitalWriteFast(13, HIGH);
 	daddr = (uint32_t)(dma.TCD->DADDR);
 	dma.clearInterrupt();
 
 			} while (src < end);
 		}
 	}
-	//digitalWriteFast(13, LOW);
 }
 
 

output_i2s2.cpp

 	block_right_1st = NULL;
 
 	config_i2s();
-  	CORE_PIN2_CONFIG  = 2;  //2:TX_DATA0
+
+	// if AudioInputI2S2 set I2S_TCSR_TE (for clock sync), disable it
+	I2S2_TCSR = 0;
+	while (I2S2_TCSR & I2S_TCSR_TE) ; //wait for transmit disabled
+
+	CORE_PIN2_CONFIG  = 2;  //EMC_04, 2=SAI2_TX_DATA, page 428
 
 	dma.TCD->SADDR = i2s2_tx_buffer;
 	dma.TCD->SOFF = 2;
 	dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
 	dma.TCD->DADDR = (void *)((uint32_t)&I2S2_TDR0 + 2);
 	dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI2_TX);
-//	I2S2_RCSR |= I2S_RCSR_RE;
-	I2S2_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;
+	dma.enable();
+
+	I2S2_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE | I2S_TCSR_FR;
+
 	update_responsibility = update_setup();
 	dma.attachInterrupt(isr);
-	dma.enable();
 }
 
 void AudioOutputI2S2::isr(void)
 void AudioOutputI2S2::config_i2s(void)
 {
 	CCM_CCGR5 |= CCM_CCGR5_SAI2(CCM_CCGR_ON);
+
+	// if either transmitter or receiver is enabled, do nothing
+	if (I2S2_TCSR & I2S_TCSR_TE) return;
+	if (I2S2_RCSR & I2S_RCSR_RE) return;
 //PLL:
 	int fs = AUDIO_SAMPLE_RATE_EXACT;
 	// PLL between 27*24 = 648MHz und 54*24=1296MHz
 	CCM_CSCMR1 = (CCM_CSCMR1 & ~(CCM_CSCMR1_SAI2_CLK_SEL_MASK))
 		   | CCM_CSCMR1_SAI2_CLK_SEL(2); // &0x03 // (0,1,2): PLL3PFD0, PLL5, PLL4,
 	CCM_CS2CDR = (CCM_CS2CDR & ~(CCM_CS2CDR_SAI2_CLK_PRED_MASK | CCM_CS2CDR_SAI2_CLK_PODF_MASK))
-		   | CCM_CS2CDR_SAI2_CLK_PRED(n1-1) 
+		   | CCM_CS2CDR_SAI2_CLK_PRED(n1-1)
 		   | CCM_CS2CDR_SAI2_CLK_PODF(n2-1);
 	IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1 & ~(IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK))
 			| (IOMUXC_GPR_GPR1_SAI2_MCLK_DIR | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(0));	//Select MCLK
 
-	// if either transmitter or receiver is enabled, do nothing
-	if (I2S2_TCSR & I2S_TCSR_TE) return;
-	if (I2S2_RCSR & I2S_RCSR_RE) return;
-
-	CORE_PIN33_CONFIG = 2;  //2:MCLK
-	CORE_PIN4_CONFIG  = 2;  //2:TX_BCLK
-	CORE_PIN3_CONFIG  = 2;  //2:TX_SYNC
+	CORE_PIN33_CONFIG = 2;  //EMC_07, 2=SAI2_MCLK
+	CORE_PIN4_CONFIG  = 2;  //EMC_06, 2=SAI2_TX_BCLK
+	CORE_PIN3_CONFIG  = 2;  //EMC_05, 2=SAI2_TX_SYNC, page 429
 
 	int rsync = 1;
 	int tsync = 0;
 	//I2S2_TCSR = (1<<25); //Reset
 	I2S2_TCR1 = I2S_TCR1_RFW(1);
 	I2S2_TCR2 = I2S_TCR2_SYNC(tsync) | I2S_TCR2_BCP // sync=0; tx is async;
-		    | (I2S_TCR2_BCD | I2S_TCR2_DIV((1)) | I2S_TCR2_MSEL(1));
+		| (I2S_TCR2_BCD | I2S_TCR2_DIV((1)) | I2S_TCR2_MSEL(1));
 	I2S2_TCR3 = I2S_TCR3_TCE;
-	I2S2_TCR4 = I2S_TCR4_FRSZ((2-1)) | I2S_TCR4_SYWD((32-1)) | I2S_TCR4_MF | I2S_TCR4_FSD | I2S_TCR4_FSE | I2S_TCR4_FSP;
+	I2S2_TCR4 = I2S_TCR4_FRSZ((2-1)) | I2S_TCR4_SYWD((32-1)) | I2S_TCR4_MF
+		| I2S_TCR4_FSD | I2S_TCR4_FSE | I2S_TCR4_FSP;
 	I2S2_TCR5 = I2S_TCR5_WNW((32-1)) | I2S_TCR5_W0W((32-1)) | I2S_TCR5_FBT((32-1));
 
 	I2S2_RMR = 0;
 	//I2S2_RCSR = (1<<25); //Reset
 	I2S2_RCR1 = I2S_RCR1_RFW(1);
 	I2S2_RCR2 = I2S_RCR2_SYNC(rsync) | I2S_RCR2_BCP  // sync=0; rx is async;
-		    | (I2S_RCR2_BCD | I2S_RCR2_DIV((1)) | I2S_RCR2_MSEL(1));
+		| (I2S_RCR2_BCD | I2S_RCR2_DIV((1)) | I2S_RCR2_MSEL(1));
 	I2S2_RCR3 = I2S_RCR3_RCE;
-	I2S2_RCR4 = I2S_RCR4_FRSZ((2-1)) | I2S_RCR4_SYWD((32-1)) | I2S_RCR4_MF | I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD;
+	I2S2_RCR4 = I2S_RCR4_FRSZ((2-1)) | I2S_RCR4_SYWD((32-1)) | I2S_RCR4_MF
+		| I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD;
 	I2S2_RCR5 = I2S_RCR5_WNW((32-1)) | I2S_RCR5_W0W((32-1)) | I2S_RCR5_FBT((32-1));
 
 }