- switch to single-DMA architecture (was having to manually reset address/byte counter each time anyway, so no real benefit of using two)
- add 2-block output pipeline (mirroring Teensy 3.x)
- (sneak in timer frequency increase - may want to revert this)
- actiate DMA on timer expiration (required to use DMA from timer)
- have to manually enable DMA after setup and after each call to isr
- implement isr
	- check if dma is done (not sure this is required, but thought I saw it call once when it wasn't, and in theory you get called on errors too)
	- reset source buffer to point to other staging memory
	- re-enable dma at completion
	- otherwise similar to teensy3.x version

https://forum.pjrc.com/threads/58477-extend-Queue-object-for-Teensy-4-0-to-more-blocks

PT8211: Fix Teensy 3.x

#if define and assign of conditional var to stop compile warning

Elimitate unused var 'dc' compile warning

fix input i2s slave

dma.enable() needs to be called before setting I2S0_TCSR

fix __IMXRT1062__

Better initialization of PLL

+Add parameter "force" to allow runtime PLL-freq change

Patch for T4B2 (Pin6 -> Pin7)

T4B2: Pin6->Pin7

T4: Input TDM, Input TDM2

+ minor fixes

T4 Cache-Fix TDM

SPDIF3, initial cache-support