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@@ -2893,6 +2893,9 @@ typedef struct { |
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#define DAC0_DAT14L (*(volatile uint8_t *)0x400CC01C) // DAC Data Low Register |
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#define DAC0_DAT15L (*(volatile uint8_t *)0x400CC01E) // DAC Data Low Register |
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#define DAC0_SR (*(volatile uint8_t *)0x400CC020) // DAC Status Register |
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#define DAC_SR_DACBFWMF 0x04 // Buffer Watermark Flag |
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#define DAC_SR_DACBFRTF 0x02 // Pointer Top Position Flag |
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#define DAC_SR_DACBFRBF 0x01 // Pointer Bottom Position Flag |
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#define DAC0_C0 (*(volatile uint8_t *)0x400CC021) // DAC Control Register |
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#define DAC_C0_DACEN 0x80 // DAC Enable |
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#define DAC_C0_DACRFS 0x40 // DAC Reference Select |
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@@ -3046,6 +3049,8 @@ typedef struct { |
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#define PDB0_CH1DLY0 (*(volatile uint32_t *)0x40036040) // Channel 1 Delay 0 Register |
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#define PDB0_CH1DLY1 (*(volatile uint32_t *)0x40036044) // Channel 1 Delay 1 Register |
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#define PDB0_DACINTC0 (*(volatile uint32_t *)0x40036150) // DAC Interval Trigger n Control Register |
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#define PDB_DACINTC_EXT 0x02 // External Trigger Input Enable |
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#define PDB_DACINTC_TOE 0x01 // Interval Trigger Enable |
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#define PDB0_DACINT0 (*(volatile uint32_t *)0x40036154) // DAC Interval n Register |
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#define PDB0_DACINTC1 (*(volatile uint32_t *)0x40036158) // DAC Interval Trigger n Control register |
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#define PDB0_DACINT1 (*(volatile uint32_t *)0x4003615C) // DAC Interval n register |