| #define DAC0_DAT14L (*(volatile uint8_t *)0x400CC01C) // DAC Data Low Register | #define DAC0_DAT14L (*(volatile uint8_t *)0x400CC01C) // DAC Data Low Register | ||||
| #define DAC0_DAT15L (*(volatile uint8_t *)0x400CC01E) // DAC Data Low Register | #define DAC0_DAT15L (*(volatile uint8_t *)0x400CC01E) // DAC Data Low Register | ||||
| #define DAC0_SR (*(volatile uint8_t *)0x400CC020) // DAC Status Register | #define DAC0_SR (*(volatile uint8_t *)0x400CC020) // DAC Status Register | ||||
| #define DAC_SR_DACBFWMF 0x04 // Buffer Watermark Flag | |||||
| #define DAC_SR_DACBFRTF 0x02 // Pointer Top Position Flag | |||||
| #define DAC_SR_DACBFRBF 0x01 // Pointer Bottom Position Flag | |||||
| #define DAC0_C0 (*(volatile uint8_t *)0x400CC021) // DAC Control Register | #define DAC0_C0 (*(volatile uint8_t *)0x400CC021) // DAC Control Register | ||||
| #define DAC_C0_DACEN 0x80 // DAC Enable | #define DAC_C0_DACEN 0x80 // DAC Enable | ||||
| #define DAC_C0_DACRFS 0x40 // DAC Reference Select | #define DAC_C0_DACRFS 0x40 // DAC Reference Select | ||||
| #define PDB0_CH1DLY0 (*(volatile uint32_t *)0x40036040) // Channel 1 Delay 0 Register | #define PDB0_CH1DLY0 (*(volatile uint32_t *)0x40036040) // Channel 1 Delay 0 Register | ||||
| #define PDB0_CH1DLY1 (*(volatile uint32_t *)0x40036044) // Channel 1 Delay 1 Register | #define PDB0_CH1DLY1 (*(volatile uint32_t *)0x40036044) // Channel 1 Delay 1 Register | ||||
| #define PDB0_DACINTC0 (*(volatile uint32_t *)0x40036150) // DAC Interval Trigger n Control Register | #define PDB0_DACINTC0 (*(volatile uint32_t *)0x40036150) // DAC Interval Trigger n Control Register | ||||
| #define PDB_DACINTC_EXT 0x02 // External Trigger Input Enable | |||||
| #define PDB_DACINTC_TOE 0x01 // Interval Trigger Enable | |||||
| #define PDB0_DACINT0 (*(volatile uint32_t *)0x40036154) // DAC Interval n Register | #define PDB0_DACINT0 (*(volatile uint32_t *)0x40036154) // DAC Interval n Register | ||||
| #define PDB0_DACINTC1 (*(volatile uint32_t *)0x40036158) // DAC Interval Trigger n Control register | #define PDB0_DACINTC1 (*(volatile uint32_t *)0x40036158) // DAC Interval Trigger n Control register | ||||
| #define PDB0_DACINT1 (*(volatile uint32_t *)0x4003615C) // DAC Interval n register | #define PDB0_DACINT1 (*(volatile uint32_t *)0x4003615C) // DAC Interval n register |