Add support for more clocks: 72, 120, & 168 MHz

teensy3/core_pins.h

 	uint32_t n = usec * 40;
 #elif F_CPU == 96000000
 	uint32_t n = usec << 5;
+#elif F_CPU == 72000000
+	uint32_t n = usec * 24;
 #elif F_CPU == 48000000
 	uint32_t n = usec << 4;
 #elif F_CPU == 24000000

teensy3/mk20dx128.c

 	// wait for MCGOUT to use oscillator
 	while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2)) ;
 	// now we're in FBE mode
-	// config PLL input for 16 MHz Crystal / 4 = 4 MHz
-	MCG_C5 = MCG_C5_PRDIV0(3);
+#if F_CPU == 72000000
+	MCG_C5 = MCG_C5_PRDIV0(5);		 // config PLL input for 16 MHz Crystal / 6 = 2.667 Hz
+#else
+	MCG_C5 = MCG_C5_PRDIV0(3);		 // config PLL input for 16 MHz Crystal / 4 = 4 MHz
+#endif
 	
-#if F_CPU == 144000000	
+#if F_CPU == 168000000
+	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(18); // config PLL for 168 MHz output
+#elif F_CPU == 144000000
 	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(12); // config PLL for 144 MHz output
+#elif F_CPU == 120000000
+	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(6); // config PLL for 120 MHz output
+#elif F_CPU == 72000000
+	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(3); // config PLL for 72 MHz output
 #else
 	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0); // config PLL for 96 MHz output
 #endif
 	while (!(MCG_S & MCG_S_LOCK0)) ;
 	// now we're in PBE mode
 
-#if F_CPU == 144000000
-	// config divisors: 144 MHz core, 48 MHz bus, 24 MHz flash
-	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2) |	 SIM_CLKDIV1_OUTDIV4(5); 
+#if F_CPU == 168000000
+	// config divisors: 168 MHz core, 56 MHz bus, 28 MHz flash
+	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2) |	 SIM_CLKDIV1_OUTDIV4(5);
+#elif F_CPU == 144000000
+	// config divisors: 144 MHz core, 48 MHz bus, 28.8 MHz flash
+	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2) |	 SIM_CLKDIV1_OUTDIV4(4);
+#elif F_CPU == 120000000
+	// config divisors: 120 MHz core, 60 MHz bus, 24 MHz flash
+	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) |	 SIM_CLKDIV1_OUTDIV4(4);
 #elif F_CPU == 96000000
 	// config divisors: 96 MHz core, 48 MHz bus, 24 MHz flash
 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) |	 SIM_CLKDIV1_OUTDIV4(3);
+#elif F_CPU == 72000000
+	// config divisors: 72 MHz core, 36 MHz bus, 24 MHz flash
+	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) |	 SIM_CLKDIV1_OUTDIV4(2);
 #elif F_CPU == 48000000
 	// config divisors: 48 MHz core, 48 MHz bus, 24 MHz flash
 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(1) |	 SIM_CLKDIV1_OUTDIV4(3);
 	// config divisors: 24 MHz core, 24 MHz bus, 24 MHz flash
 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(3) |	 SIM_CLKDIV1_OUTDIV4(3);
 #else
-#error "Error, F_CPU must be  144000000, 96000000, 48000000, or 24000000"
+#error "Error, F_CPU must be 168, 144, 120, 96, 72, 48, or 24 MHz"
 #endif
 	// switch to PLL as clock source, FLL input = 16 MHz / 512
 	MCG_C1 = MCG_C1_CLKS(0) | MCG_C1_FRDIV(4);
 	while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(3)) ;
 	// now we're in PEE mode
 	// configure USB for 48 MHz clock
-#if F_CPU == 144000000
-	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(2); // USB = 144 MHz PLL / 3
+#if F_CPU == 168000000
+	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(6) | SIM_CLKDIV2_USBFRAC; // USB = 168 MHz PLL * 2 / 7
+#elif F_CPU == 144000000
+	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(2);                       // USB = 144 MHz PLL / 3
+#elif F_CPU == 120000000
+	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC; // USB = 120 MHz PLL * 2 / 5
+#elif F_CPU == 72000000
+	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC; // USB = 72 MHz PLL * 2 / 3
 #else
-	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1); // USB = 96 MHz PLL / 2
+	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1);                       // USB = 96 MHz PLL / 2
 #endif	
 	// USB uses PLL clock, trace is CPU clock, CLKOUT=OSCERCLK0
 	SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL(6);

teensy3/mk20dx128.h

 #ifndef _mk20dx128_h_
 #define _mk20dx128_h_
 
+//#ifdef F_CPU
+//#undef F_CPU
+//#endif
+//#define F_CPU 168000000
+//#define F_CPU 144000000
+//#define F_CPU 120000000
 //#define F_CPU 96000000
+//#define F_CPU 72000000
 //#define F_CPU 48000000
 //#define F_CPU 24000000
-//#define F_BUS 48000000
-//#define F_BUS 24000000
-//#define F_MEM 24000000
 
-#if (F_CPU == 144000000)
+#if (F_CPU == 168000000)
+ #define F_BUS 56000000
+ #define F_MEM 28000000
+#elif (F_CPU == 144000000)
  #define F_BUS 48000000
+ #define F_MEM 28800000
+#elif (F_CPU == 120000000)
+ #define F_BUS 60000000
  #define F_MEM 24000000
 #elif (F_CPU == 96000000)
  #define F_BUS 48000000
  #define F_MEM 24000000
+#elif (F_CPU == 72000000)
+ #define F_BUS 36000000
+ #define F_MEM 24000000
 #elif (F_CPU == 48000000)
  #define F_BUS 48000000
  #define F_MEM 24000000