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Teensy 4.1 core updated for C++20
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teensy-core-4.1/teensy3/mk20dx128.h

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  1. /* Teensyduino Core Library

  2.  * http://www.pjrc.com/teensy/

  3.  * Copyright (c) 2013 PJRC.COM, LLC.

  4.  *

  5.  * Permission is hereby granted, free of charge, to any person obtaining

  6.  * a copy of this software and associated documentation files (the

  7.  * "Software"), to deal in the Software without restriction, including

  8.  * without limitation the rights to use, copy, modify, merge, publish,

  9.  * distribute, sublicense, and/or sell copies of the Software, and to

  10.  * permit persons to whom the Software is furnished to do so, subject to

  11.  * the following conditions:

  12.  *

  13.  * 1. The above copyright notice and this permission notice shall be 

  14.  * included in all copies or substantial portions of the Software.

  15.  *

  16.  * 2. If the Software is incorporated into a build system that allows 

  17.  * selection among a list of target devices, then similar target

  18.  * devices manufactured by PJRC.COM must be included in the list of

  19.  * target devices and selectable in the same manner.

  20.  *

  21.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

  22.  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

  23.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

  24.  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS

  25.  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN

  26.  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

  27.  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

  28.  * SOFTWARE.

  29.  */

  30. 

  31. #ifndef _mk20dx128_h_

  32. #define _mk20dx128_h_

  33. 

  34. //#ifdef F_CPU

  35. //#undef F_CPU

  36. //#endif

  37. //#define F_CPU 168000000

  38. //#define F_CPU 144000000

  39. //#define F_CPU 120000000

  40. //#define F_CPU 96000000

  41. //#define F_CPU 72000000

  42. //#define F_CPU 48000000

  43. //#define F_CPU 24000000

  44. 

  45. #if (F_CPU == 168000000)

  46.  #define F_BUS 56000000

  47.  #define F_MEM 28000000

  48. #elif (F_CPU == 144000000)

  49.  #define F_BUS 48000000

  50.  #define F_MEM 28800000

  51. #elif (F_CPU == 120000000)

  52.  #define F_BUS 60000000

  53.  #define F_MEM 24000000

  54. #elif (F_CPU == 96000000)

  55.  #define F_BUS 48000000

  56.  #define F_MEM 24000000

  57. #elif (F_CPU == 72000000)

  58.  #define F_BUS 36000000

  59.  #define F_MEM 24000000

  60. #elif (F_CPU == 48000000)

  61.  #define F_BUS 48000000

  62.  #define F_MEM 24000000

  63. #elif (F_CPU == 24000000)

  64.  #define F_BUS 24000000

  65.  #define F_MEM 24000000

  66. #endif

  67. 

  68. 

  69. #ifndef NULL

  70. #define NULL ((void *)0)

  71. #endif

  72. 

  73. #include <stdint.h>

  74. #ifdef __cplusplus

  75. extern "C" {

  76. #endif

  77. 

  78. // chapter 11: Port control and interrupts (PORT)

  79. #define PORTA_PCR0		*(volatile uint32_t *)0x40049000 // Pin Control Register n

  80. #define PORT_PCR_ISF			(uint32_t)0x01000000		// Interrupt Status Flag

  81. #define PORT_PCR_IRQC(n)		(uint32_t)(((n) & 15) << 16)	// Interrupt Configuration

  82. #define PORT_PCR_IRQC_MASK		(uint32_t)0x000F0000

  83. #define PORT_PCR_LK			(uint32_t)0x00008000		// Lock Register

  84. #define PORT_PCR_MUX(n)			(uint32_t)(((n) & 7) << 8)	// Pin Mux Control

  85. #define PORT_PCR_MUX_MASK		(uint32_t)0x00000700

  86. #define PORT_PCR_DSE			(uint32_t)0x00000040		// Drive Strength Enable

  87. #define PORT_PCR_ODE			(uint32_t)0x00000020		// Open Drain Enable

  88. #define PORT_PCR_PFE			(uint32_t)0x00000010		// Passive Filter Enable

  89. #define PORT_PCR_SRE			(uint32_t)0x00000004		// Slew Rate Enable

  90. #define PORT_PCR_PE			(uint32_t)0x00000002		// Pull Enable

  91. #define PORT_PCR_PS			(uint32_t)0x00000001		// Pull Select

  92. #define PORTA_PCR1		*(volatile uint32_t *)0x40049004 // Pin Control Register n

  93. #define PORTA_PCR2		*(volatile uint32_t *)0x40049008 // Pin Control Register n

  94. #define PORTA_PCR3		*(volatile uint32_t *)0x4004900C // Pin Control Register n

  95. #define PORTA_PCR4		*(volatile uint32_t *)0x40049010 // Pin Control Register n

  96. #define PORTA_PCR5		*(volatile uint32_t *)0x40049014 // Pin Control Register n

  97. #define PORTA_PCR6		*(volatile uint32_t *)0x40049018 // Pin Control Register n

  98. #define PORTA_PCR7		*(volatile uint32_t *)0x4004901C // Pin Control Register n

  99. #define PORTA_PCR8		*(volatile uint32_t *)0x40049020 // Pin Control Register n

  100. #define PORTA_PCR9		*(volatile uint32_t *)0x40049024 // Pin Control Register n

  101. #define PORTA_PCR10		*(volatile uint32_t *)0x40049028 // Pin Control Register n

  102. #define PORTA_PCR11		*(volatile uint32_t *)0x4004902C // Pin Control Register n

  103. #define PORTA_PCR12		*(volatile uint32_t *)0x40049030 // Pin Control Register n

  104. #define PORTA_PCR13		*(volatile uint32_t *)0x40049034 // Pin Control Register n

  105. #define PORTA_PCR14		*(volatile uint32_t *)0x40049038 // Pin Control Register n

  106. #define PORTA_PCR15		*(volatile uint32_t *)0x4004903C // Pin Control Register n

  107. #define PORTA_PCR16		*(volatile uint32_t *)0x40049040 // Pin Control Register n

  108. #define PORTA_PCR17		*(volatile uint32_t *)0x40049044 // Pin Control Register n

  109. #define PORTA_PCR18		*(volatile uint32_t *)0x40049048 // Pin Control Register n

  110. #define PORTA_PCR19		*(volatile uint32_t *)0x4004904C // Pin Control Register n

  111. #define PORTA_PCR20		*(volatile uint32_t *)0x40049050 // Pin Control Register n

  112. #define PORTA_PCR21		*(volatile uint32_t *)0x40049054 // Pin Control Register n

  113. #define PORTA_PCR22		*(volatile uint32_t *)0x40049058 // Pin Control Register n

  114. #define PORTA_PCR23		*(volatile uint32_t *)0x4004905C // Pin Control Register n

  115. #define PORTA_PCR24		*(volatile uint32_t *)0x40049060 // Pin Control Register n

  116. #define PORTA_PCR25		*(volatile uint32_t *)0x40049064 // Pin Control Register n

  117. #define PORTA_PCR26		*(volatile uint32_t *)0x40049068 // Pin Control Register n

  118. #define PORTA_PCR27		*(volatile uint32_t *)0x4004906C // Pin Control Register n

  119. #define PORTA_PCR28		*(volatile uint32_t *)0x40049070 // Pin Control Register n

  120. #define PORTA_PCR29		*(volatile uint32_t *)0x40049074 // Pin Control Register n

  121. #define PORTA_PCR30		*(volatile uint32_t *)0x40049078 // Pin Control Register n

  122. #define PORTA_PCR31		*(volatile uint32_t *)0x4004907C // Pin Control Register n

  123. #define PORTA_GPCLR		*(volatile uint32_t *)0x40049080 // Global Pin Control Low Register

  124. #define PORTA_GPCHR		*(volatile uint32_t *)0x40049084 // Global Pin Control High Register

  125. #define PORTA_ISFR		*(volatile uint32_t *)0x400490A0 // Interrupt Status Flag Register

  126. #define PORTB_PCR0		*(volatile uint32_t *)0x4004A000 // Pin Control Register n

  127. #define PORTB_PCR1		*(volatile uint32_t *)0x4004A004 // Pin Control Register n

  128. #define PORTB_PCR2		*(volatile uint32_t *)0x4004A008 // Pin Control Register n

  129. #define PORTB_PCR3		*(volatile uint32_t *)0x4004A00C // Pin Control Register n

  130. #define PORTB_PCR4		*(volatile uint32_t *)0x4004A010 // Pin Control Register n

  131. #define PORTB_PCR5		*(volatile uint32_t *)0x4004A014 // Pin Control Register n

  132. #define PORTB_PCR6		*(volatile uint32_t *)0x4004A018 // Pin Control Register n

  133. #define PORTB_PCR7		*(volatile uint32_t *)0x4004A01C // Pin Control Register n

  134. #define PORTB_PCR8		*(volatile uint32_t *)0x4004A020 // Pin Control Register n

  135. #define PORTB_PCR9		*(volatile uint32_t *)0x4004A024 // Pin Control Register n

  136. #define PORTB_PCR10		*(volatile uint32_t *)0x4004A028 // Pin Control Register n

  137. #define PORTB_PCR11		*(volatile uint32_t *)0x4004A02C // Pin Control Register n

  138. #define PORTB_PCR12		*(volatile uint32_t *)0x4004A030 // Pin Control Register n

  139. #define PORTB_PCR13		*(volatile uint32_t *)0x4004A034 // Pin Control Register n

  140. #define PORTB_PCR14		*(volatile uint32_t *)0x4004A038 // Pin Control Register n

  141. #define PORTB_PCR15		*(volatile uint32_t *)0x4004A03C // Pin Control Register n

  142. #define PORTB_PCR16		*(volatile uint32_t *)0x4004A040 // Pin Control Register n

  143. #define PORTB_PCR17		*(volatile uint32_t *)0x4004A044 // Pin Control Register n

  144. #define PORTB_PCR18		*(volatile uint32_t *)0x4004A048 // Pin Control Register n

  145. #define PORTB_PCR19		*(volatile uint32_t *)0x4004A04C // Pin Control Register n

  146. #define PORTB_PCR20		*(volatile uint32_t *)0x4004A050 // Pin Control Register n

  147. #define PORTB_PCR21		*(volatile uint32_t *)0x4004A054 // Pin Control Register n

  148. #define PORTB_PCR22		*(volatile uint32_t *)0x4004A058 // Pin Control Register n

  149. #define PORTB_PCR23		*(volatile uint32_t *)0x4004A05C // Pin Control Register n

  150. #define PORTB_PCR24		*(volatile uint32_t *)0x4004A060 // Pin Control Register n

  151. #define PORTB_PCR25		*(volatile uint32_t *)0x4004A064 // Pin Control Register n

  152. #define PORTB_PCR26		*(volatile uint32_t *)0x4004A068 // Pin Control Register n

  153. #define PORTB_PCR27		*(volatile uint32_t *)0x4004A06C // Pin Control Register n

  154. #define PORTB_PCR28		*(volatile uint32_t *)0x4004A070 // Pin Control Register n

  155. #define PORTB_PCR29		*(volatile uint32_t *)0x4004A074 // Pin Control Register n

  156. #define PORTB_PCR30		*(volatile uint32_t *)0x4004A078 // Pin Control Register n

  157. #define PORTB_PCR31		*(volatile uint32_t *)0x4004A07C // Pin Control Register n

  158. #define PORTB_GPCLR		*(volatile uint32_t *)0x4004A080 // Global Pin Control Low Register

  159. #define PORTB_GPCHR		*(volatile uint32_t *)0x4004A084 // Global Pin Control High Register

  160. #define PORTB_ISFR		*(volatile uint32_t *)0x4004A0A0 // Interrupt Status Flag Register

  161. #define PORTC_PCR0		*(volatile uint32_t *)0x4004B000 // Pin Control Register n

  162. #define PORTC_PCR1		*(volatile uint32_t *)0x4004B004 // Pin Control Register n

  163. #define PORTC_PCR2		*(volatile uint32_t *)0x4004B008 // Pin Control Register n

  164. #define PORTC_PCR3		*(volatile uint32_t *)0x4004B00C // Pin Control Register n

  165. #define PORTC_PCR4		*(volatile uint32_t *)0x4004B010 // Pin Control Register n

  166. #define PORTC_PCR5		*(volatile uint32_t *)0x4004B014 // Pin Control Register n

  167. #define PORTC_PCR6		*(volatile uint32_t *)0x4004B018 // Pin Control Register n

  168. #define PORTC_PCR7		*(volatile uint32_t *)0x4004B01C // Pin Control Register n

  169. #define PORTC_PCR8		*(volatile uint32_t *)0x4004B020 // Pin Control Register n

  170. #define PORTC_PCR9		*(volatile uint32_t *)0x4004B024 // Pin Control Register n

  171. #define PORTC_PCR10		*(volatile uint32_t *)0x4004B028 // Pin Control Register n

  172. #define PORTC_PCR11		*(volatile uint32_t *)0x4004B02C // Pin Control Register n

  173. #define PORTC_PCR12		*(volatile uint32_t *)0x4004B030 // Pin Control Register n

  174. #define PORTC_PCR13		*(volatile uint32_t *)0x4004B034 // Pin Control Register n

  175. #define PORTC_PCR14		*(volatile uint32_t *)0x4004B038 // Pin Control Register n

  176. #define PORTC_PCR15		*(volatile uint32_t *)0x4004B03C // Pin Control Register n

  177. #define PORTC_PCR16		*(volatile uint32_t *)0x4004B040 // Pin Control Register n

  178. #define PORTC_PCR17		*(volatile uint32_t *)0x4004B044 // Pin Control Register n

  179. #define PORTC_PCR18		*(volatile uint32_t *)0x4004B048 // Pin Control Register n

  180. #define PORTC_PCR19		*(volatile uint32_t *)0x4004B04C // Pin Control Register n

  181. #define PORTC_PCR20		*(volatile uint32_t *)0x4004B050 // Pin Control Register n

  182. #define PORTC_PCR21		*(volatile uint32_t *)0x4004B054 // Pin Control Register n

  183. #define PORTC_PCR22		*(volatile uint32_t *)0x4004B058 // Pin Control Register n

  184. #define PORTC_PCR23		*(volatile uint32_t *)0x4004B05C // Pin Control Register n

  185. #define PORTC_PCR24		*(volatile uint32_t *)0x4004B060 // Pin Control Register n

  186. #define PORTC_PCR25		*(volatile uint32_t *)0x4004B064 // Pin Control Register n

  187. #define PORTC_PCR26		*(volatile uint32_t *)0x4004B068 // Pin Control Register n

  188. #define PORTC_PCR27		*(volatile uint32_t *)0x4004B06C // Pin Control Register n

  189. #define PORTC_PCR28		*(volatile uint32_t *)0x4004B070 // Pin Control Register n

  190. #define PORTC_PCR29		*(volatile uint32_t *)0x4004B074 // Pin Control Register n

  191. #define PORTC_PCR30		*(volatile uint32_t *)0x4004B078 // Pin Control Register n

  192. #define PORTC_PCR31		*(volatile uint32_t *)0x4004B07C // Pin Control Register n

  193. #define PORTC_GPCLR		*(volatile uint32_t *)0x4004B080 // Global Pin Control Low Register

  194. #define PORTC_GPCHR		*(volatile uint32_t *)0x4004B084 // Global Pin Control High Register

  195. #define PORTC_ISFR		*(volatile uint32_t *)0x4004B0A0 // Interrupt Status Flag Register

  196. #define PORTD_PCR0		*(volatile uint32_t *)0x4004C000 // Pin Control Register n

  197. #define PORTD_PCR1		*(volatile uint32_t *)0x4004C004 // Pin Control Register n

  198. #define PORTD_PCR2		*(volatile uint32_t *)0x4004C008 // Pin Control Register n

  199. #define PORTD_PCR3		*(volatile uint32_t *)0x4004C00C // Pin Control Register n

  200. #define PORTD_PCR4		*(volatile uint32_t *)0x4004C010 // Pin Control Register n

  201. #define PORTD_PCR5		*(volatile uint32_t *)0x4004C014 // Pin Control Register n

  202. #define PORTD_PCR6		*(volatile uint32_t *)0x4004C018 // Pin Control Register n

  203. #define PORTD_PCR7		*(volatile uint32_t *)0x4004C01C // Pin Control Register n

  204. #define PORTD_PCR8		*(volatile uint32_t *)0x4004C020 // Pin Control Register n

  205. #define PORTD_PCR9		*(volatile uint32_t *)0x4004C024 // Pin Control Register n

  206. #define PORTD_PCR10		*(volatile uint32_t *)0x4004C028 // Pin Control Register n

  207. #define PORTD_PCR11		*(volatile uint32_t *)0x4004C02C // Pin Control Register n

  208. #define PORTD_PCR12		*(volatile uint32_t *)0x4004C030 // Pin Control Register n

  209. #define PORTD_PCR13		*(volatile uint32_t *)0x4004C034 // Pin Control Register n

  210. #define PORTD_PCR14		*(volatile uint32_t *)0x4004C038 // Pin Control Register n

  211. #define PORTD_PCR15		*(volatile uint32_t *)0x4004C03C // Pin Control Register n

  212. #define PORTD_PCR16		*(volatile uint32_t *)0x4004C040 // Pin Control Register n

  213. #define PORTD_PCR17		*(volatile uint32_t *)0x4004C044 // Pin Control Register n

  214. #define PORTD_PCR18		*(volatile uint32_t *)0x4004C048 // Pin Control Register n

  215. #define PORTD_PCR19		*(volatile uint32_t *)0x4004C04C // Pin Control Register n

  216. #define PORTD_PCR20		*(volatile uint32_t *)0x4004C050 // Pin Control Register n

  217. #define PORTD_PCR21		*(volatile uint32_t *)0x4004C054 // Pin Control Register n

  218. #define PORTD_PCR22		*(volatile uint32_t *)0x4004C058 // Pin Control Register n

  219. #define PORTD_PCR23		*(volatile uint32_t *)0x4004C05C // Pin Control Register n

  220. #define PORTD_PCR24		*(volatile uint32_t *)0x4004C060 // Pin Control Register n

  221. #define PORTD_PCR25		*(volatile uint32_t *)0x4004C064 // Pin Control Register n

  222. #define PORTD_PCR26		*(volatile uint32_t *)0x4004C068 // Pin Control Register n

  223. #define PORTD_PCR27		*(volatile uint32_t *)0x4004C06C // Pin Control Register n

  224. #define PORTD_PCR28		*(volatile uint32_t *)0x4004C070 // Pin Control Register n

  225. #define PORTD_PCR29		*(volatile uint32_t *)0x4004C074 // Pin Control Register n

  226. #define PORTD_PCR30		*(volatile uint32_t *)0x4004C078 // Pin Control Register n

  227. #define PORTD_PCR31		*(volatile uint32_t *)0x4004C07C // Pin Control Register n

  228. #define PORTD_GPCLR		*(volatile uint32_t *)0x4004C080 // Global Pin Control Low Register

  229. #define PORTD_GPCHR		*(volatile uint32_t *)0x4004C084 // Global Pin Control High Register

  230. #define PORTD_ISFR		*(volatile uint32_t *)0x4004C0A0 // Interrupt Status Flag Register

  231. #define PORTE_PCR0		*(volatile uint32_t *)0x4004D000 // Pin Control Register n

  232. #define PORTE_PCR1		*(volatile uint32_t *)0x4004D004 // Pin Control Register n

  233. #define PORTE_PCR2		*(volatile uint32_t *)0x4004D008 // Pin Control Register n

  234. #define PORTE_PCR3		*(volatile uint32_t *)0x4004D00C // Pin Control Register n

  235. #define PORTE_PCR4		*(volatile uint32_t *)0x4004D010 // Pin Control Register n

  236. #define PORTE_PCR5		*(volatile uint32_t *)0x4004D014 // Pin Control Register n

  237. #define PORTE_PCR6		*(volatile uint32_t *)0x4004D018 // Pin Control Register n

  238. #define PORTE_PCR7		*(volatile uint32_t *)0x4004D01C // Pin Control Register n

  239. #define PORTE_PCR8		*(volatile uint32_t *)0x4004D020 // Pin Control Register n

  240. #define PORTE_PCR9		*(volatile uint32_t *)0x4004D024 // Pin Control Register n

  241. #define PORTE_PCR10		*(volatile uint32_t *)0x4004D028 // Pin Control Register n

  242. #define PORTE_PCR11		*(volatile uint32_t *)0x4004D02C // Pin Control Register n

  243. #define PORTE_PCR12		*(volatile uint32_t *)0x4004D030 // Pin Control Register n

  244. #define PORTE_PCR13		*(volatile uint32_t *)0x4004D034 // Pin Control Register n

  245. #define PORTE_PCR14		*(volatile uint32_t *)0x4004D038 // Pin Control Register n

  246. #define PORTE_PCR15		*(volatile uint32_t *)0x4004D03C // Pin Control Register n

  247. #define PORTE_PCR16		*(volatile uint32_t *)0x4004D040 // Pin Control Register n

  248. #define PORTE_PCR17		*(volatile uint32_t *)0x4004D044 // Pin Control Register n

  249. #define PORTE_PCR18		*(volatile uint32_t *)0x4004D048 // Pin Control Register n

  250. #define PORTE_PCR19		*(volatile uint32_t *)0x4004D04C // Pin Control Register n

  251. #define PORTE_PCR20		*(volatile uint32_t *)0x4004D050 // Pin Control Register n

  252. #define PORTE_PCR21		*(volatile uint32_t *)0x4004D054 // Pin Control Register n

  253. #define PORTE_PCR22		*(volatile uint32_t *)0x4004D058 // Pin Control Register n

  254. #define PORTE_PCR23		*(volatile uint32_t *)0x4004D05C // Pin Control Register n

  255. #define PORTE_PCR24		*(volatile uint32_t *)0x4004D060 // Pin Control Register n

  256. #define PORTE_PCR25		*(volatile uint32_t *)0x4004D064 // Pin Control Register n

  257. #define PORTE_PCR26		*(volatile uint32_t *)0x4004D068 // Pin Control Register n

  258. #define PORTE_PCR27		*(volatile uint32_t *)0x4004D06C // Pin Control Register n

  259. #define PORTE_PCR28		*(volatile uint32_t *)0x4004D070 // Pin Control Register n

  260. #define PORTE_PCR29		*(volatile uint32_t *)0x4004D074 // Pin Control Register n

  261. #define PORTE_PCR30		*(volatile uint32_t *)0x4004D078 // Pin Control Register n

  262. #define PORTE_PCR31		*(volatile uint32_t *)0x4004D07C // Pin Control Register n

  263. #define PORTE_GPCLR		*(volatile uint32_t *)0x4004D080 // Global Pin Control Low Register

  264. #define PORTE_GPCHR		*(volatile uint32_t *)0x4004D084 // Global Pin Control High Register

  265. #define PORTE_ISFR		*(volatile uint32_t *)0x4004D0A0 // Interrupt Status Flag Register

  266. 

  267. // Chapter 12: System Integration Module (SIM)

  268. #define SIM_SOPT1		*(volatile uint32_t *)0x40047000 // System Options Register 1

  269. #define SIM_SOPT1CFG		*(volatile uint32_t *)0x40047004 // SOPT1 Configuration Register

  270. #define SIM_SOPT2		*(volatile uint32_t *)0x40048004 // System Options Register 2

  271. #define SIM_SOPT2_USBSRC		(uint32_t)0x00040000		// 0=USB_CLKIN, 1=FFL/PLL 

  272. #define SIM_SOPT2_PLLFLLSEL		(uint32_t)0x00010000		// 0=FLL, 1=PLL

  273. #define SIM_SOPT2_TRACECLKSEL		(uint32_t)0x00001000		// 0=MCGOUTCLK, 1=CPU

  274. #define SIM_SOPT2_PTD7PAD		(uint32_t)0x00000800		// 0=normal, 1=double drive PTD7

  275. #define SIM_SOPT2_CLKOUTSEL(n)		(uint32_t)(((n) & 7) << 5)	// Selects the clock to output on the CLKOUT pin.

  276. #define SIM_SOPT2_RTCCLKOUTSEL		(uint32_t)0x00000010		// RTC clock out select

  277. #define SIM_SOPT4		*(volatile uint32_t *)0x4004800C // System Options Register 4

  278. #define SIM_SOPT5		*(volatile uint32_t *)0x40048010 // System Options Register 5

  279. #define SIM_SOPT7		*(volatile uint32_t *)0x40048018 // System Options Register 7

  280. #define SIM_SDID		*(const	   uint32_t *)0x40048024 // System Device Identification Register

  281. #define SIM_SCGC2		*(volatile uint32_t *)0x4004802C // System Clock Gating Control Register 2

  282. #define SIM_SCGC2_DAC0			(uint32_t)0x00001000		// DAC0 Clock Gate Control

  283. #define SIM_SCGC3		*(volatile uint32_t *)0x40048030 // System Clock Gating Control Register 3

  284. #define SIM_SCGC3_ADC1			(uint32_t)0x08000000		// ADC1 Clock Gate Control

  285. #define SIM_SCGC3_FTM2			(uint32_t)0x01000000		// FTM2 Clock Gate Control

  286. #define SIM_SCGC4		*(volatile uint32_t *)0x40048034 // System Clock Gating Control Register 4

  287. #define SIM_SCGC4_VREF			(uint32_t)0x00100000		// VREF Clock Gate Control

  288. #define SIM_SCGC4_CMP			(uint32_t)0x00080000		// Comparator Clock Gate Control

  289. #define SIM_SCGC4_USBOTG		(uint32_t)0x00040000		// USB Clock Gate Control

  290. #define SIM_SCGC4_UART2			(uint32_t)0x00001000		// UART2 Clock Gate Control

  291. #define SIM_SCGC4_UART1			(uint32_t)0x00000800		// UART1 Clock Gate Control

  292. #define SIM_SCGC4_UART0			(uint32_t)0x00000400		// UART0 Clock Gate Control

  293. #define SIM_SCGC4_I2C1			(uint32_t)0x00000080		// I2C1 Clock Gate Control

  294. #define SIM_SCGC4_I2C0			(uint32_t)0x00000040		// I2C0 Clock Gate Control

  295. #define SIM_SCGC4_CMT			(uint32_t)0x00000004		// CMT Clock Gate Control

  296. #define SIM_SCGC4_EWM			(uint32_t)0x00000002		// EWM Clock Gate Control

  297. #define SIM_SCGC5		*(volatile uint32_t *)0x40048038 // System Clock Gating Control Register 5

  298. #define SIM_SCGC5_PORTE			(uint32_t)0x00002000		// Port E Clock Gate Control

  299. #define SIM_SCGC5_PORTD			(uint32_t)0x00001000		// Port D Clock Gate Control

  300. #define SIM_SCGC5_PORTC			(uint32_t)0x00000800		// Port C Clock Gate Control

  301. #define SIM_SCGC5_PORTB			(uint32_t)0x00000400		// Port B Clock Gate Control

  302. #define SIM_SCGC5_PORTA			(uint32_t)0x00000200		// Port A Clock Gate Control

  303. #define SIM_SCGC5_TSI			(uint32_t)0x00000020		// Touch Sense Input TSI Clock Gate Control

  304. #define SIM_SCGC5_LPTIMER		(uint32_t)0x00000001		// Low Power Timer Access Control

  305. #define SIM_SCGC6		*(volatile uint32_t *)0x4004803C // System Clock Gating Control Register 6

  306. #define SIM_SCGC6_RTC			(uint32_t)0x20000000		// RTC Access

  307. #define SIM_SCGC6_ADC0			(uint32_t)0x08000000		// ADC0 Clock Gate Control

  308. #define SIM_SCGC6_FTM1			(uint32_t)0x02000000		// FTM1 Clock Gate Control

  309. #define SIM_SCGC6_FTM0			(uint32_t)0x01000000		// FTM0 Clock Gate Control

  310. #define SIM_SCGC6_PIT			(uint32_t)0x00800000		// PIT Clock Gate Control

  311. #define SIM_SCGC6_PDB			(uint32_t)0x00400000		// PDB Clock Gate Control

  312. #define SIM_SCGC6_USBDCD		(uint32_t)0x00200000		// USB DCD Clock Gate Control

  313. #define SIM_SCGC6_CRC			(uint32_t)0x00040000		// CRC Clock Gate Control

  314. #define SIM_SCGC6_I2S			(uint32_t)0x00008000		// I2S Clock Gate Control

  315. #define SIM_SCGC6_SPI1			(uint32_t)0x00002000		// SPI1 Clock Gate Control

  316. #define SIM_SCGC6_SPI0			(uint32_t)0x00001000		// SPI0 Clock Gate Control

  317. #define SIM_SCGC6_FLEXCAN0		(uint32_t)0x00000010		// FlexCAN0 Clock Gate Control

  318. #define SIM_SCGC6_DMAMUX		(uint32_t)0x00000002		// DMA Mux Clock Gate Control

  319. #define SIM_SCGC6_FTFL			(uint32_t)0x00000001		// Flash Memory Clock Gate Control

  320. #define SIM_SCGC7		*(volatile uint32_t *)0x40048040 // System Clock Gating Control Register 7

  321. #define SIM_SCGC7_DMA			(uint32_t)0x00000002		// DMA Clock Gate Control

  322. #define SIM_CLKDIV1		*(volatile uint32_t *)0x40048044 // System Clock Divider Register 1

  323. #define SIM_CLKDIV1_OUTDIV1(n)		(uint32_t)(((n) & 0x0F) << 28)	// divide value for the core/system clock

  324. #define SIM_CLKDIV1_OUTDIV2(n)		(uint32_t)(((n) & 0x0F) << 24)	// divide value for the peripheral clock

  325. #define SIM_CLKDIV1_OUTDIV4(n)		(uint32_t)(((n) & 0x0F) << 16)	// divide value for the flash clock

  326. #define SIM_CLKDIV2		*(volatile uint32_t *)0x40048048 // System Clock Divider Register 2

  327. #define SIM_CLKDIV2_USBDIV(n)		(uint32_t)(((n) & 0x07) << 1)

  328. #define SIM_CLKDIV2_USBFRAC		(uint32_t)0x01

  329. #define SIM_FCFG1		*(const	   uint32_t *)0x4004804C // Flash Configuration Register 1

  330. #define SIM_FCFG2		*(const	   uint32_t *)0x40048050 // Flash Configuration Register 2

  331. #define SIM_UIDH		*(const	   uint32_t *)0x40048054 // Unique Identification Register High

  332. #define SIM_UIDMH		*(const	   uint32_t *)0x40048058 // Unique Identification Register Mid-High

  333. #define SIM_UIDML		*(const	   uint32_t *)0x4004805C // Unique Identification Register Mid Low

  334. #define SIM_UIDL		*(const	   uint32_t *)0x40048060 // Unique Identification Register Low

  335. 

  336. // Chapter 13: Reset Control Module (RCM)

  337. #define RCM_SRS0		*(volatile uint8_t  *)0x4007F000 // System Reset Status Register 0

  338. #define RCM_SRS1		*(volatile uint8_t  *)0x4007F001 // System Reset Status Register 1

  339. #define RCM_RPFC		*(volatile uint8_t  *)0x4007F004 // Reset Pin Filter Control Register

  340. #define RCM_RPFW		*(volatile uint8_t  *)0x4007F005 // Reset Pin Filter Width Register

  341. #define RCM_MR			*(volatile uint8_t  *)0x4007F007 // Mode Register

  342. 

  343. // Chapter 14: System Mode Controller

  344. #define SMC_PMPROT		*(volatile uint8_t  *)0x4007E000 // Power Mode Protection Register

  345. #define SMC_PMPROT_AVLP			(uint8_t)0x20			// Allow very low power modes

  346. #define SMC_PMPROT_ALLS			(uint8_t)0x08			// Allow low leakage stop mode

  347. #define SMC_PMPROT_AVLLS		(uint8_t)0x02			// Allow very low leakage stop mode

  348. #define SMC_PMCTRL		*(volatile uint8_t  *)0x4007E001 // Power Mode Control Register

  349. #define SMC_PMCTRL_LPWUI		(uint8_t)0x80			// Low Power Wake Up on Interrupt

  350. #define SMC_PMCTRL_RUNM(n)		(uint8_t)(((n) & 0x03) << 5)	// Run Mode Control

  351. #define SMC_PMCTRL_STOPA		(uint8_t)0x08			// Stop Aborted

  352. #define SMC_PMCTRL_STOPM(n)		(uint8_t)((n) & 0x07)		// Stop Mode Control

  353. #define SMC_VLLSCTRL		*(volatile uint8_t  *)0x4007E002 // VLLS Control Register

  354. #define SMC_VLLSCTRL_PORPO		(uint8_t)0x20			// POR Power Option

  355. #define SMC_VLLSCTRL_VLLSM(n)		(uint8_t)((n) & 0x07)		// VLLS Mode Control

  356. #define SMC_PMSTAT		*(volatile uint8_t  *)0x4007E003 // Power Mode Status Register

  357. #define SMC_PMSTAT_RUN			(uint8_t)0x01			// Current power mode is RUN

  358. #define SMC_PMSTAT_STOP			(uint8_t)0x02			// Current power mode is STOP

  359. #define SMC_PMSTAT_VLPR			(uint8_t)0x04			// Current power mode is VLPR

  360. #define SMC_PMSTAT_VLPW			(uint8_t)0x08			// Current power mode is VLPW

  361. #define SMC_PMSTAT_VLPS			(uint8_t)0x10			// Current power mode is VLPS

  362. #define SMC_PMSTAT_LLS			(uint8_t)0x20			// Current power mode is LLS

  363. #define SMC_PMSTAT_VLLS			(uint8_t)0x40			// Current power mode is VLLS

  364. 

  365. // Chapter 15: Power Management Controller

  366. #define PMC_LVDSC1		*(volatile uint8_t  *)0x4007D000 // Low Voltage Detect Status And Control 1 register

  367. #define PMC_LVDSC1_LVDF			(uint8_t)0x80			// Low-Voltage Detect Flag

  368. #define PMC_LVDSC1_LVDACK		(uint8_t)0x40			// Low-Voltage Detect Acknowledge

  369. #define PMC_LVDSC1_LVDIE		(uint8_t)0x20			// Low-Voltage Detect Interrupt Enable

  370. #define PMC_LVDSC1_LVDRE		(uint8_t)0x10			// Low-Voltage Detect Reset Enable

  371. #define PMC_LVDSC1_LVDV(n)		(uint8_t)((n) & 0x03)		// Low-Voltage Detect Voltage Select

  372. #define PMC_LVDSC2		*(volatile uint8_t  *)0x4007D001 // Low Voltage Detect Status And Control 2 register

  373. #define PMC_LVDSC2_LVWF			(uint8_t)0x80			// Low-Voltage Warning Flag

  374. #define PMC_LVDSC2_LVWACK		(uint8_t)0x40			// Low-Voltage Warning Acknowledge

  375. #define PMC_LVDSC2_LVWIE		(uint8_t)0x20			// Low-Voltage Warning Interrupt Enable

  376. #define PMC_LVDSC2_LVWV(n)		(uint8_t)((n) & 0x03)		// Low-Voltage Warning Voltage Select

  377. #define PMC_REGSC		*(volatile uint8_t  *)0x4007D002 // Regulator Status And Control register

  378. #define PMC_REGSC_BGEN			(uint8_t)0x10			// Bandgap Enable In VLPx Operation

  379. #define PMC_REGSC_ACKISO		(uint8_t)0x08			// Acknowledge Isolation

  380. #define PMC_REGSC_REGONS		(uint8_t)0x04			// Regulator In Run Regulation Status

  381. #define PMC_REGSC_BGBE			(uint8_t)0x01			// Bandgap Buffer Enable

  382. 

  383. // Chapter 16: Low-Leakage Wakeup Unit (LLWU)

  384. #define LLWU_PE1		*(volatile uint8_t  *)0x4007C000 // LLWU Pin Enable 1 register

  385. #define LLWU_PE2		*(volatile uint8_t  *)0x4007C001 // LLWU Pin Enable 2 register

  386. #define LLWU_PE3		*(volatile uint8_t  *)0x4007C002 // LLWU Pin Enable 3 register

  387. #define LLWU_PE4		*(volatile uint8_t  *)0x4007C003 // LLWU Pin Enable 4 register

  388. #define LLWU_ME			*(volatile uint8_t  *)0x4007C004 // LLWU Module Enable register

  389. #define LLWU_F1			*(volatile uint8_t  *)0x4007C005 // LLWU Flag 1 register

  390. #define LLWU_F2			*(volatile uint8_t  *)0x4007C006 // LLWU Flag 2 register

  391. #define LLWU_F3			*(volatile uint8_t  *)0x4007C007 // LLWU Flag 3 register

  392. #define LLWU_FILT1		*(volatile uint8_t  *)0x4007C008 // LLWU Pin Filter 1 register

  393. #define LLWU_FILT2		*(volatile uint8_t  *)0x4007C009 // LLWU Pin Filter 2 register

  394. #define LLWU_RST		*(volatile uint8_t  *)0x4007C00A // LLWU Reset Enable register

  395. 

  396. // Chapter 17: Miscellaneous Control Module (MCM)

  397. #define MCM_PLASC		*(volatile uint16_t *)0xE0080008 // Crossbar Switch (AXBS) Slave Configuration

  398. #define MCM_PLAMC		*(volatile uint16_t *)0xE008000A // Crossbar Switch (AXBS) Master Configuration

  399. #define MCM_PLACR		*(volatile uint32_t *)0xE008000C // Crossbar Switch (AXBS) Control Register (MK20DX128)

  400. #define MCM_PLACR_ARG			(uint32_t)0x00000200		// Arbitration select, 0=fixed, 1=round-robin

  401. #define MCM_CR			*(volatile uint32_t *)0xE008000C // RAM arbitration control register (MK20DX256)

  402. #define MCM_CR_SRAMLWP			(uint32_t)0x40000000		// SRAM_L write protect

  403. #define MCM_CR_SRAMLAP(n)		(uint32_t)(((n) & 0x03) << 28)	// SRAM_L priority, 0=RR, 1=favor DMA, 2=CPU, 3=DMA

  404. #define MCM_CR_SRAMUWP			(uint32_t)0x04000000		// SRAM_U write protect

  405. #define MCM_CR_SRAMUAP(n)		(uint32_t)(((n) & 0x03) << 24)	// SRAM_U priority, 0=RR, 1=favor DMA, 2=CPU, 3=DMA

  406. 

  407. // Crossbar Switch (AXBS) - only programmable on MK20DX256

  408. #define AXBS_PRS0		*(volatile uint32_t *)0x40004000 // Priority Registers Slave 0

  409. #define AXBS_CRS0		*(volatile uint32_t *)0x40004010 // Control Register 0

  410. #define AXBS_PRS1		*(volatile uint32_t *)0x40004100 // Priority Registers Slave 1

  411. #define AXBS_CRS1		*(volatile uint32_t *)0x40004110 // Control Register 1

  412. #define AXBS_PRS2		*(volatile uint32_t *)0x40004200 // Priority Registers Slave 2

  413. #define AXBS_CRS2		*(volatile uint32_t *)0x40004210 // Control Register 2

  414. #define AXBS_PRS3		*(volatile uint32_t *)0x40004300 // Priority Registers Slave 3

  415. #define AXBS_CRS3		*(volatile uint32_t *)0x40004310 // Control Register 3

  416. #define AXBS_PRS4		*(volatile uint32_t *)0x40004400 // Priority Registers Slave 4

  417. #define AXBS_CRS4		*(volatile uint32_t *)0x40004410 // Control Register 4

  418. #define AXBS_PRS5		*(volatile uint32_t *)0x40004500 // Priority Registers Slave 5

  419. #define AXBS_CRS5		*(volatile uint32_t *)0x40004510 // Control Register 5

  420. #define AXBS_PRS6		*(volatile uint32_t *)0x40004600 // Priority Registers Slave 6

  421. #define AXBS_CRS6		*(volatile uint32_t *)0x40004610 // Control Register 6

  422. #define AXBS_PRS7		*(volatile uint32_t *)0x40004700 // Priority Registers Slave 7

  423. #define AXBS_CRS7		*(volatile uint32_t *)0x40004710 // Control Register 7

  424. #define AXBS_MGPCR0		*(volatile uint32_t *)0x40004800 // Master 0 General Purpose Control Register

  425. #define AXBS_MGPCR1		*(volatile uint32_t *)0x40004900 // Master 1 General Purpose Control Register

  426. #define AXBS_MGPCR2		*(volatile uint32_t *)0x40004A00 // Master 2 General Purpose Control Register

  427. #define AXBS_MGPCR3		*(volatile uint32_t *)0x40004B00 // Master 3 General Purpose Control Register

  428. #define AXBS_MGPCR4		*(volatile uint32_t *)0x40004C00 // Master 4 General Purpose Control Register

  429. #define AXBS_MGPCR5		*(volatile uint32_t *)0x40004D00 // Master 5 General Purpose Control Register

  430. #define AXBS_MGPCR6		*(volatile uint32_t *)0x40004E00 // Master 6 General Purpose Control Register

  431. #define AXBS_MGPCR7		*(volatile uint32_t *)0x40004F00 // Master 7 General Purpose Control Register

  432. #define AXBS_CRS_READONLY		(uint32_t)0x80000000

  433. #define AXBS_CRS_HALTLOWPRIORITY	(uint32_t)0x40000000

  434. #define AXBS_CRS_ARB_FIXED		(uint32_t)0x00000000

  435. #define AXBS_CRS_ARB_ROUNDROBIN		(uint32_t)0x00010000

  436. #define AXBS_CRS_PARK_FIXED		(uint32_t)0x00000000

  437. #define AXBS_CRS_PARK_PREVIOUS		(uint32_t)0x00000010

  438. #define AXBS_CRS_PARK_NONE		(uint32_t)0x00000020

  439. #define AXBS_CRS_PARK(n)		(uint32_t)(((n) & 7) << 0)

  440. 

  441. 

  442. 

  443. // Chapter 20: Direct Memory Access Multiplexer (DMAMUX)

  444. #define DMAMUX0_CHCFG0		*(volatile uint8_t  *)0x40021000 // Channel Configuration register

  445. #define DMAMUX0_CHCFG1		*(volatile uint8_t  *)0x40021001 // Channel Configuration register

  446. #define DMAMUX0_CHCFG2		*(volatile uint8_t  *)0x40021002 // Channel Configuration register

  447. #define DMAMUX0_CHCFG3		*(volatile uint8_t  *)0x40021003 // Channel Configuration register

  448. #define DMAMUX0_CHCFG4		*(volatile uint8_t  *)0x40021004 // Channel Configuration register

  449. #define DMAMUX0_CHCFG5		*(volatile uint8_t  *)0x40021005 // Channel Configuration register

  450. #define DMAMUX0_CHCFG6		*(volatile uint8_t  *)0x40021006 // Channel Configuration register

  451. #define DMAMUX0_CHCFG7		*(volatile uint8_t  *)0x40021007 // Channel Configuration register

  452. #define DMAMUX0_CHCFG8		*(volatile uint8_t  *)0x40021008 // Channel Configuration register

  453. #define DMAMUX0_CHCFG9		*(volatile uint8_t  *)0x40021009 // Channel Configuration register

  454. #define DMAMUX0_CHCFG10		*(volatile uint8_t  *)0x4002100A // Channel Configuration register

  455. #define DMAMUX0_CHCFG11		*(volatile uint8_t  *)0x4002100B // Channel Configuration register

  456. #define DMAMUX0_CHCFG12		*(volatile uint8_t  *)0x4002100C // Channel Configuration register

  457. #define DMAMUX0_CHCFG13		*(volatile uint8_t  *)0x4002100D // Channel Configuration register

  458. #define DMAMUX0_CHCFG14		*(volatile uint8_t  *)0x4002100E // Channel Configuration register

  459. #define DMAMUX0_CHCFG15		*(volatile uint8_t  *)0x4002100F // Channel Configuration register

  460. #define DMAMUX_DISABLE			0

  461. #define DMAMUX_TRIG			64

  462. #define DMAMUX_ENABLE			128

  463. #define DMAMUX_SOURCE_UART0_RX		2

  464. #define DMAMUX_SOURCE_UART0_TX		3

  465. #define DMAMUX_SOURCE_UART1_RX		4

  466. #define DMAMUX_SOURCE_UART1_TX		5

  467. #define DMAMUX_SOURCE_UART2_RX		6

  468. #define DMAMUX_SOURCE_UART2_TX		7

  469. #define DMAMUX_SOURCE_I2S0_RX		14

  470. #define DMAMUX_SOURCE_I2S0_TX		15

  471. #define DMAMUX_SOURCE_SPI0_RX		16

  472. #define DMAMUX_SOURCE_SPI0_TX		17

  473. #define DMAMUX_SOURCE_I2C0		22

  474. #define DMAMUX_SOURCE_I2C1		23

  475. #define DMAMUX_SOURCE_FTM0_CH0		24

  476. #define DMAMUX_SOURCE_FTM0_CH1		25

  477. #define DMAMUX_SOURCE_FTM0_CH2		26

  478. #define DMAMUX_SOURCE_FTM0_CH3		27

  479. #define DMAMUX_SOURCE_FTM0_CH4		28

  480. #define DMAMUX_SOURCE_FTM0_CH5		29

  481. #define DMAMUX_SOURCE_FTM0_CH6		30

  482. #define DMAMUX_SOURCE_FTM0_CH7		31

  483. #define DMAMUX_SOURCE_FTM1_CH0		32

  484. #define DMAMUX_SOURCE_FTM1_CH1		33

  485. #define DMAMUX_SOURCE_FTM2_CH0		34

  486. #define DMAMUX_SOURCE_FTM2_CH1		35

  487. #define DMAMUX_SOURCE_ADC0		40

  488. #define DMAMUX_SOURCE_ADC1		41

  489. #define DMAMUX_SOURCE_CMP0		42

  490. #define DMAMUX_SOURCE_CMP1		43

  491. #define DMAMUX_SOURCE_CMP2		44

  492. #define DMAMUX_SOURCE_DAC0		45

  493. #define DMAMUX_SOURCE_CMT		47

  494. #define DMAMUX_SOURCE_PDB		48

  495. #define DMAMUX_SOURCE_PORTA		49

  496. #define DMAMUX_SOURCE_PORTB		50

  497. #define DMAMUX_SOURCE_PORTC		51

  498. #define DMAMUX_SOURCE_PORTD		52

  499. #define DMAMUX_SOURCE_PORTE		53

  500. #define DMAMUX_SOURCE_ALWAYS0		54

  501. #define DMAMUX_SOURCE_ALWAYS1		55

  502. #define DMAMUX_SOURCE_ALWAYS2		56

  503. #define DMAMUX_SOURCE_ALWAYS3		57

  504. #define DMAMUX_SOURCE_ALWAYS4		58

  505. #define DMAMUX_SOURCE_ALWAYS5		59

  506. #define DMAMUX_SOURCE_ALWAYS6		60

  507. #define DMAMUX_SOURCE_ALWAYS7		61

  508. #define DMAMUX_SOURCE_ALWAYS8		62

  509. #define DMAMUX_SOURCE_ALWAYS9		63

  510. 

  511. // Chapter 21: Direct Memory Access Controller (eDMA)

  512. #define DMA_CR			*(volatile uint32_t *)0x40008000 // Control Register

  513. #define DMA_CR_CX			((uint32_t)(1<<17))	// Cancel Transfer

  514. #define DMA_CR_ECX			((uint32_t)(1<<16))	// Error Cancel Transfer

  515. #define DMA_CR_EMLM			((uint32_t)0x80)	// Enable Minor Loop Mapping

  516. #define DMA_CR_CLM			((uint32_t)0x40)	// Continuous Link Mode

  517. #define DMA_CR_HALT			((uint32_t)0x20)	// Halt DMA Operations

  518. #define DMA_CR_HOE			((uint32_t)0x10)	// Halt On Error

  519. #define DMA_CR_ERCA			((uint32_t)0x04)	// Enable Round Robin Channel Arbitration

  520. #define DMA_CR_EDBG			((uint32_t)0x02)	// Enable Debug

  521. #define DMA_ES			*(volatile uint32_t *)0x40008004 // Error Status Register

  522. #define DMA_ERQ			*(volatile uint32_t *)0x4000800C // Enable Request Register

  523. #define DMA_ERQ_ERQ0			((uint32_t)1<<0)	// Enable DMA Request 0

  524. #define DMA_ERQ_ERQ1			((uint32_t)1<<1)	// Enable DMA Request 1

  525. #define DMA_ERQ_ERQ2			((uint32_t)1<<2)	// Enable DMA Request 2

  526. #define DMA_ERQ_ERQ3			((uint32_t)1<<3)	// Enable DMA Request 3

  527. #define DMA_ERQ_ERQ4			((uint32_t)1<<4)	// Enable DMA Request 4

  528. #define DMA_ERQ_ERQ5			((uint32_t)1<<5)	// Enable DMA Request 5

  529. #define DMA_ERQ_ERQ6			((uint32_t)1<<6)	// Enable DMA Request 6

  530. #define DMA_ERQ_ERQ7			((uint32_t)1<<7)	// Enable DMA Request 7

  531. #define DMA_ERQ_ERQ8			((uint32_t)1<<8)	// Enable DMA Request 8

  532. #define DMA_ERQ_ERQ9			((uint32_t)1<<9)	// Enable DMA Request 9

  533. #define DMA_ERQ_ERQ10			((uint32_t)1<<10)	// Enable DMA Request 10

  534. #define DMA_ERQ_ERQ11			((uint32_t)1<<11)	// Enable DMA Request 11

  535. #define DMA_ERQ_ERQ12			((uint32_t)1<<12)	// Enable DMA Request 12

  536. #define DMA_ERQ_ERQ13			((uint32_t)1<<13)	// Enable DMA Request 13

  537. #define DMA_ERQ_ERQ14			((uint32_t)1<<14)	// Enable DMA Request 14

  538. #define DMA_ERQ_ERQ15			((uint32_t)1<<15)	// Enable DMA Request 15

  539. #define DMA_EEI			*(volatile uint32_t *)0x40008014 // Enable Error Interrupt Register

  540. #define DMA_EEI_EEI0			((uint32_t)1<<0)	// Enable Error Interrupt 0

  541. #define DMA_EEI_EEI1			((uint32_t)1<<1)	// Enable Error Interrupt 1

  542. #define DMA_EEI_EEI2			((uint32_t)1<<2)	// Enable Error Interrupt 2

  543. #define DMA_EEI_EEI3			((uint32_t)1<<3)	// Enable Error Interrupt 3

  544. #define DMA_EEI_EEI4			((uint32_t)1<<4)	// Enable Error Interrupt 4

  545. #define DMA_EEI_EEI5			((uint32_t)1<<5)	// Enable Error Interrupt 5

  546. #define DMA_EEI_EEI6			((uint32_t)1<<6)	// Enable Error Interrupt 6

  547. #define DMA_EEI_EEI7			((uint32_t)1<<7)	// Enable Error Interrupt 7

  548. #define DMA_EEI_EEI8			((uint32_t)1<<8)	// Enable Error Interrupt 8

  549. #define DMA_EEI_EEI9			((uint32_t)1<<9)	// Enable Error Interrupt 9

  550. #define DMA_EEI_EEI10			((uint32_t)1<<10)	// Enable Error Interrupt 10

  551. #define DMA_EEI_EEI11			((uint32_t)1<<11)	// Enable Error Interrupt 11

  552. #define DMA_EEI_EEI12			((uint32_t)1<<12)	// Enable Error Interrupt 12

  553. #define DMA_EEI_EEI13			((uint32_t)1<<13)	// Enable Error Interrupt 13

  554. #define DMA_EEI_EEI14			((uint32_t)1<<14)	// Enable Error Interrupt 14

  555. #define DMA_EEI_EEI15			((uint32_t)1<<15)	// Enable Error Interrupt 15

  556. #define DMA_CEEI		*(volatile uint8_t  *)0x40008018 // Clear Enable Error Interrupt Register

  557. #define DMA_CEEI_CEEI(n)		((uint8_t)(n & 15)<<0)	// Clear Enable Error Interrupt

  558. #define DMA_CEEI_CAEE			((uint8_t)1<<6)		// Clear All Enable Error Interrupts

  559. #define DMA_CEEI_NOP			((uint8_t)1<<7)		// NOP

  560. #define DMA_SEEI		*(volatile uint8_t  *)0x40008019 // Set Enable Error Interrupt Register

  561. #define DMA_SEEI_SEEI(n)		((uint8_t)(n & 15)<<0)	// Set Enable Error Interrupt

  562. #define DMA_SEEI_SAEE			((uint8_t)1<<6)		// Set All Enable Error Interrupts

  563. #define DMA_SEEI_NOP			((uint8_t)1<<7)		// NOP

  564. #define DMA_CERQ		*(volatile uint8_t  *)0x4000801A // Clear Enable Request Register

  565. #define DMA_CERQ_CERQ(n)		((uint8_t)(n & 15)<<0)	// Clear Enable Request

  566. #define DMA_CERQ_CAER			((uint8_t)1<<6)		// Clear All Enable Requests

  567. #define DMA_CERQ_NOP			((uint8_t)1<<7)		// NOP

  568. #define DMA_SERQ		*(volatile uint8_t  *)0x4000801B // Set Enable Request Register

  569. #define DMA_SERQ_SERQ(n)		((uint8_t)(n & 15)<<0)	// Set Enable Request

  570. #define DMA_SERQ_SAER			((uint8_t)1<<6)		// Set All Enable Requests

  571. #define DMA_SERQ_NOP			((uint8_t)1<<7)		// NOP

  572. #define DMA_CDNE		*(volatile uint8_t  *)0x4000801C // Clear DONE Status Bit Register

  573. #define DMA_CDNE_CDNE(n)		((uint8_t)(n & 15)<<0)	// Clear Done Bit

  574. #define DMA_CDNE_CADN			((uint8_t)1<<6)		// Clear All Done Bits

  575. #define DMA_CDNE_NOP			((uint8_t)1<<7)		// NOP

  576. #define DMA_SSRT		*(volatile uint8_t  *)0x4000801D // Set START Bit Register

  577. #define DMA_SSRT_SSRT(n)		((uint8_t)(n & 15)<<0)	// Set Start Bit

  578. #define DMA_SSRT_SAST			((uint8_t)1<<6)		// Set All Start Bits

  579. #define DMA_SSRT_NOP			((uint8_t)1<<7)		// NOP

  580. #define DMA_CERR		*(volatile uint8_t  *)0x4000801E // Clear Error Register

  581. #define DMA_CERR_CERR(n)		((uint8_t)(n & 15)<<0)	// Clear Error Indicator

  582. #define DMA_CERR_CAEI			((uint8_t)1<<6)		// Clear All Error Indicators

  583. #define DMA_CERR_NOP			((uint8_t)1<<7)		// NOP

  584. #define DMA_CINT		*(volatile uint8_t  *)0x4000801F // Clear Interrupt Request Register

  585. #define DMA_CINT_CINT(n)		((uint8_t)(n & 15)<<0)	// Clear Interrupt Request

  586. #define DMA_CINT_CAIR			((uint8_t)1<<6)		// Clear All Interrupt Requests

  587. #define DMA_CINT_NOP			((uint8_t)1<<7)		// NOP

  588. #define DMA_INT			*(volatile uint32_t *)0x40008024 // Interrupt Request Register

  589. #define DMA_INT_INT0			((uint32_t)1<<0)	// Interrupt Request 0

  590. #define DMA_INT_INT1			((uint32_t)1<<1)	// Interrupt Request 1

  591. #define DMA_INT_INT2			((uint32_t)1<<2)	// Interrupt Request 2

  592. #define DMA_INT_INT3			((uint32_t)1<<3)	// Interrupt Request 3

  593. #define DMA_INT_INT4			((uint32_t)1<<4)	// Interrupt Request 4

  594. #define DMA_INT_INT5			((uint32_t)1<<5)	// Interrupt Request 5

  595. #define DMA_INT_INT6			((uint32_t)1<<6)	// Interrupt Request 6

  596. #define DMA_INT_INT7			((uint32_t)1<<7)	// Interrupt Request 7

  597. #define DMA_INT_INT8			((uint32_t)1<<8)	// Interrupt Request 8

  598. #define DMA_INT_INT9			((uint32_t)1<<9)	// Interrupt Request 9

  599. #define DMA_INT_INT10			((uint32_t)1<<10)	// Interrupt Request 10

  600. #define DMA_INT_INT11			((uint32_t)1<<11)	// Interrupt Request 11

  601. #define DMA_INT_INT12			((uint32_t)1<<12)	// Interrupt Request 12

  602. #define DMA_INT_INT13			((uint32_t)1<<13)	// Interrupt Request 13

  603. #define DMA_INT_INT14			((uint32_t)1<<14)	// Interrupt Request 14

  604. #define DMA_INT_INT15			((uint32_t)1<<15)	// Interrupt Request 15

  605. #define DMA_ERR			*(volatile uint32_t *)0x4000802C // Error Register

  606. #define DMA_ERR_ERR0			((uint32_t)1<<0)	// Error in Channel 0

  607. #define DMA_ERR_ERR1			((uint32_t)1<<1)	// Error in Channel 1

  608. #define DMA_ERR_ERR2			((uint32_t)1<<2)	// Error in Channel 2

  609. #define DMA_ERR_ERR3			((uint32_t)1<<3)	// Error in Channel 3

  610. #define DMA_ERR_ERR4			((uint32_t)1<<4)	// Error in Channel 4

  611. #define DMA_ERR_ERR5			((uint32_t)1<<5)	// Error in Channel 5

  612. #define DMA_ERR_ERR6			((uint32_t)1<<6)	// Error in Channel 6

  613. #define DMA_ERR_ERR7			((uint32_t)1<<7)	// Error in Channel 7

  614. #define DMA_ERR_ERR8			((uint32_t)1<<8)	// Error in Channel 8

  615. #define DMA_ERR_ERR9			((uint32_t)1<<9)	// Error in Channel 9

  616. #define DMA_ERR_ERR10			((uint32_t)1<<10)	// Error in Channel 10

  617. #define DMA_ERR_ERR11			((uint32_t)1<<11)	// Error in Channel 11

  618. #define DMA_ERR_ERR12			((uint32_t)1<<12)	// Error in Channel 12

  619. #define DMA_ERR_ERR13			((uint32_t)1<<13)	// Error in Channel 13

  620. #define DMA_ERR_ERR14			((uint32_t)1<<14)	// Error in Channel 14

  621. #define DMA_ERR_ERR15			((uint32_t)1<<15)	// Error in Channel 15

  622. #define DMA_HRS			*(volatile uint32_t *)0x40008034 // Hardware Request Status Register

  623. #define DMA_HRS_HRS0			((uint32_t)1<<0)	// Hardware Request Status Channel 0

  624. #define DMA_HRS_HRS1			((uint32_t)1<<1)	// Hardware Request Status Channel 1

  625. #define DMA_HRS_HRS2			((uint32_t)1<<2)	// Hardware Request Status Channel 2

  626. #define DMA_HRS_HRS3			((uint32_t)1<<3)	// Hardware Request Status Channel 3

  627. #define DMA_HRS_HRS4			((uint32_t)1<<4)	// Hardware Request Status Channel 4

  628. #define DMA_HRS_HRS5			((uint32_t)1<<5)	// Hardware Request Status Channel 5

  629. #define DMA_HRS_HRS6			((uint32_t)1<<6)	// Hardware Request Status Channel 6

  630. #define DMA_HRS_HRS7			((uint32_t)1<<7)	// Hardware Request Status Channel 7

  631. #define DMA_HRS_HRS8			((uint32_t)1<<8)	// Hardware Request Status Channel 8

  632. #define DMA_HRS_HRS9			((uint32_t)1<<9)	// Hardware Request Status Channel 9

  633. #define DMA_HRS_HRS10			((uint32_t)1<<10)	// Hardware Request Status Channel 10

  634. #define DMA_HRS_HRS11			((uint32_t)1<<11)	// Hardware Request Status Channel 11

  635. #define DMA_HRS_HRS12			((uint32_t)1<<12)	// Hardware Request Status Channel 12

  636. #define DMA_HRS_HRS13			((uint32_t)1<<13)	// Hardware Request Status Channel 13

  637. #define DMA_HRS_HRS14			((uint32_t)1<<14)	// Hardware Request Status Channel 14

  638. #define DMA_HRS_HRS15			((uint32_t)1<<15)	// Hardware Request Status Channel 15

  639. #define DMA_DCHPRI3		*(volatile uint8_t  *)0x40008100 // Channel n Priority Register

  640. #define DMA_DCHPRI2		*(volatile uint8_t  *)0x40008101 // Channel n Priority Register

  641. #define DMA_DCHPRI1		*(volatile uint8_t  *)0x40008102 // Channel n Priority Register

  642. #define DMA_DCHPRI0		*(volatile uint8_t  *)0x40008103 // Channel n Priority Register

  643. #define DMA_DCHPRI_CHPRI(n)		((uint8_t)(n & 3)<<0)	// Channel Arbitration Priority

  644. #define DMA_DCHPRI_DPA			((uint8_t)1<<6)		// Disable PreEmpt Ability

  645. #define DMA_DCHPRI_ECP			((uint8_t)1<<7)		// Enable PreEmption

  646. 

  647. 

  648. #define DMA_TCD_ATTR_SMOD(n)		(((n) & 0x1F) << 11)

  649. #define DMA_TCD_ATTR_SSIZE(n)		(((n) & 0x7) << 8)

  650. #define DMA_TCD_ATTR_DMOD(n)		(((n) & 0x1F) << 3)

  651. #define DMA_TCD_ATTR_DSIZE(n)		(((n) & 0x7) << 0)

  652. #define DMA_TCD_ATTR_SIZE_8BIT		0

  653. #define DMA_TCD_ATTR_SIZE_16BIT		1

  654. #define DMA_TCD_ATTR_SIZE_32BIT		2

  655. #define DMA_TCD_ATTR_SIZE_16BYTE	4

  656. #define DMA_TCD_ATTR_SIZE_32BYTE	5

  657. #define DMA_TCD_CSR_BWC(n)		(((n) & 0x3) << 14)

  658. #define DMA_TCD_CSR_MAJORLINKCH(n)	(((n) & 0x3) << 8)

  659. #define DMA_TCD_CSR_DONE		0x0080

  660. #define DMA_TCD_CSR_ACTIVE		0x0040

  661. #define DMA_TCD_CSR_MAJORELINK		0x0020

  662. #define DMA_TCD_CSR_ESG			0x0010

  663. #define DMA_TCD_CSR_DREQ		0x0008

  664. #define DMA_TCD_CSR_INTHALF		0x0004

  665. #define DMA_TCD_CSR_INTMAJOR		0x0002

  666. #define DMA_TCD_CSR_START		0x0001

  667. #define DMA_TCD_CITER_MASK		    ((uint16_t)0x7FFF)	   // Loop count mask

  668. #define DMA_TCD_CITER_ELINK		    ((uint16_t)1<<15)	   // Enable channel linking on minor-loop complete

  669. #define DMA_TCD_BITER_MASK		    ((uint16_t)0x7FFF)	   // Loop count mask

  670. #define DMA_TCD_BITER_ELINK		    ((uint16_t)1<<15)	   // Enable channel linking on minor-loop complete

  671. #define DMA_TCD_NBYTES_SMLOE		    ((uint32_t)1<<31)		    // Source Minor Loop Offset Enable

  672. #define DMA_TCD_NBYTES_DMLOE		    ((uint32_t)1<<30)		    // Destination Minor Loop Offset Enable

  673. #define DMA_TCD_NBYTES_MLOFFNO_NBYTES(n)    ((uint32_t)(n))		    // NBytes transfer count when minor loop disabled

  674. #define DMA_TCD_NBYTES_MLOFFYES_NBYTES(n)   ((uint32_t)(n & 0x1F))	    // NBytes transfer count when minor loop enabled

  675. #define DMA_TCD_NBYTES_MLOFFYES_MLOFF(n)    ((uint32_t)(n & 0xFFFFF)<<10)   // Offset 

  676. 

  677. #define DMA_TCD0_SADDR		*(volatile const void * volatile *)0x40009000 // TCD Source Address

  678. #define DMA_TCD0_SOFF		*(volatile int16_t *)0x40009004	 // TCD Signed Source Address Offset

  679. #define DMA_TCD0_ATTR		*(volatile uint16_t *)0x40009006 // TCD Transfer Attributes

  680. #define DMA_TCD0_NBYTES_MLNO	*(volatile uint32_t *)0x40009008 // TCD Minor Byte Count (Minor Loop Disabled)

  681. #define DMA_TCD0_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009008 // TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)

  682. #define DMA_TCD0_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009008 // TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)

  683. #define DMA_TCD0_SLAST		*(volatile int32_t *)0x4000900C	 // TCD Last Source Address Adjustment

  684. #define DMA_TCD0_DADDR		*(volatile void * volatile *)0x40009010 // TCD Destination Address

  685. #define DMA_TCD0_DOFF		*(volatile int16_t *)0x40009014	 // TCD Signed Destination Address Offset

  686. #define DMA_TCD0_CITER_ELINKYES *(volatile uint16_t *)0x40009016 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled

  687. #define DMA_TCD0_CITER_ELINKNO	*(volatile uint16_t *)0x40009016 // ??

  688. #define DMA_TCD0_DLASTSGA	*(volatile int32_t *)0x40009018	 // TCD Last Destination Address Adjustment/Scatter Gather Address

  689. #define DMA_TCD0_CSR		*(volatile uint16_t *)0x4000901C // TCD Control and Status

  690. #define DMA_TCD0_BITER_ELINKYES *(volatile uint16_t *)0x4000901E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Enabled

  691. #define DMA_TCD0_BITER_ELINKNO	*(volatile uint16_t *)0x4000901E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled

  692. 

  693. #define DMA_TCD1_SADDR		*(volatile const void * volatile *)0x40009020 // TCD Source Address

  694. #define DMA_TCD1_SOFF		*(volatile int16_t *)0x40009024	 // TCD Signed Source Address Offset

  695. #define DMA_TCD1_ATTR		*(volatile uint16_t *)0x40009026 // TCD Transfer Attributes

  696. #define DMA_TCD1_NBYTES_MLNO	*(volatile uint32_t *)0x40009028 // TCD Minor Byte Count, Minor Loop Disabled

  697. #define DMA_TCD1_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009028 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled

  698. #define DMA_TCD1_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009028 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled

  699. #define DMA_TCD1_SLAST		*(volatile int32_t *)0x4000902C	 // TCD Last Source Address Adjustment

  700. #define DMA_TCD1_DADDR		*(volatile void * volatile *)0x40009030 // TCD Destination Address

  701. #define DMA_TCD1_DOFF		*(volatile int16_t *)0x40009034	 // TCD Signed Destination Address Offset

  702. #define DMA_TCD1_CITER_ELINKYES *(volatile uint16_t *)0x40009036 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled

  703. #define DMA_TCD1_CITER_ELINKNO	*(volatile uint16_t *)0x40009036 // ??

  704. #define DMA_TCD1_DLASTSGA	*(volatile int32_t *)0x40009038	 // TCD Last Destination Address Adjustment/Scatter Gather Address

  705. #define DMA_TCD1_CSR		*(volatile uint16_t *)0x4000903C // TCD Control and Status

  706. #define DMA_TCD1_BITER_ELINKYES *(volatile uint16_t *)0x4000903E // TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled

  707. #define DMA_TCD1_BITER_ELINKNO	*(volatile uint16_t *)0x4000903E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled

  708. 

  709. #define DMA_TCD2_SADDR		*(volatile const void * volatile *)0x40009040 // TCD Source Address

  710. #define DMA_TCD2_SOFF		*(volatile int16_t *)0x40009044	 // TCD Signed Source Address Offset

  711. #define DMA_TCD2_ATTR		*(volatile uint16_t *)0x40009046 // TCD Transfer Attributes

  712. #define DMA_TCD2_NBYTES_MLNO	*(volatile uint32_t *)0x40009048 // TCD Minor Byte Count, Minor Loop Disabled

  713. #define DMA_TCD2_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009048 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled

  714. #define DMA_TCD2_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009048 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled

  715. #define DMA_TCD2_SLAST		*(volatile int32_t *)0x4000904C	 // TCD Last Source Address Adjustment

  716. #define DMA_TCD2_DADDR		*(volatile void * volatile *)0x40009050 // TCD Destination Address

  717. #define DMA_TCD2_DOFF		*(volatile int16_t *)0x40009054	 // TCD Signed Destination Address Offset

  718. #define DMA_TCD2_CITER_ELINKYES *(volatile uint16_t *)0x40009056 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled

  719. #define DMA_TCD2_CITER_ELINKNO	*(volatile uint16_t *)0x40009056 // ??

  720. #define DMA_TCD2_DLASTSGA	*(volatile int32_t *)0x40009058	 // TCD Last Destination Address Adjustment/Scatter Gather Address

  721. #define DMA_TCD2_CSR		*(volatile uint16_t *)0x4000905C // TCD Control and Status

  722. #define DMA_TCD2_BITER_ELINKYES *(volatile uint16_t *)0x4000905E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Enabled

  723. #define DMA_TCD2_BITER_ELINKNO	*(volatile uint16_t *)0x4000905E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled

  724. 

  725. #define DMA_TCD3_SADDR		*(volatile const void * volatile *)0x40009060 // TCD Source Address

  726. #define DMA_TCD3_SOFF		*(volatile int16_t *)0x40009064	 // TCD Signed Source Address Offset

  727. #define DMA_TCD3_ATTR		*(volatile uint16_t *)0x40009066 // TCD Transfer Attributes

  728. #define DMA_TCD3_NBYTES_MLNO	*(volatile uint32_t *)0x40009068 // TCD Minor Byte Count, Minor Loop Disabled

  729. #define DMA_TCD3_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009068 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled

  730. #define DMA_TCD3_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009068 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled

  731. #define DMA_TCD3_SLAST		*(volatile int32_t *)0x4000906C	 // TCD Last Source Address Adjustment

  732. #define DMA_TCD3_DADDR		*(volatile void * volatile *)0x40009070 // TCD Destination Address

  733. #define DMA_TCD3_DOFF		*(volatile int16_t *)0x40009074	 // TCD Signed Destination Address Offset

  734. #define DMA_TCD3_CITER_ELINKYES *(volatile uint16_t *)0x40009076 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled

  735. #define DMA_TCD3_CITER_ELINKNO	*(volatile uint16_t *)0x40009076 // ??

  736. #define DMA_TCD3_DLASTSGA	*(volatile int32_t *)0x40009078	 // TCD Last Destination Address Adjustment/Scatter Gather Address

  737. #define DMA_TCD3_CSR		*(volatile uint16_t *)0x4000907C // TCD Control and Status

  738. #define DMA_TCD3_BITER_ELINKYES *(volatile uint16_t *)0x4000907E // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Enabled

  739. #define DMA_TCD3_BITER_ELINKNO	*(volatile uint16_t *)0x4000907E // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Disabled

  740. 

  741. #define DMA_TCD4_SADDR		*(volatile const void * volatile *)0x40009080 // TCD Source Addr

  742. #define DMA_TCD4_SOFF		*(volatile int16_t *)0x40009084	 // TCD Signed Source Address Offset

  743. #define DMA_TCD4_ATTR		*(volatile uint16_t *)0x40009086 // TCD Transfer Attributes

  744. #define DMA_TCD4_NBYTES_MLNO	*(volatile uint32_t *)0x40009088 // TCD Minor Byte Count

  745. #define DMA_TCD4_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009088 // TCD Signed Minor Loop Offset

  746. #define DMA_TCD4_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009088 // TCD Signed Minor Loop Offset

  747. #define DMA_TCD4_SLAST		*(volatile int32_t *)0x4000908C	 // TCD Last Source Addr Adj.

  748. #define DMA_TCD4_DADDR		*(volatile void * volatile *)0x40009090 // TCD Destination Address

  749. #define DMA_TCD4_DOFF		*(volatile int16_t *)0x40009094	 // TCD Signed Dest Address Offset

  750. #define DMA_TCD4_CITER_ELINKYES *(volatile uint16_t *)0x40009096 // TCD Current Minor Loop Link

  751. #define DMA_TCD4_CITER_ELINKNO	*(volatile uint16_t *)0x40009096 // ??

  752. #define DMA_TCD4_DLASTSGA	*(volatile int32_t *)0x40009098	 // TCD Last Destination Addr Adj

  753. #define DMA_TCD4_CSR		*(volatile uint16_t *)0x4000909C // TCD Control and Status

  754. #define DMA_TCD4_BITER_ELINKYES *(volatile uint16_t *)0x4000909E // TCD Beginning Minor Loop Link

  755. #define DMA_TCD4_BITER_ELINKNO	*(volatile uint16_t *)0x4000909E // TCD Beginning Minor Loop Link

  756. 

  757. #define DMA_TCD5_SADDR		*(volatile const void * volatile *)0x400090A0 // TCD Source Addr

  758. #define DMA_TCD5_SOFF		*(volatile int16_t *)0x400090A4	 // TCD Signed Source Address Offset

  759. #define DMA_TCD5_ATTR		*(volatile uint16_t *)0x400090A6 // TCD Transfer Attributes

  760. #define DMA_TCD5_NBYTES_MLNO	*(volatile uint32_t *)0x400090A8 // TCD Minor Byte Count

  761. #define DMA_TCD5_NBYTES_MLOFFNO *(volatile uint32_t *)0x400090A8 // TCD Signed Minor Loop Offset

  762. #define DMA_TCD5_NBYTES_MLOFFYES *(volatile uint32_t *)0x400090A8 // TCD Signed Minor Loop Offset

  763. #define DMA_TCD5_SLAST		*(volatile int32_t *)0x400090AC	 // TCD Last Source Addr Adj.

  764. #define DMA_TCD5_DADDR		*(volatile void * volatile *)0x400090B0 // TCD Destination Address

  765. #define DMA_TCD5_DOFF		*(volatile int16_t *)0x400090B4	 // TCD Signed Dest Address Offset

  766. #define DMA_TCD5_CITER_ELINKYES *(volatile uint16_t *)0x400090B6 // TCD Current Minor Loop Link

  767. #define DMA_TCD5_CITER_ELINKNO	*(volatile uint16_t *)0x400090B6 // ??

  768. #define DMA_TCD5_DLASTSGA	*(volatile int32_t *)0x400090B8	 // TCD Last Destination Addr Adj

  769. #define DMA_TCD5_CSR		*(volatile uint16_t *)0x400090BC // TCD Control and Status

  770. #define DMA_TCD5_BITER_ELINKYES *(volatile uint16_t *)0x400090BE // TCD Beginning Minor Loop Link

  771. #define DMA_TCD5_BITER_ELINKNO	*(volatile uint16_t *)0x400090BE // TCD Beginning Minor Loop Link

  772. 

  773. #define DMA_TCD6_SADDR		*(volatile const void * volatile *)0x400090C0 // TCD Source Addr

  774. #define DMA_TCD6_SOFF		*(volatile int16_t *)0x400090C4	 // TCD Signed Source Address Offset

  775. #define DMA_TCD6_ATTR		*(volatile uint16_t *)0x400090C6 // TCD Transfer Attributes

  776. #define DMA_TCD6_NBYTES_MLNO	*(volatile uint32_t *)0x400090C8 // TCD Minor Byte Count

  777. #define DMA_TCD6_NBYTES_MLOFFNO *(volatile uint32_t *)0x400090C8 // TCD Signed Minor Loop Offset

  778. #define DMA_TCD6_NBYTES_MLOFFYES *(volatile uint32_t *)0x400090C8 // TCD Signed Minor Loop Offset

  779. #define DMA_TCD6_SLAST		*(volatile int32_t *)0x400090CC	 // TCD Last Source Addr Adj.

  780. #define DMA_TCD6_DADDR		*(volatile void * volatile *)0x400090D0 // TCD Destination Address

  781. #define DMA_TCD6_DOFF		*(volatile int16_t *)0x400090D4	 // TCD Signed Dest Address Offset

  782. #define DMA_TCD6_CITER_ELINKYES *(volatile uint16_t *)0x400090D6 // TCD Current Minor Loop Link

  783. #define DMA_TCD6_CITER_ELINKNO	*(volatile uint16_t *)0x400090D6 // ??

  784. #define DMA_TCD6_DLASTSGA	*(volatile int32_t *)0x400090D8	 // TCD Last Destination Addr Adj

  785. #define DMA_TCD6_CSR		*(volatile uint16_t *)0x400090DC // TCD Control and Status

  786. #define DMA_TCD6_BITER_ELINKYES *(volatile uint16_t *)0x400090DE // TCD Beginning Minor Loop Link

  787. #define DMA_TCD6_BITER_ELINKNO	*(volatile uint16_t *)0x400090DE // TCD Beginning Minor Loop Link

  788. 

  789. #define DMA_TCD7_SADDR		*(volatile const void * volatile *)0x400090E0 // TCD Source Addr

  790. #define DMA_TCD7_SOFF		*(volatile int16_t *)0x400090E4	 // TCD Signed Source Address Offset

  791. #define DMA_TCD7_ATTR		*(volatile uint16_t *)0x400090E6 // TCD Transfer Attributes

  792. #define DMA_TCD7_NBYTES_MLNO	*(volatile uint32_t *)0x400090E8 // TCD Minor Byte Count

  793. #define DMA_TCD7_NBYTES_MLOFFNO *(volatile uint32_t *)0x400090E8 // TCD Signed Minor Loop Offset

  794. #define DMA_TCD7_NBYTES_MLOFFYES *(volatile uint32_t *)0x400090E8 // TCD Signed Minor Loop Offset

  795. #define DMA_TCD7_SLAST		*(volatile int32_t *)0x400090EC	 // TCD Last Source Addr Adj.

  796. #define DMA_TCD7_DADDR		*(volatile void * volatile *)0x400090F0 // TCD Destination Address

  797. #define DMA_TCD7_DOFF		*(volatile int16_t *)0x400090F4	 // TCD Signed Dest Address Offset

  798. #define DMA_TCD7_CITER_ELINKYES *(volatile uint16_t *)0x400090F6 // TCD Current Minor Loop Link

  799. #define DMA_TCD7_CITER_ELINKNO	*(volatile uint16_t *)0x400090F6 // ??

  800. #define DMA_TCD7_DLASTSGA	*(volatile int32_t *)0x400090F8	 // TCD Last Destination Addr Adj

  801. #define DMA_TCD7_CSR		*(volatile uint16_t *)0x400090FC // TCD Control and Status

  802. #define DMA_TCD7_BITER_ELINKYES *(volatile uint16_t *)0x400090FE // TCD Beginning Minor Loop Link

  803. #define DMA_TCD7_BITER_ELINKNO	*(volatile uint16_t *)0x400090FE // TCD Beginning Minor Loop Link

  804. 

  805. #define DMA_TCD8_SADDR		*(volatile const void * volatile *)0x40009100 // TCD Source Addr

  806. #define DMA_TCD8_SOFF		*(volatile int16_t *)0x40009104	 // TCD Signed Source Address Offset

  807. #define DMA_TCD8_ATTR		*(volatile uint16_t *)0x40009106 // TCD Transfer Attributes

  808. #define DMA_TCD8_NBYTES_MLNO	*(volatile uint32_t *)0x40009108 // TCD Minor Byte Count

  809. #define DMA_TCD8_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009108 // TCD Signed Minor Loop Offset

  810. #define DMA_TCD8_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009108 // TCD Signed Minor Loop Offset

  811. #define DMA_TCD8_SLAST		*(volatile int32_t *)0x4000910C	 // TCD Last Source Addr Adj.

  812. #define DMA_TCD8_DADDR		*(volatile void * volatile *)0x40009110 // TCD Destination Address

  813. #define DMA_TCD8_DOFF		*(volatile int16_t *)0x40009114	 // TCD Signed Dest Address Offset

  814. #define DMA_TCD8_CITER_ELINKYES *(volatile uint16_t *)0x40009116 // TCD Current Minor Loop Link

  815. #define DMA_TCD8_CITER_ELINKNO	*(volatile uint16_t *)0x40009116 // ??

  816. #define DMA_TCD8_DLASTSGA	*(volatile int32_t *)0x40009118	 // TCD Last Destination Addr Adj

  817. #define DMA_TCD8_CSR		*(volatile uint16_t *)0x4000911C // TCD Control and Status

  818. #define DMA_TCD8_BITER_ELINKYES *(volatile uint16_t *)0x4000911E // TCD Beginning Minor Loop Link

  819. #define DMA_TCD8_BITER_ELINKNO	*(volatile uint16_t *)0x4000911E // TCD Beginning Minor Loop Link

  820. 

  821. #define DMA_TCD9_SADDR		*(volatile const void * volatile *)0x40009120 // TCD Source Addr

  822. #define DMA_TCD9_SOFF		*(volatile int16_t *)0x40009124	 // TCD Signed Source Address Offset

  823. #define DMA_TCD9_ATTR		*(volatile uint16_t *)0x40009126 // TCD Transfer Attributes

  824. #define DMA_TCD9_NBYTES_MLNO	*(volatile uint32_t *)0x40009128 // TCD Minor Byte Count

  825. #define DMA_TCD9_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009128 // TCD Signed Minor Loop Offset

  826. #define DMA_TCD9_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009128 // TCD Signed Minor Loop Offset

  827. #define DMA_TCD9_SLAST		*(volatile int32_t *)0x4000912C	 // TCD Last Source Addr Adj.

  828. #define DMA_TCD9_DADDR		*(volatile void * volatile *)0x40009130 // TCD Destination Address

  829. #define DMA_TCD9_DOFF		*(volatile int16_t *)0x40009134	 // TCD Signed Dest Address Offset

  830. #define DMA_TCD9_CITER_ELINKYES *(volatile uint16_t *)0x40009136 // TCD Current Minor Loop Link

  831. #define DMA_TCD9_CITER_ELINKNO	*(volatile uint16_t *)0x40009136 // ??

  832. #define DMA_TCD9_DLASTSGA	*(volatile int32_t *)0x40009138	 // TCD Last Destination Addr Adj

  833. #define DMA_TCD9_CSR		*(volatile uint16_t *)0x4000913C // TCD Control and Status

  834. #define DMA_TCD9_BITER_ELINKYES *(volatile uint16_t *)0x4000913E // TCD Beginning Minor Loop Link

  835. #define DMA_TCD9_BITER_ELINKNO	*(volatile uint16_t *)0x4000913E // TCD Beginning Minor Loop Link

  836. 

  837. #define DMA_TCD10_SADDR		*(volatile const void * volatile *)0x40009140 // TCD Source Addr

  838. #define DMA_TCD10_SOFF		*(volatile int16_t *)0x40009144	 // TCD Signed Source Address Offset

  839. #define DMA_TCD10_ATTR		*(volatile uint16_t *)0x40009146 // TCD Transfer Attributes

  840. #define DMA_TCD10_NBYTES_MLNO	*(volatile uint32_t *)0x40009148 // TCD Minor Byte Count

  841. #define DMA_TCD10_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009148 // TCD Signed Minor Loop Offset

  842. #define DMA_TCD10_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009148 // TCD Signed Minor Loop Offset

  843. #define DMA_TCD10_SLAST		*(volatile int32_t *)0x4000914C	 // TCD Last Source Addr Adj.

  844. #define DMA_TCD10_DADDR		*(volatile void * volatile *)0x40009150 // TCD Destination Address

  845. #define DMA_TCD10_DOFF		*(volatile int16_t *)0x40009154	 // TCD Signed Dest Address Offset

  846. #define DMA_TCD10_CITER_ELINKYES *(volatile uint16_t *)0x40009156 // TCD Current Minor Loop Link

  847. #define DMA_TCD10_CITER_ELINKNO	*(volatile uint16_t *)0x40009156 // ??

  848. #define DMA_TCD10_DLASTSGA	*(volatile int32_t *)0x40009158	 // TCD Last Destination Addr Adj

  849. #define DMA_TCD10_CSR		*(volatile uint16_t *)0x4000915C // TCD Control and Status

  850. #define DMA_TCD10_BITER_ELINKYES *(volatile uint16_t *)0x4000915E // TCD Beginning Minor Loop Link

  851. #define DMA_TCD10_BITER_ELINKNO	*(volatile uint16_t *)0x4000915E // TCD Beginning Minor Loop Link

  852. 

  853. #define DMA_TCD11_SADDR		*(volatile const void * volatile *)0x40009160 // TCD Source Addr

  854. #define DMA_TCD11_SOFF		*(volatile int16_t *)0x40009164	 // TCD Signed Source Address Offset

  855. #define DMA_TCD11_ATTR		*(volatile uint16_t *)0x40009166 // TCD Transfer Attributes

  856. #define DMA_TCD11_NBYTES_MLNO	*(volatile uint32_t *)0x40009168 // TCD Minor Byte Count

  857. #define DMA_TCD11_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009168 // TCD Signed Minor Loop Offset

  858. #define DMA_TCD11_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009168 // TCD Signed Minor Loop Offset

  859. #define DMA_TCD11_SLAST		*(volatile int32_t *)0x4000916C	 // TCD Last Source Addr Adj.

  860. #define DMA_TCD11_DADDR		*(volatile void * volatile *)0x40009170 // TCD Destination Address

  861. #define DMA_TCD11_DOFF		*(volatile int16_t *)0x40009174	 // TCD Signed Dest Address Offset

  862. #define DMA_TCD11_CITER_ELINKYES *(volatile uint16_t *)0x40009176 // TCD Current Minor Loop Link

  863. #define DMA_TCD11_CITER_ELINKNO	*(volatile uint16_t *)0x40009176 // ??

  864. #define DMA_TCD11_DLASTSGA	*(volatile int32_t *)0x40009178	 // TCD Last Destination Addr Adj

  865. #define DMA_TCD11_CSR		*(volatile uint16_t *)0x4000917C // TCD Control and Status

  866. #define DMA_TCD11_BITER_ELINKYES *(volatile uint16_t *)0x4000917E // TCD Beginning Minor Loop Link

  867. #define DMA_TCD11_BITER_ELINKNO	*(volatile uint16_t *)0x4000917E // TCD Beginning Minor Loop Link

  868. 

  869. #define DMA_TCD12_SADDR		*(volatile const void * volatile *)0x40009180 // TCD Source Addr

  870. #define DMA_TCD12_SOFF		*(volatile int16_t *)0x40009184	 // TCD Signed Source Address Offset

  871. #define DMA_TCD12_ATTR		*(volatile uint16_t *)0x40009186 // TCD Transfer Attributes

  872. #define DMA_TCD12_NBYTES_MLNO	*(volatile uint32_t *)0x40009188 // TCD Minor Byte Count

  873. #define DMA_TCD12_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009188 // TCD Signed Minor Loop Offset

  874. #define DMA_TCD12_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009188 // TCD Signed Minor Loop Offset

  875. #define DMA_TCD12_SLAST		*(volatile int32_t *)0x4000918C	 // TCD Last Source Addr Adj.

  876. #define DMA_TCD12_DADDR		*(volatile void * volatile *)0x40009190 // TCD Destination Address

  877. #define DMA_TCD12_DOFF		*(volatile int16_t *)0x40009194	 // TCD Signed Dest Address Offset

  878. #define DMA_TCD12_CITER_ELINKYES *(volatile uint16_t *)0x40009196 // TCD Current Minor Loop Link

  879. #define DMA_TCD12_CITER_ELINKNO	*(volatile uint16_t *)0x40009196 // ??

  880. #define DMA_TCD12_DLASTSGA	*(volatile int32_t *)0x40009198	 // TCD Last Destination Addr Adj

  881. #define DMA_TCD12_CSR		*(volatile uint16_t *)0x4000919C // TCD Control and Status

  882. #define DMA_TCD12_BITER_ELINKYES *(volatile uint16_t *)0x4000919E // TCD Beginning Minor Loop Link

  883. #define DMA_TCD12_BITER_ELINKNO	*(volatile uint16_t *)0x4000919E // TCD Beginning Minor Loop Link

  884. 

  885. #define DMA_TCD13_SADDR		*(volatile const void * volatile *)0x400091A0 // TCD Source Addr

  886. #define DMA_TCD13_SOFF		*(volatile int16_t *)0x400091A4	 // TCD Signed Source Address Offset

  887. #define DMA_TCD13_ATTR		*(volatile uint16_t *)0x400091A6 // TCD Transfer Attributes

  888. #define DMA_TCD13_NBYTES_MLNO	*(volatile uint32_t *)0x400091A8 // TCD Minor Byte Count

  889. #define DMA_TCD13_NBYTES_MLOFFNO *(volatile uint32_t *)0x400091A8 // TCD Signed Minor Loop Offset

  890. #define DMA_TCD13_NBYTES_MLOFFYES *(volatile uint32_t *)0x400091A8 // TCD Signed Minor Loop Offset

  891. #define DMA_TCD13_SLAST		*(volatile int32_t *)0x400091AC	 // TCD Last Source Addr Adj.

  892. #define DMA_TCD13_DADDR		*(volatile void * volatile *)0x400091B0 // TCD Destination Address

  893. #define DMA_TCD13_DOFF		*(volatile int16_t *)0x400091B4	 // TCD Signed Dest Address Offset

  894. #define DMA_TCD13_CITER_ELINKYES *(volatile uint16_t *)0x400091B6 // TCD Current Minor Loop Link

  895. #define DMA_TCD13_CITER_ELINKNO	*(volatile uint16_t *)0x400091B6 // ??

  896. #define DMA_TCD13_DLASTSGA	*(volatile int32_t *)0x400091B8	 // TCD Last Destination Addr Adj

  897. #define DMA_TCD13_CSR		*(volatile uint16_t *)0x400091BC // TCD Control and Status

  898. #define DMA_TCD13_BITER_ELINKYES *(volatile uint16_t *)0x400091BE // TCD Beginning Minor Loop Link

  899. #define DMA_TCD13_BITER_ELINKNO	*(volatile uint16_t *)0x400091BE // TCD Beginning Minor Loop Link

  900. 

  901. #define DMA_TCD14_SADDR		*(volatile const void * volatile *)0x400091C0 // TCD Source Addr

  902. #define DMA_TCD14_SOFF		*(volatile int16_t *)0x400091C4	 // TCD Signed Source Address Offset

  903. #define DMA_TCD14_ATTR		*(volatile uint16_t *)0x400091C6 // TCD Transfer Attributes

  904. #define DMA_TCD14_NBYTES_MLNO	*(volatile uint32_t *)0x400091C8 // TCD Minor Byte Count

  905. #define DMA_TCD14_NBYTES_MLOFFNO *(volatile uint32_t *)0x400091C8 // TCD Signed Minor Loop Offset

  906. #define DMA_TCD14_NBYTES_MLOFFYES *(volatile uint32_t *)0x400091C8 // TCD Signed Minor Loop Offset

  907. #define DMA_TCD14_SLAST		*(volatile int32_t *)0x400091CC	 // TCD Last Source Addr Adj.

  908. #define DMA_TCD14_DADDR		*(volatile void * volatile *)0x400091D0 // TCD Destination Address

  909. #define DMA_TCD14_DOFF		*(volatile int16_t *)0x400091D4	 // TCD Signed Dest Address Offset

  910. #define DMA_TCD14_CITER_ELINKYES *(volatile uint16_t *)0x400091D6 // TCD Current Minor Loop Link

  911. #define DMA_TCD14_CITER_ELINKNO	*(volatile uint16_t *)0x400091D6 // ??

  912. #define DMA_TCD14_DLASTSGA	*(volatile int32_t *)0x400091D8	 // TCD Last Destination Addr Adj

  913. #define DMA_TCD14_CSR		*(volatile uint16_t *)0x400091DC // TCD Control and Status

  914. #define DMA_TCD14_BITER_ELINKYES *(volatile uint16_t *)0x400091DE // TCD Beginning Minor Loop Link

  915. #define DMA_TCD14_BITER_ELINKNO	*(volatile uint16_t *)0x400091DE // TCD Beginning Minor Loop Link

  916. 

  917. #define DMA_TCD15_SADDR		*(volatile const void * volatile *)0x400091E0 // TCD Source Addr

  918. #define DMA_TCD15_SOFF		*(volatile int16_t *)0x400091E4	 // TCD Signed Source Address Offset

  919. #define DMA_TCD15_ATTR		*(volatile uint16_t *)0x400091E6 // TCD Transfer Attributes

  920. #define DMA_TCD15_NBYTES_MLNO	*(volatile uint32_t *)0x400091E8 // TCD Minor Byte Count

  921. #define DMA_TCD15_NBYTES_MLOFFNO *(volatile uint32_t *)0x400091E8 // TCD Signed Minor Loop Offset

  922. #define DMA_TCD15_NBYTES_MLOFFYES *(volatile uint32_t *)0x400091E8 // TCD Signed Minor Loop Offset

  923. #define DMA_TCD15_SLAST		*(volatile int32_t *)0x400091EC	 // TCD Last Source Addr Adj.

  924. #define DMA_TCD15_DADDR		*(volatile void * volatile *)0x400091F0 // TCD Destination Address

  925. #define DMA_TCD15_DOFF		*(volatile int16_t *)0x400091F4	 // TCD Signed Dest Address Offset

  926. #define DMA_TCD15_CITER_ELINKYES *(volatile uint16_t *)0x400091F6 // TCD Current Minor Loop Link

  927. #define DMA_TCD15_CITER_ELINKNO	*(volatile uint16_t *)0x400091F6 // ??

  928. #define DMA_TCD15_DLASTSGA	*(volatile int32_t *)0x400091F8	 // TCD Last Destination Addr Adj

  929. #define DMA_TCD15_CSR		*(volatile uint16_t *)0x400091FC // TCD Control and Status

  930. #define DMA_TCD15_BITER_ELINKYES *(volatile uint16_t *)0x400091FE // TCD Beginning Minor Loop Link

  931. #define DMA_TCD15_BITER_ELINKNO	*(volatile uint16_t *)0x400091FE // TCD Beginning Minor Loop Link

  932. 

  933. 

  934. // Chapter 22: External Watchdog Monitor (EWM)

  935. #define EWM_CTRL		*(volatile uint8_t  *)0x40061000 // Control Register

  936. #define EWM_SERV		*(volatile uint8_t  *)0x40061001 // Service Register

  937. #define EWM_CMPL		*(volatile uint8_t  *)0x40061002 // Compare Low Register

  938. #define EWM_CMPH		*(volatile uint8_t  *)0x40061003 // Compare High Register

  939. 

  940. // Chapter 23: Watchdog Timer (WDOG)

  941. #define WDOG_STCTRLH		*(volatile uint16_t *)0x40052000 // Watchdog Status and Control Register High

  942. #define WDOG_STCTRLH_DISTESTWDOG	(uint16_t)0x4000		// Allows the WDOG's functional test mode to be disabled permanently.

  943. #define WDOG_STCTRLH_BYTESEL(n)		(uint16_t)(((n) & 3) << 12)	// selects the byte to be tested when the watchdog is in the byte test mode.

  944. #define WDOG_STCTRLH_TESTSEL		(uint16_t)0x0800

  945. #define WDOG_STCTRLH_TESTWDOG		(uint16_t)0x0400

  946. #define WDOG_STCTRLH_WAITEN		(uint16_t)0x0080

  947. #define WDOG_STCTRLH_STOPEN		(uint16_t)0x0040

  948. #define WDOG_STCTRLH_DBGEN		(uint16_t)0x0020

  949. #define WDOG_STCTRLH_ALLOWUPDATE	(uint16_t)0x0010

  950. #define WDOG_STCTRLH_WINEN		(uint16_t)0x0008

  951. #define WDOG_STCTRLH_IRQRSTEN		(uint16_t)0x0004

  952. #define WDOG_STCTRLH_CLKSRC		(uint16_t)0x0002

  953. #define WDOG_STCTRLH_WDOGEN		(uint16_t)0x0001

  954. #define WDOG_STCTRLL		*(volatile uint16_t *)0x40052002 // Watchdog Status and Control Register Low

  955. #define WDOG_TOVALH		*(volatile uint16_t *)0x40052004 // Watchdog Time-out Value Register High

  956. #define WDOG_TOVALL		*(volatile uint16_t *)0x40052006 // Watchdog Time-out Value Register Low

  957. #define WDOG_WINH		*(volatile uint16_t *)0x40052008 // Watchdog Window Register High

  958. #define WDOG_WINL		*(volatile uint16_t *)0x4005200A // Watchdog Window Register Low

  959. #define WDOG_REFRESH		*(volatile uint16_t *)0x4005200C // Watchdog Refresh register

  960. #define WDOG_UNLOCK		*(volatile uint16_t *)0x4005200E // Watchdog Unlock register

  961. #define WDOG_UNLOCK_SEQ1		(uint16_t)0xC520

  962. #define WDOG_UNLOCK_SEQ2		(uint16_t)0xD928

  963. #define WDOG_TMROUTH		*(volatile uint16_t *)0x40052010 // Watchdog Timer Output Register High

  964. #define WDOG_TMROUTL		*(volatile uint16_t *)0x40052012 // Watchdog Timer Output Register Low

  965. #define WDOG_RSTCNT		*(volatile uint16_t *)0x40052014 // Watchdog Reset Count register

  966. #define WDOG_PRESC		*(volatile uint16_t *)0x40052016 // Watchdog Prescaler register

  967. 

  968. // Chapter 24: Multipurpose Clock Generator (MCG)

  969. #define MCG_C1			*(volatile uint8_t  *)0x40064000 // MCG Control 1 Register

  970. #define MCG_C1_IREFSTEN			(uint8_t)0x01			// Internal Reference Stop Enable, Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode.

  971. #define MCG_C1_IRCLKEN			(uint8_t)0x02			// Internal Reference Clock Enable, Enables the internal reference clock for use as MCGIRCLK.

  972. #define MCG_C1_IREFS			(uint8_t)0x04			// Internal Reference Select, Selects the reference clock source for the FLL.

  973. #define MCG_C1_FRDIV(n)			(uint8_t)(((n) & 0x07) << 3)	// FLL External Reference Divider, Selects the amount to divide down the external reference clock for the FLL

  974. #define MCG_C1_CLKS(n)			(uint8_t)(((n) & 0x03) << 6)	// Clock Source Select, Selects the clock source for MCGOUTCLK

  975. #define MCG_C2			*(volatile uint8_t  *)0x40064001 // MCG Control 2 Register

  976. #define MCG_C2_IRCS			(uint8_t)0x01			// Internal Reference Clock Select, Selects between the fast or slow internal reference clock source.

  977. #define MCG_C2_LP			(uint8_t)0x02			// Low Power Select, Controls whether the FLL or PLL is disabled in BLPI and BLPE modes.

  978. #define MCG_C2_EREFS			(uint8_t)0x04			// External Reference Select, Selects the source for the external reference clock. 

  979. #define MCG_C2_HGO0			(uint8_t)0x08			// High Gain Oscillator Select, Controls the crystal oscillator mode of operation

  980. #define MCG_C2_RANGE0(n)		(uint8_t)(((n) & 0x03) << 4)	// Frequency Range Select, Selects the frequency range for the crystal oscillator

  981. #define MCG_C2_LOCRE0			(uint8_t)0x80			// Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0 

  982. #define MCG_C3			*(volatile uint8_t  *)0x40064002 // MCG Control 3 Register

  983. #define MCG_C3_SCTRIM(n)		(uint8_t)(n)			// Slow Internal Reference Clock Trim Setting

  984. #define MCG_C4			*(volatile uint8_t  *)0x40064003 // MCG Control 4 Register

  985. #define MCG_C4_SCFTRIM			(uint8_t)0x01			// Slow Internal Reference Clock Fine Trim

  986. #define MCG_C4_FCTRIM(n)		(uint8_t)(((n) & 0x0F) << 1)	// Fast Internal Reference Clock Trim Setting

  987. #define MCG_C4_DRST_DRS(n)		(uint8_t)(((n) & 0x03) << 5)	// DCO Range Select

  988. #define MCG_C4_DMX32			(uint8_t)0x80			// DCO Maximum Frequency with 32.768 kHz Reference, controls whether the DCO frequency range is narrowed

  989. #define MCG_C5			*(volatile uint8_t  *)0x40064004 // MCG Control 5 Register

  990. #define MCG_C5_PRDIV0(n)		(uint8_t)((n) & 0x1F)		// PLL External Reference Divider

  991. #define MCG_C5_PLLSTEN0			(uint8_t)0x20			// PLL Stop Enable

  992. #define MCG_C5_PLLCLKEN0		(uint8_t)0x40			// PLL Clock Enable

  993. #define MCG_C6			*(volatile uint8_t  *)0x40064005 // MCG Control 6 Register

  994. #define MCG_C6_VDIV0(n)			(uint8_t)((n) & 0x1F)		// VCO 0 Divider

  995. #define MCG_C6_CME0			(uint8_t)0x20			// Clock Monitor Enable

  996. #define MCG_C6_PLLS			(uint8_t)0x40			// PLL Select, Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00. 

  997. #define MCG_C6_LOLIE0			(uint8_t)0x80			// Loss of Lock Interrrupt Enable

  998. #define MCG_S			*(volatile uint8_t  *)0x40064006 // MCG Status Register

  999. #define MCG_S_IRCST			(uint8_t)0x01			// Internal Reference Clock Status

  1000. #define MCG_S_OSCINIT0			(uint8_t)0x02			// OSC Initialization,	resets to 0, is set to 1 after the initialization cycles of the crystal oscillator

  1001. #define MCG_S_CLKST(n)			(uint8_t)(((n) & 0x03) << 2)	// Clock Mode Status, 0=FLL is selected, 1= Internal ref, 2=External ref, 3=PLL

  1002. #define MCG_S_CLKST_MASK		(uint8_t)0x0C

  1003. #define MCG_S_IREFST			(uint8_t)0x10			// Internal Reference Status

  1004. #define MCG_S_PLLST			(uint8_t)0x20			// PLL Select Status

  1005. #define MCG_S_LOCK0			(uint8_t)0x40			// Lock Status, 0=PLL Unlocked, 1=PLL Locked

  1006. #define MCG_S_LOLS0			(uint8_t)0x80			// Loss of Lock Status

  1007. #define MCG_SC			*(volatile uint8_t  *)0x40064008 // MCG Status and Control Register

  1008. #define MCG_SC_LOCS0			(uint8_t)0x01			// OSC0 Loss of Clock Status

  1009. #define MCG_SC_FCRDIV(n)		(uint8_t)(((n) & 0x07) << 1)	// Fast Clock Internal Reference Divider

  1010. #define MCG_SC_FLTPRSRV			(uint8_t)0x10			// FLL Filter Preserve Enable

  1011. #define MCG_SC_ATMF			(uint8_t)0x20			// Automatic Trim Machine Fail Flag

  1012. #define MCG_SC_ATMS			(uint8_t)0x40			// Automatic Trim Machine Select

  1013. #define MCG_SC_ATME			(uint8_t)0x80			// Automatic Trim Machine Enable

  1014. #define MCG_ATCVH		*(volatile uint8_t  *)0x4006400A // MCG Auto Trim Compare Value High Register

  1015. #define MCG_ATCVL		*(volatile uint8_t  *)0x4006400B // MCG Auto Trim Compare Value Low Register

  1016. #define MCG_C7			*(volatile uint8_t  *)0x4006400C // MCG Control 7 Register

  1017. #define MCG_C8			*(volatile uint8_t  *)0x4006400D // MCG Control 8 Register

  1018. 

  1019. // Chapter 25: Oscillator (OSC)

  1020. #define OSC0_CR			*(volatile uint8_t  *)0x40065000 // OSC Control Register

  1021. #define OSC_SC16P			(uint8_t)0x01			// Oscillator 16 pF Capacitor Load Configure

  1022. #define OSC_SC8P			(uint8_t)0x02			// Oscillator 8 pF Capacitor Load Configure

  1023. #define OSC_SC4P			(uint8_t)0x04			// Oscillator 4 pF Capacitor Load Configure

  1024. #define OSC_SC2P			(uint8_t)0x08			// Oscillator 2 pF Capacitor Load Configure

  1025. #define OSC_EREFSTEN			(uint8_t)0x20			// External Reference Stop Enable, Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters Stop mode.

  1026. #define OSC_ERCLKEN			(uint8_t)0x80			// External Reference Enable, Enables external reference clock (OSCERCLK).

  1027. 

  1028. // Chapter 27: Flash Memory Controller (FMC)

  1029. #define FMC_PFAPR		*(volatile uint32_t *)0x4001F000	// Flash Access Protection

  1030. #define FMC_PFB0CR		*(volatile uint32_t *)0x4001F004	// Flash Control

  1031. #define FMC_TAGVDW0S0		*(volatile uint32_t *)0x4001F100	// Cache Tag Storage

  1032. #define FMC_TAGVDW0S1		*(volatile uint32_t *)0x4001F104	// Cache Tag Storage

  1033. #define FMC_TAGVDW1S0		*(volatile uint32_t *)0x4001F108	// Cache Tag Storage

  1034. #define FMC_TAGVDW1S1		*(volatile uint32_t *)0x4001F10C	// Cache Tag Storage

  1035. #define FMC_TAGVDW2S0		*(volatile uint32_t *)0x4001F110	// Cache Tag Storage

  1036. #define FMC_TAGVDW2S1		*(volatile uint32_t *)0x4001F114	// Cache Tag Storage

  1037. #define FMC_TAGVDW3S0		*(volatile uint32_t *)0x4001F118	// Cache Tag Storage

  1038. #define FMC_TAGVDW3S1		*(volatile uint32_t *)0x4001F11C	// Cache Tag Storage

  1039. #define FMC_DATAW0S0		*(volatile uint32_t *)0x4001F200	// Cache Data Storage

  1040. #define FMC_DATAW0S1		*(volatile uint32_t *)0x4001F204	// Cache Data Storage

  1041. #define FMC_DATAW1S0		*(volatile uint32_t *)0x4001F208	// Cache Data Storage

  1042. #define FMC_DATAW1S1		*(volatile uint32_t *)0x4001F20C	// Cache Data Storage

  1043. #define FMC_DATAW2S0		*(volatile uint32_t *)0x4001F210	// Cache Data Storage

  1044. #define FMC_DATAW2S1		*(volatile uint32_t *)0x4001F214	// Cache Data Storage

  1045. #define FMC_DATAW3S0		*(volatile uint32_t *)0x4001F218	// Cache Data Storage

  1046. #define FMC_DATAW3S1		*(volatile uint32_t *)0x4001F21C	// Cache Data Storage

  1047. 

  1048. // Chapter 28: Flash Memory Module (FTFL)

  1049. #define FTFL_FSTAT		*(volatile uint8_t  *)0x40020000      // Flash Status Register

  1050. #define FTFL_FSTAT_CCIF			(uint8_t)0x80			// Command Complete Interrupt Flag

  1051. #define FTFL_FSTAT_RDCOLERR		(uint8_t)0x40			// Flash Read Collision Error Flag

  1052. #define FTFL_FSTAT_ACCERR		(uint8_t)0x20			// Flash Access Error Flag

  1053. #define FTFL_FSTAT_FPVIOL		(uint8_t)0x10			// Flash Protection Violation Flag

  1054. #define FTFL_FSTAT_MGSTAT0		(uint8_t)0x01			// Memory Controller Command Completion Status Flag

  1055. #define FTFL_FCNFG		*(volatile uint8_t  *)0x40020001      // Flash Configuration Register

  1056. #define FTFL_FCNFG_CCIE			(uint8_t)0x80			// Command Complete Interrupt Enable

  1057. #define FTFL_FCNFG_RDCOLLIE		(uint8_t)0x40			// Read Collision Error Interrupt Enable

  1058. #define FTFL_FCNFG_ERSAREQ		(uint8_t)0x20			// Erase All Request

  1059. #define FTFL_FCNFG_ERSSUSP		(uint8_t)0x10			// Erase Suspend

  1060. #define FTFL_FCNFG_PFLSH		(uint8_t)0x04			// Flash memory configuration

  1061. #define FTFL_FCNFG_RAMRDY		(uint8_t)0x02			// RAM Ready

  1062. #define FTFL_FCNFG_EEERDY		(uint8_t)0x01			// EEPROM Ready

  1063. #define FTFL_FSEC		*(const	   uint8_t  *)0x40020002      // Flash Security Register

  1064. #define FTFL_FOPT		*(const	   uint8_t  *)0x40020003      // Flash Option Register

  1065. #define FTFL_FCCOB3		*(volatile uint8_t  *)0x40020004      // Flash Common Command Object Registers

  1066. #define FTFL_FCCOB2		*(volatile uint8_t  *)0x40020005

  1067. #define FTFL_FCCOB1		*(volatile uint8_t  *)0x40020006

  1068. #define FTFL_FCCOB0		*(volatile uint8_t  *)0x40020007

  1069. #define FTFL_FCCOB7		*(volatile uint8_t  *)0x40020008

  1070. #define FTFL_FCCOB6		*(volatile uint8_t  *)0x40020009

  1071. #define FTFL_FCCOB5		*(volatile uint8_t  *)0x4002000A

  1072. #define FTFL_FCCOB4		*(volatile uint8_t  *)0x4002000B

  1073. #define FTFL_FCCOBB		*(volatile uint8_t  *)0x4002000C

  1074. #define FTFL_FCCOBA		*(volatile uint8_t  *)0x4002000D

  1075. #define FTFL_FCCOB9		*(volatile uint8_t  *)0x4002000E

  1076. #define FTFL_FCCOB8		*(volatile uint8_t  *)0x4002000F

  1077. #define FTFL_FPROT3		*(volatile uint8_t  *)0x40020010      // Program Flash Protection Registers

  1078. #define FTFL_FPROT2		*(volatile uint8_t  *)0x40020011      // Program Flash Protection Registers

  1079. #define FTFL_FPROT1		*(volatile uint8_t  *)0x40020012      // Program Flash Protection Registers

  1080. #define FTFL_FPROT0		*(volatile uint8_t  *)0x40020013      // Program Flash Protection Registers

  1081. #define FTFL_FEPROT		*(volatile uint8_t  *)0x40020016      // EEPROM Protection Register

  1082. #define FTFL_FDPROT		*(volatile uint8_t  *)0x40020017      // Data Flash Protection Register

  1083. 

  1084. // Chapter 30: Cyclic Redundancy Check (CRC)

  1085. #define CRC_CRC			*(volatile uint32_t *)0x40032000 // CRC Data register

  1086. #define CRC_GPOLY		*(volatile uint32_t *)0x40032004 // CRC Polynomial register

  1087. #define CRC_CTRL		*(volatile uint32_t *)0x40032008 // CRC Control register

  1088. 

  1089. // Chapter 31: Analog-to-Digital Converter (ADC)

  1090. #define ADC0_SC1A		*(volatile uint32_t *)0x4003B000 // ADC status and control registers 1

  1091. #define ADC0_SC1B		*(volatile uint32_t *)0x4003B004 // ADC status and control registers 1

  1092. #define ADC_SC1_COCO			(uint32_t)0x80			// Conversion complete flag

  1093. #define ADC_SC1_AIEN			(uint32_t)0x40			// Interrupt enable

  1094. #define ADC_SC1_DIFF			(uint32_t)0x20			// Differential mode enable

  1095. #define ADC_SC1_ADCH(n)			(uint32_t)((n) & 0x1F)		// Input channel select

  1096. #define ADC0_CFG1		*(volatile uint32_t *)0x4003B008 // ADC configuration register 1

  1097. #define ADC_CFG1_ADLPC			(uint32_t)0x80			// Low-power configuration

  1098. #define ADC_CFG1_ADIV(n)		(uint32_t)(((n) & 3) << 5)	// Clock divide select, 0=direct, 1=div2, 2=div4, 3=div8

  1099. #define ADC_CFG1_ADLSMP			(uint32_t)0x10			// Sample time configuration, 0=Short, 1=Long

  1100. #define ADC_CFG1_MODE(n)		(uint32_t)(((n) & 3) << 2)	// Conversion mode, 0=8 bit, 1=12 bit, 2=10 bit, 3=16 bit

  1101. #define ADC_CFG1_ADICLK(n)		(uint32_t)(((n) & 3) << 0)	// Input clock, 0=bus, 1=bus/2, 2=OSCERCLK, 3=async

  1102. #define ADC0_CFG2		*(volatile uint32_t *)0x4003B00C // Configuration register 2

  1103. #define ADC_CFG2_MUXSEL			(uint32_t)0x10			// 0=a channels, 1=b channels

  1104. #define ADC_CFG2_ADACKEN		(uint32_t)0x08			// async clock enable

  1105. #define ADC_CFG2_ADHSC			(uint32_t)0x04			// High speed configuration

  1106. #define ADC_CFG2_ADLSTS(n)		(uint32_t)(((n) & 3) << 0)	// Sample time, 0=24 cycles, 1=12 cycles, 2=6 cycles, 3=2 cycles

  1107. #define ADC0_RA			*(volatile uint32_t *)0x4003B010 // ADC data result register

  1108. #define ADC0_RB			*(volatile uint32_t *)0x4003B014 // ADC data result register

  1109. #define ADC0_CV1		*(volatile uint32_t *)0x4003B018 // Compare value registers

  1110. #define ADC0_CV2		*(volatile uint32_t *)0x4003B01C // Compare value registers

  1111. #define ADC0_SC2		*(volatile uint32_t *)0x4003B020 // Status and control register 2

  1112. #define ADC_SC2_ADACT			(uint32_t)0x80			// Conversion active

  1113. #define ADC_SC2_ADTRG			(uint32_t)0x40			// Conversion trigger select, 0=software, 1=hardware

  1114. #define ADC_SC2_ACFE			(uint32_t)0x20			// Compare function enable

  1115. #define ADC_SC2_ACFGT			(uint32_t)0x10			// Compare function greater than enable

  1116. #define ADC_SC2_ACREN			(uint32_t)0x08			// Compare function range enable

  1117. #define ADC_SC2_DMAEN			(uint32_t)0x04			// DMA enable

  1118. #define ADC_SC2_REFSEL(n)		(uint32_t)(((n) & 3) << 0)	// Voltage reference, 0=vcc/external, 1=1.2 volts

  1119. #define ADC0_SC3		*(volatile uint32_t *)0x4003B024 // Status and control register 3

  1120. #define ADC_SC3_CAL			(uint32_t)0x80			// Calibration, 1=begin, stays set while cal in progress

  1121. #define ADC_SC3_CALF			(uint32_t)0x40			// Calibration failed flag

  1122. #define ADC_SC3_ADCO			(uint32_t)0x08			// Continuous conversion enable

  1123. #define ADC_SC3_AVGE			(uint32_t)0x04			// Hardware average enable

  1124. #define ADC_SC3_AVGS(n)			(uint32_t)(((n) & 3) << 0)	// avg select, 0=4 samples, 1=8 samples, 2=16 samples, 3=32 samples

  1125. #define ADC0_OFS		*(volatile uint32_t *)0x4003B028 // ADC offset correction register

  1126. #define ADC0_PG			*(volatile uint32_t *)0x4003B02C // ADC plus-side gain register

  1127. #define ADC0_MG			*(volatile uint32_t *)0x4003B030 // ADC minus-side gain register

  1128. #define ADC0_CLPD		*(volatile uint32_t *)0x4003B034 // ADC plus-side general calibration value register

  1129. #define ADC0_CLPS		*(volatile uint32_t *)0x4003B038 // ADC plus-side general calibration value register

  1130. #define ADC0_CLP4		*(volatile uint32_t *)0x4003B03C // ADC plus-side general calibration value register

  1131. #define ADC0_CLP3		*(volatile uint32_t *)0x4003B040 // ADC plus-side general calibration value register

  1132. #define ADC0_CLP2		*(volatile uint32_t *)0x4003B044 // ADC plus-side general calibration value register

  1133. #define ADC0_CLP1		*(volatile uint32_t *)0x4003B048 // ADC plus-side general calibration value register

  1134. #define ADC0_CLP0		*(volatile uint32_t *)0x4003B04C // ADC plus-side general calibration value register

  1135. #define ADC0_PGA		*(volatile uint32_t *)0x4003B050 // ADC Programmable Gain Amplifier

  1136. #define ADC_PGA_PGAEN			(uint32_t)0x00800000		// Enable

  1137. #define ADC_PGA_PGALPB			(uint32_t)0x00100000		// Low-Power Mode Control, 0=low power, 1=normal

  1138. #define ADC_PGA_PGAG(n)			(uint32_t)(((n) & 15) << 16)	// Gain, 0=1X, 1=2X, 2=4X, 3=8X, 4=16X, 5=32X, 6=64X

  1139. #define ADC0_CLMD		*(volatile uint32_t *)0x4003B054 // ADC minus-side general calibration value register

  1140. #define ADC0_CLMS		*(volatile uint32_t *)0x4003B058 // ADC minus-side general calibration value register

  1141. #define ADC0_CLM4		*(volatile uint32_t *)0x4003B05C // ADC minus-side general calibration value register

  1142. #define ADC0_CLM3		*(volatile uint32_t *)0x4003B060 // ADC minus-side general calibration value register

  1143. #define ADC0_CLM2		*(volatile uint32_t *)0x4003B064 // ADC minus-side general calibration value register

  1144. #define ADC0_CLM1		*(volatile uint32_t *)0x4003B068 // ADC minus-side general calibration value register

  1145. #define ADC0_CLM0		*(volatile uint32_t *)0x4003B06C // ADC minus-side general calibration value register

  1146. 

  1147. #define ADC1_SC1A		*(volatile uint32_t *)0x400BB000 // ADC status and control registers 1

  1148. #define ADC1_SC1B		*(volatile uint32_t *)0x400BB004 // ADC status and control registers 1

  1149. #define ADC1_CFG1		*(volatile uint32_t *)0x400BB008 // ADC configuration register 1

  1150. #define ADC1_CFG2		*(volatile uint32_t *)0x400BB00C // Configuration register 2

  1151. #define ADC1_RA			*(volatile uint32_t *)0x400BB010 // ADC data result register

  1152. #define ADC1_RB			*(volatile uint32_t *)0x400BB014 // ADC data result register

  1153. #define ADC1_CV1		*(volatile uint32_t *)0x400BB018 // Compare value registers

  1154. #define ADC1_CV2		*(volatile uint32_t *)0x400BB01C // Compare value registers

  1155. #define ADC1_SC2		*(volatile uint32_t *)0x400BB020 // Status and control register 2

  1156. #define ADC1_SC3		*(volatile uint32_t *)0x400BB024 // Status and control register 3

  1157. #define ADC1_OFS		*(volatile uint32_t *)0x400BB028 // ADC offset correction register

  1158. #define ADC1_PG			*(volatile uint32_t *)0x400BB02C // ADC plus-side gain register

  1159. #define ADC1_MG			*(volatile uint32_t *)0x400BB030 // ADC minus-side gain register

  1160. #define ADC1_CLPD		*(volatile uint32_t *)0x400BB034 // ADC plus-side general calibration value register

  1161. #define ADC1_CLPS		*(volatile uint32_t *)0x400BB038 // ADC plus-side general calibration value register

  1162. #define ADC1_CLP4		*(volatile uint32_t *)0x400BB03C // ADC plus-side general calibration value register

  1163. #define ADC1_CLP3		*(volatile uint32_t *)0x400BB040 // ADC plus-side general calibration value register

  1164. #define ADC1_CLP2		*(volatile uint32_t *)0x400BB044 // ADC plus-side general calibration value register

  1165. #define ADC1_CLP1		*(volatile uint32_t *)0x400BB048 // ADC plus-side general calibration value register

  1166. #define ADC1_CLP0		*(volatile uint32_t *)0x400BB04C // ADC plus-side general calibration value register

  1167. #define ADC1_PGA		*(volatile uint32_t *)0x400BB050 // ADC Programmable Gain Amplifier

  1168. #define ADC1_CLMD		*(volatile uint32_t *)0x400BB054 // ADC minus-side general calibration value register

  1169. #define ADC1_CLMS		*(volatile uint32_t *)0x400BB058 // ADC minus-side general calibration value register

  1170. #define ADC1_CLM4		*(volatile uint32_t *)0x400BB05C // ADC minus-side general calibration value register

  1171. #define ADC1_CLM3		*(volatile uint32_t *)0x400BB060 // ADC minus-side general calibration value register

  1172. #define ADC1_CLM2		*(volatile uint32_t *)0x400BB064 // ADC minus-side general calibration value register

  1173. #define ADC1_CLM1		*(volatile uint32_t *)0x400BB068 // ADC minus-side general calibration value register

  1174. #define ADC1_CLM0		*(volatile uint32_t *)0x400BB06C // ADC minus-side general calibration value register

  1175. 

  1176. #define DAC0_DAT0L		*(volatile uint8_t  *)0x400CC000 // DAC Data Low Register 

  1177. #define DAC0_DATH		*(volatile uint8_t  *)0x400CC001 // DAC Data High Register 

  1178. #define DAC0_DAT1L		*(volatile uint8_t  *)0x400CC002 // DAC Data Low Register 

  1179. #define DAC0_DAT2L		*(volatile uint8_t  *)0x400CC004 // DAC Data Low Register 

  1180. #define DAC0_DAT3L		*(volatile uint8_t  *)0x400CC006 // DAC Data Low Register 

  1181. #define DAC0_DAT4L		*(volatile uint8_t  *)0x400CC008 // DAC Data Low Register 

  1182. #define DAC0_DAT5L		*(volatile uint8_t  *)0x400CC00A // DAC Data Low Register 

  1183. #define DAC0_DAT6L		*(volatile uint8_t  *)0x400CC00C // DAC Data Low Register 

  1184. #define DAC0_DAT7L		*(volatile uint8_t  *)0x400CC00E // DAC Data Low Register 

  1185. #define DAC0_DAT8L		*(volatile uint8_t  *)0x400CC010 // DAC Data Low Register 

  1186. #define DAC0_DAT9L		*(volatile uint8_t  *)0x400CC012 // DAC Data Low Register 

  1187. #define DAC0_DAT10L		*(volatile uint8_t  *)0x400CC014 // DAC Data Low Register 

  1188. #define DAC0_DAT11L		*(volatile uint8_t  *)0x400CC016 // DAC Data Low Register 

  1189. #define DAC0_DAT12L		*(volatile uint8_t  *)0x400CC018 // DAC Data Low Register 

  1190. #define DAC0_DAT13L		*(volatile uint8_t  *)0x400CC01A // DAC Data Low Register 

  1191. #define DAC0_DAT14L		*(volatile uint8_t  *)0x400CC01C // DAC Data Low Register 

  1192. #define DAC0_DAT15L		*(volatile uint8_t  *)0x400CC01E // DAC Data Low Register 

  1193. #define DAC0_SR			*(volatile uint8_t  *)0x400CC020 // DAC Status Register 

  1194. #define DAC0_C0			*(volatile uint8_t  *)0x400CC021 // DAC Control Register 

  1195. #define DAC_C0_DACEN			0x80				// DAC Enable

  1196. #define DAC_C0_DACRFS			0x40				// DAC Reference Select

  1197. #define DAC_C0_DACTRGSEL		0x20				// DAC Trigger Select

  1198. #define DAC_C0_DACSWTRG			0x10				// DAC Software Trigger

  1199. #define DAC_C0_LPEN			0x08				// DAC Low Power Control

  1200. #define DAC_C0_DACBWIEN			0x04				// DAC Buffer Watermark Interrupt Enable

  1201. #define DAC_C0_DACBTIEN			0x02				// DAC Buffer Read Pointer Top Flag Interrupt Enable

  1202. #define DAC_C0_DACBBIEN			0x01				// DAC Buffer Read Pointer Bottom Flag Interrupt Enable

  1203. #define DAC0_C1			*(volatile uint8_t  *)0x400CC022 // DAC Control Register 1 

  1204. #define DAC_C1_DMAEN			0x80				// DMA Enable Select

  1205. #define DAC_C1_DACBFWM(n)		(((n) & 3) << 3)		// DAC Buffer Watermark Select

  1206. #define DAC_C1_DACBFMD(n)		(((n) & 3) << 0)		// DAC Buffer Work Mode Select

  1207. #define DAC_C1_DACBFEN			0x00				// DAC Buffer Enable

  1208. 

  1209. #define DAC0_C2			*(volatile uint8_t  *)0x400CC023 // DAC Control Register 2 

  1210. #define DAC_C2_DACBFRP(n)		(((n) & 15) << 4)		// DAC Buffer Read Pointer

  1211. #define DAC_C2_DACBFUP(n)		(((n) & 15) << 0)		// DAC Buffer Upper Limit

  1212. 

  1213. 

  1214. //#define MCG_C2_RANGE0(n)		(uint8_t)(((n) & 0x03) << 4)	// Frequency Range Select, Selects the frequency range for the crystal oscillator

  1215. //#define MCG_C2_LOCRE0			(uint8_t)0x80			// Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0 

  1216. 

  1217. // Chapter 32: Comparator (CMP)

  1218. #define CMP0_CR0		*(volatile uint8_t  *)0x40073000 // CMP Control Register 0

  1219. #define CMP0_CR1		*(volatile uint8_t  *)0x40073001 // CMP Control Register 1

  1220. #define CMP0_FPR		*(volatile uint8_t  *)0x40073002 // CMP Filter Period Register

  1221. #define CMP0_SCR		*(volatile uint8_t  *)0x40073003 // CMP Status and Control Register

  1222. #define CMP0_DACCR		*(volatile uint8_t  *)0x40073004 // DAC Control Register

  1223. #define CMP0_MUXCR		*(volatile uint8_t  *)0x40073005 // MUX Control Register

  1224. #define CMP1_CR0		*(volatile uint8_t  *)0x40073008 // CMP Control Register 0

  1225. #define CMP1_CR1		*(volatile uint8_t  *)0x40073009 // CMP Control Register 1

  1226. #define CMP1_FPR		*(volatile uint8_t  *)0x4007300A // CMP Filter Period Register

  1227. #define CMP1_SCR		*(volatile uint8_t  *)0x4007300B // CMP Status and Control Register

  1228. #define CMP1_DACCR		*(volatile uint8_t  *)0x4007300C // DAC Control Register

  1229. #define CMP1_MUXCR		*(volatile uint8_t  *)0x4007300D // MUX Control Register

  1230. 

  1231. // Chapter 33: Voltage Reference (VREFV1)

  1232. #define VREF_TRM		*(volatile uint8_t  *)0x40074000 // VREF Trim Register

  1233. #define VREF_TRM_CHOPEN			(uint8_t)0x40			// Chop oscillator enable

  1234. #define VREF_TRM_TRIM(n)		((n) & 0x3F)			// Trim bits

  1235. #define VREF_SC			*(volatile uint8_t  *)0x40074001 // VREF Status and Control Register

  1236. #define VREF_SC_VREFEN			(uint8_t)0x80			// Internal Voltage Reference enable

  1237. #define VREF_SC_REGEN			(uint8_t)0x40			// Regulator enable

  1238. #define VREF_SC_ICOMPEN			(uint8_t)0x20			// Second order curvature compensation enable

  1239. #define VREF_SC_VREFST			(uint8_t)0x04			// Internal Voltage Reference stable flag

  1240. #define VREF_SC_MODE_LV(n)		(uint8_t)(((n) & 3) << 0)	// Buffer Mode selection: 0=Bandgap on only

  1241. 									//  1=High power buffer mode,

  1242. 									//  2=Low-power buffer mode

  1243. 

  1244. // Chapter 34: Programmable Delay Block (PDB)

  1245. #define PDB0_SC			*(volatile uint32_t *)0x40036000 // Status and Control Register

  1246. #define PDB_SC_LDMOD(n)			(((n) & 3) << 18)	// Load Mode Select

  1247. #define PDB_SC_PDBEIE			0x00020000		// Sequence Error Interrupt Enable

  1248. #define PDB_SC_SWTRIG			0x00010000		// Software Trigger

  1249. #define PDB_SC_DMAEN			0x00008000		// DMA Enable

  1250. #define PDB_SC_PRESCALER(n)		(((n) & 7) << 12)	// Prescaler Divider Select

  1251. #define PDB_SC_TRGSEL(n)		(((n) & 15) << 8)	// Trigger Input Source Select

  1252. #define PDB_SC_PDBEN			0x00000080		// PDB Enable

  1253. #define PDB_SC_PDBIF			0x00000040		// PDB Interrupt Flag

  1254. #define PDB_SC_PDBIE			0x00000020		// PDB Interrupt Enable.

  1255. #define PDB_SC_MULT(n)			(((n) & 3) << 2)	// Multiplication Factor

  1256. #define PDB_SC_CONT			0x00000002		// Continuous Mode Enable

  1257. #define PDB_SC_LDOK			0x00000001		// Load OK

  1258. #define PDB0_MOD		*(volatile uint32_t *)0x40036004 // Modulus Register

  1259. #define PDB0_CNT		*(volatile uint32_t *)0x40036008 // Counter Register

  1260. #define PDB0_IDLY		*(volatile uint32_t *)0x4003600C // Interrupt Delay Register

  1261. #define PDB0_CH0C1		*(volatile uint32_t *)0x40036010 // Channel n Control Register 1

  1262. #define PDB0_CH0S		*(volatile uint32_t *)0x40036014 // Channel n Status Register

  1263. #define PDB0_CH0DLY0		*(volatile uint32_t *)0x40036018 // Channel n Delay 0 Register

  1264. #define PDB0_CH0DLY1		*(volatile uint32_t *)0x4003601C // Channel n Delay 1 Register

  1265. #define PDB0_POEN		*(volatile uint32_t *)0x40036190 // Pulse-Out n Enable Register

  1266. #define PDB0_PO0DLY		*(volatile uint32_t *)0x40036194 // Pulse-Out n Delay Register

  1267. #define PDB0_PO1DLY		*(volatile uint32_t *)0x40036198 // Pulse-Out n Delay Register

  1268. 

  1269. // Chapter 35: FlexTimer Module (FTM)

  1270. #define FTM0_SC			*(volatile uint32_t *)0x40038000 // Status And Control

  1271. #define FTM_SC_TOF			0x80				// Timer Overflow Flag

  1272. #define FTM_SC_TOIE			0x40				// Timer Overflow Interrupt Enable

  1273. #define FTM_SC_CPWMS			0x20				// Center-Aligned PWM Select

  1274. #define FTM_SC_CLKS(n)			(((n) & 3) << 3)		// Clock Source Selection

  1275. #define FTM_SC_PS(n)			(((n) & 7) << 0)		// Prescale Factor Selection

  1276. #define FTM0_CNT		*(volatile uint32_t *)0x40038004 // Counter

  1277. #define FTM0_MOD		*(volatile uint32_t *)0x40038008 // Modulo

  1278. #define FTM0_C0SC		*(volatile uint32_t *)0x4003800C // Channel 0 Status And Control

  1279. #define FTM0_C0V		*(volatile uint32_t *)0x40038010 // Channel 0 Value

  1280. #define FTM0_C1SC		*(volatile uint32_t *)0x40038014 // Channel 1 Status And Control

  1281. #define FTM0_C1V		*(volatile uint32_t *)0x40038018 // Channel 1 Value

  1282. #define FTM0_C2SC		*(volatile uint32_t *)0x4003801C // Channel 2 Status And Control

  1283. #define FTM0_C2V		*(volatile uint32_t *)0x40038020 // Channel 2 Value

  1284. #define FTM0_C3SC		*(volatile uint32_t *)0x40038024 // Channel 3 Status And Control

  1285. #define FTM0_C3V		*(volatile uint32_t *)0x40038028 // Channel 3 Value

  1286. #define FTM0_C4SC		*(volatile uint32_t *)0x4003802C // Channel 4 Status And Control

  1287. #define FTM0_C4V		*(volatile uint32_t *)0x40038030 // Channel 4 Value

  1288. #define FTM0_C5SC		*(volatile uint32_t *)0x40038034 // Channel 5 Status And Control

  1289. #define FTM0_C5V		*(volatile uint32_t *)0x40038038 // Channel 5 Value

  1290. #define FTM0_C6SC		*(volatile uint32_t *)0x4003803C // Channel 6 Status And Control

  1291. #define FTM0_C6V		*(volatile uint32_t *)0x40038040 // Channel 6 Value

  1292. #define FTM0_C7SC		*(volatile uint32_t *)0x40038044 // Channel 7 Status And Control

  1293. #define FTM0_C7V		*(volatile uint32_t *)0x40038048 // Channel 7 Value

  1294. #define FTM0_CNTIN		*(volatile uint32_t *)0x4003804C // Counter Initial Value

  1295. #define FTM0_STATUS		*(volatile uint32_t *)0x40038050 // Capture And Compare Status

  1296. #define FTM0_MODE		*(volatile uint32_t *)0x40038054 // Features Mode Selection

  1297. #define FTM_MODE_FAULTIE		0x80				// Fault Interrupt Enable

  1298. #define FTM_MODE_FAULTM(n)		(((n) & 3) << 5)		// Fault Control Mode

  1299. #define FTM_MODE_CAPTEST		0x10				// Capture Test Mode Enable

  1300. #define FTM_MODE_PWMSYNC		0x08				// PWM Synchronization Mode

  1301. #define FTM_MODE_WPDIS			0x04				// Write Protection Disable

  1302. #define FTM_MODE_INIT			0x02				// Initialize The Channels Output

  1303. #define FTM_MODE_FTMEN			0x01				// FTM Enable

  1304. #define FTM0_SYNC		*(volatile uint32_t *)0x40038058 // Synchronization

  1305. #define FTM_SYNC_SWSYNC			0x80				// 

  1306. #define FTM_SYNC_TRIG2			0x40				// 

  1307. #define FTM_SYNC_TRIG1			0x20				// 

  1308. #define FTM_SYNC_TRIG0			0x10				// 

  1309. #define FTM_SYNC_SYNCHOM		0x08				// 

  1310. #define FTM_SYNC_REINIT			0x04				// 

  1311. #define FTM_SYNC_CNTMAX			0x02				// 

  1312. #define FTM_SYNC_CNTMIN			0x01				// 

  1313. #define FTM0_OUTINIT		*(volatile uint32_t *)0x4003805C // Initial State For Channels Output

  1314. #define FTM0_OUTMASK		*(volatile uint32_t *)0x40038060 // Output Mask

  1315. #define FTM0_COMBINE		*(volatile uint32_t *)0x40038064 // Function For Linked Channels

  1316. #define FTM0_DEADTIME		*(volatile uint32_t *)0x40038068 // Deadtime Insertion Control

  1317. #define FTM0_EXTTRIG		*(volatile uint32_t *)0x4003806C // FTM External Trigger

  1318. #define FTM0_POL		*(volatile uint32_t *)0x40038070 // Channels Polarity

  1319. #define FTM0_FMS		*(volatile uint32_t *)0x40038074 // Fault Mode Status

  1320. #define FTM0_FILTER		*(volatile uint32_t *)0x40038078 // Input Capture Filter Control

  1321. #define FTM0_FLTCTRL		*(volatile uint32_t *)0x4003807C // Fault Control

  1322. #define FTM0_QDCTRL		*(volatile uint32_t *)0x40038080 // Quadrature Decoder Control And Status

  1323. #define FTM0_CONF		*(volatile uint32_t *)0x40038084 // Configuration

  1324. #define FTM0_FLTPOL		*(volatile uint32_t *)0x40038088 // FTM Fault Input Polarity

  1325. #define FTM0_SYNCONF		*(volatile uint32_t *)0x4003808C // Synchronization Configuration

  1326. #define FTM0_INVCTRL		*(volatile uint32_t *)0x40038090 // FTM Inverting Control

  1327. #define FTM0_SWOCTRL		*(volatile uint32_t *)0x40038094 // FTM Software Output Control

  1328. #define FTM0_PWMLOAD		*(volatile uint32_t *)0x40038098 // FTM PWM Load

  1329. #define FTM1_SC			*(volatile uint32_t *)0x40039000 // Status And Control

  1330. #define FTM1_CNT		*(volatile uint32_t *)0x40039004 // Counter

  1331. #define FTM1_MOD		*(volatile uint32_t *)0x40039008 // Modulo

  1332. #define FTM1_C0SC		*(volatile uint32_t *)0x4003900C // Channel 0 Status And Control

  1333. #define FTM1_C0V		*(volatile uint32_t *)0x40039010 // Channel 0 Value

  1334. #define FTM1_C1SC		*(volatile uint32_t *)0x40039014 // Channel 1 Status And Control

  1335. #define FTM1_C1V		*(volatile uint32_t *)0x40039018 // Channel 1 Value

  1336. #define FTM1_CNTIN		*(volatile uint32_t *)0x4003904C // Counter Initial Value

  1337. #define FTM1_STATUS		*(volatile uint32_t *)0x40039050 // Capture And Compare Status

  1338. #define FTM1_MODE		*(volatile uint32_t *)0x40039054 // Features Mode Selection

  1339. #define FTM1_SYNC		*(volatile uint32_t *)0x40039058 // Synchronization

  1340. #define FTM1_OUTINIT		*(volatile uint32_t *)0x4003905C // Initial State For Channels Output

  1341. #define FTM1_OUTMASK		*(volatile uint32_t *)0x40039060 // Output Mask

  1342. #define FTM1_COMBINE		*(volatile uint32_t *)0x40039064 // Function For Linked Channels

  1343. #define FTM1_DEADTIME		*(volatile uint32_t *)0x40039068 // Deadtime Insertion Control

  1344. #define FTM1_EXTTRIG		*(volatile uint32_t *)0x4003906C // FTM External Trigger

  1345. #define FTM1_POL		*(volatile uint32_t *)0x40039070 // Channels Polarity

  1346. #define FTM1_FMS		*(volatile uint32_t *)0x40039074 // Fault Mode Status

  1347. #define FTM1_FILTER		*(volatile uint32_t *)0x40039078 // Input Capture Filter Control

  1348. #define FTM1_FLTCTRL		*(volatile uint32_t *)0x4003907C // Fault Control

  1349. #define FTM1_QDCTRL		*(volatile uint32_t *)0x40039080 // Quadrature Decoder Control And Status

  1350. #define FTM1_CONF		*(volatile uint32_t *)0x40039084 // Configuration

  1351. #define FTM1_FLTPOL		*(volatile uint32_t *)0x40039088 // FTM Fault Input Polarity

  1352. #define FTM1_SYNCONF		*(volatile uint32_t *)0x4003908C // Synchronization Configuration

  1353. #define FTM1_INVCTRL		*(volatile uint32_t *)0x40039090 // FTM Inverting Control

  1354. #define FTM1_SWOCTRL		*(volatile uint32_t *)0x40039094 // FTM Software Output Control

  1355. #define FTM1_PWMLOAD		*(volatile uint32_t *)0x40039098 // FTM PWM Load

  1356. #define FTM2_SC			*(volatile uint32_t *)0x400B8000 // Status And Control

  1357. #define FTM2_CNT		*(volatile uint32_t *)0x400B8004 // Counter

  1358. #define FTM2_MOD		*(volatile uint32_t *)0x400B8008 // Modulo

  1359. #define FTM2_C0SC		*(volatile uint32_t *)0x400B800C // Channel 0 Status And Control

  1360. #define FTM2_C0V		*(volatile uint32_t *)0x400B8010 // Channel 0 Value

  1361. #define FTM2_C1SC		*(volatile uint32_t *)0x400B8014 // Channel 1 Status And Control

  1362. #define FTM2_C1V		*(volatile uint32_t *)0x400B8018 // Channel 1 Value

  1363. #define FTM2_CNTIN		*(volatile uint32_t *)0x400B804C // Counter Initial Value

  1364. #define FTM2_STATUS		*(volatile uint32_t *)0x400B8050 // Capture And Compare Status

  1365. #define FTM2_MODE		*(volatile uint32_t *)0x400B8054 // Features Mode Selection

  1366. #define FTM2_SYNC		*(volatile uint32_t *)0x400B8058 // Synchronization

  1367. #define FTM2_OUTINIT		*(volatile uint32_t *)0x400B805C // Initial State For Channels Output

  1368. #define FTM2_OUTMASK		*(volatile uint32_t *)0x400B8060 // Output Mask

  1369. #define FTM2_COMBINE		*(volatile uint32_t *)0x400B8064 // Function For Linked Channels

  1370. #define FTM2_DEADTIME		*(volatile uint32_t *)0x400B8068 // Deadtime Insertion Control

  1371. #define FTM2_EXTTRIG		*(volatile uint32_t *)0x400B806C // FTM External Trigger

  1372. #define FTM2_POL		*(volatile uint32_t *)0x400B8070 // Channels Polarity

  1373. #define FTM2_FMS		*(volatile uint32_t *)0x400B8074 // Fault Mode Status

  1374. #define FTM2_FILTER		*(volatile uint32_t *)0x400B8078 // Input Capture Filter Control

  1375. #define FTM2_FLTCTRL		*(volatile uint32_t *)0x400B807C // Fault Control

  1376. #define FTM2_QDCTRL		*(volatile uint32_t *)0x400B8080 // Quadrature Decoder Control And Status

  1377. #define FTM2_CONF		*(volatile uint32_t *)0x400B8084 // Configuration

  1378. #define FTM2_FLTPOL		*(volatile uint32_t *)0x400B8088 // FTM Fault Input Polarity

  1379. #define FTM2_SYNCONF		*(volatile uint32_t *)0x400B808C // Synchronization Configuration

  1380. #define FTM2_INVCTRL		*(volatile uint32_t *)0x400B8090 // FTM Inverting Control

  1381. #define FTM2_SWOCTRL		*(volatile uint32_t *)0x400B8094 // FTM Software Output Control

  1382. #define FTM2_PWMLOAD		*(volatile uint32_t *)0x400B8098 // FTM PWM Load

  1383. 

  1384. // Chapter 36: Periodic Interrupt Timer (PIT)

  1385. #define PIT_MCR			*(volatile uint32_t *)0x40037000 // PIT Module Control Register

  1386. #define PIT_LDVAL0		*(volatile uint32_t *)0x40037100 // Timer Load Value Register

  1387. #define PIT_CVAL0		*(volatile uint32_t *)0x40037104 // Current Timer Value Register

  1388. #define PIT_TCTRL0		*(volatile uint32_t *)0x40037108 // Timer Control Register

  1389. #define PIT_TFLG0		*(volatile uint32_t *)0x4003710C // Timer Flag Register

  1390. #define PIT_LDVAL1		*(volatile uint32_t *)0x40037110 // Timer Load Value Register

  1391. #define PIT_CVAL1		*(volatile uint32_t *)0x40037114 // Current Timer Value Register

  1392. #define PIT_TCTRL1		*(volatile uint32_t *)0x40037118 // Timer Control Register

  1393. #define PIT_TFLG1		*(volatile uint32_t *)0x4003711C // Timer Flag Register

  1394. #define PIT_LDVAL2		*(volatile uint32_t *)0x40037120 // Timer Load Value Register

  1395. #define PIT_CVAL2		*(volatile uint32_t *)0x40037124 // Current Timer Value Register

  1396. #define PIT_TCTRL2		*(volatile uint32_t *)0x40037128 // Timer Control Register

  1397. #define PIT_TFLG2		*(volatile uint32_t *)0x4003712C // Timer Flag Register

  1398. #define PIT_LDVAL3		*(volatile uint32_t *)0x40037130 // Timer Load Value Register

  1399. #define PIT_CVAL3		*(volatile uint32_t *)0x40037134 // Current Timer Value Register

  1400. #define PIT_TCTRL3		*(volatile uint32_t *)0x40037138 // Timer Control Register

  1401. #define PIT_TFLG3		*(volatile uint32_t *)0x4003713C // Timer Flag Register

  1402. 

  1403. // Chapter 37: Low-Power Timer (LPTMR)

  1404. #define LPTMR0_CSR		*(volatile uint32_t *)0x40040000 // Low Power Timer Control Status Register

  1405. #define LPTMR0_PSR		*(volatile uint32_t *)0x40040004 // Low Power Timer Prescale Register

  1406. #define LPTMR0_CMR		*(volatile uint32_t *)0x40040008 // Low Power Timer Compare Register

  1407. #define LPTMR0_CNR		*(volatile uint32_t *)0x4004000C // Low Power Timer Counter Register

  1408. 

  1409. // Chapter 38: Carrier Modulator Transmitter (CMT)

  1410. #define CMT_CGH1		*(volatile uint8_t  *)0x40062000 // CMT Carrier Generator High Data Register 1

  1411. #define CMT_CGL1		*(volatile uint8_t  *)0x40062001 // CMT Carrier Generator Low Data Register 1

  1412. #define CMT_CGH2		*(volatile uint8_t  *)0x40062002 // CMT Carrier Generator High Data Register 2

  1413. #define CMT_CGL2		*(volatile uint8_t  *)0x40062003 // CMT Carrier Generator Low Data Register 2

  1414. #define CMT_OC			*(volatile uint8_t  *)0x40062004 // CMT Output Control Register

  1415. #define CMT_MSC			*(volatile uint8_t  *)0x40062005 // CMT Modulator Status and Control Register

  1416. #define CMT_CMD1		*(volatile uint8_t  *)0x40062006 // CMT Modulator Data Register Mark High

  1417. #define CMT_CMD2		*(volatile uint8_t  *)0x40062007 // CMT Modulator Data Register Mark Low

  1418. #define CMT_CMD3		*(volatile uint8_t  *)0x40062008 // CMT Modulator Data Register Space High

  1419. #define CMT_CMD4		*(volatile uint8_t  *)0x40062009 // CMT Modulator Data Register Space Low

  1420. #define CMT_PPS			*(volatile uint8_t  *)0x4006200A // CMT Primary Prescaler Register

  1421. #define CMT_DMA			*(volatile uint8_t  *)0x4006200B // CMT Direct Memory Access Register

  1422. 

  1423. // Chapter 39: Real Time Clock (RTC)

  1424. #define RTC_TSR			*(volatile uint32_t *)0x4003D000 // RTC Time Seconds Register

  1425. #define RTC_TPR			*(volatile uint32_t *)0x4003D004 // RTC Time Prescaler Register

  1426. #define RTC_TAR			*(volatile uint32_t *)0x4003D008 // RTC Time Alarm Register

  1427. #define RTC_TCR			*(volatile uint32_t *)0x4003D00C // RTC Time Compensation Register

  1428. #define RTC_TCR_CIC(n)			(((n) & 255) << 24)		// Compensation Interval Counter

  1429. #define RTC_TCR_TCV(n)			(((n) & 255) << 16)		// Time Compensation Value

  1430. #define RTC_TCR_CIR(n)			(((n) & 255) << 8)		// Compensation Interval Register

  1431. #define RTC_TCR_TCR(n)			(((n) & 255) << 0)		// Time Compensation Register

  1432. #define RTC_CR			*(volatile uint32_t *)0x4003D010 // RTC Control Register

  1433. #define RTC_CR_SC2P			(uint32_t)0x00002000		// 

  1434. #define RTC_CR_SC4P			(uint32_t)0x00001000		// 

  1435. #define RTC_CR_SC8P			(uint32_t)0x00000800		// 

  1436. #define RTC_CR_SC16P			(uint32_t)0x00000400		// 

  1437. #define RTC_CR_CLKO			(uint32_t)0x00000200		// 

  1438. #define RTC_CR_OSCE			(uint32_t)0x00000100		// 

  1439. #define RTC_CR_UM			(uint32_t)0x00000008		// 

  1440. #define RTC_CR_SUP			(uint32_t)0x00000004		// 

  1441. #define RTC_CR_WPE			(uint32_t)0x00000002		// 

  1442. #define RTC_CR_SWR			(uint32_t)0x00000001		// 

  1443. #define RTC_SR			*(volatile uint32_t *)0x4003D014 // RTC Status Register

  1444. #define RTC_SR_TCE			(uint32_t)0x00000010		// 

  1445. #define RTC_SR_TAF			(uint32_t)0x00000004		// 

  1446. #define RTC_SR_TOF			(uint32_t)0x00000002		// 

  1447. #define RTC_SR_TIF			(uint32_t)0x00000001		// 

  1448. #define RTC_LR			*(volatile uint32_t *)0x4003D018 // RTC Lock Register

  1449. #define RTC_IER			*(volatile uint32_t *)0x4003D01C // RTC Interrupt Enable Register

  1450. #define RTC_WAR			*(volatile uint32_t *)0x4003D800 // RTC Write Access Register

  1451. #define RTC_RAR			*(volatile uint32_t *)0x4003D804 // RTC Read Access Register

  1452. 

  1453. // Chapter 40: Universal Serial Bus OTG Controller (USBOTG)

  1454. #define USB0_PERID		*(const	   uint8_t  *)0x40072000 // Peripheral ID register

  1455. #define USB0_IDCOMP		*(const	   uint8_t  *)0x40072004 // Peripheral ID Complement register

  1456. #define USB0_REV		*(const	   uint8_t  *)0x40072008 // Peripheral Revision register

  1457. #define USB0_ADDINFO		*(volatile uint8_t  *)0x4007200C // Peripheral Additional Info register

  1458. #define USB0_OTGISTAT		*(volatile uint8_t  *)0x40072010 // OTG Interrupt Status register

  1459. #define USB_OTGISTAT_IDCHG		(uint8_t)0x80			//

  1460. #define USB_OTGISTAT_ONEMSEC		(uint8_t)0x40			//

  1461. #define USB_OTGISTAT_LINE_STATE_CHG	(uint8_t)0x20			//

  1462. #define USB_OTGISTAT_SESSVLDCHG		(uint8_t)0x08			//

  1463. #define USB_OTGISTAT_B_SESS_CHG		(uint8_t)0x04			//

  1464. #define USB_OTGISTAT_AVBUSCHG		(uint8_t)0x01			//

  1465. #define USB0_OTGICR		*(volatile uint8_t  *)0x40072014 // OTG Interrupt Control Register

  1466. #define USB_OTGICR_IDEN			(uint8_t)0x80			// 

  1467. #define USB_OTGICR_ONEMSECEN		(uint8_t)0x40			// 

  1468. #define USB_OTGICR_LINESTATEEN		(uint8_t)0x20			// 

  1469. #define USB_OTGICR_SESSVLDEN		(uint8_t)0x08			// 

  1470. #define USB_OTGICR_BSESSEN		(uint8_t)0x04			// 

  1471. #define USB_OTGICR_AVBUSEN		(uint8_t)0x01			// 

  1472. #define USB0_OTGSTAT		*(volatile uint8_t  *)0x40072018 // OTG Status register

  1473. #define USB_OTGSTAT_ID			(uint8_t)0x80			// 

  1474. #define USB_OTGSTAT_ONEMSECEN		(uint8_t)0x40			// 

  1475. #define USB_OTGSTAT_LINESTATESTABLE	(uint8_t)0x20			// 

  1476. #define USB_OTGSTAT_SESS_VLD		(uint8_t)0x08			// 

  1477. #define USB_OTGSTAT_BSESSEND		(uint8_t)0x04			// 

  1478. #define USB_OTGSTAT_AVBUSVLD		(uint8_t)0x01			// 

  1479. #define USB0_OTGCTL		*(volatile uint8_t  *)0x4007201C // OTG Control Register

  1480. #define USB_OTGCTL_DPHIGH		(uint8_t)0x80			// 

  1481. #define USB_OTGCTL_DPLOW		(uint8_t)0x20			// 

  1482. #define USB_OTGCTL_DMLOW		(uint8_t)0x10			// 

  1483. #define USB_OTGCTL_OTGEN		(uint8_t)0x04			// 

  1484. #define USB0_ISTAT		*(volatile uint8_t  *)0x40072080 // Interrupt Status Register

  1485. #define USB_ISTAT_STALL			(uint8_t)0x80			// 

  1486. #define USB_ISTAT_ATTACH		(uint8_t)0x40			// 

  1487. #define USB_ISTAT_RESUME		(uint8_t)0x20			// 

  1488. #define USB_ISTAT_SLEEP			(uint8_t)0x10			// 

  1489. #define USB_ISTAT_TOKDNE		(uint8_t)0x08			// 

  1490. #define USB_ISTAT_SOFTOK		(uint8_t)0x04			// 

  1491. #define USB_ISTAT_ERROR			(uint8_t)0x02			// 

  1492. #define USB_ISTAT_USBRST		(uint8_t)0x01			// 

  1493. #define USB0_INTEN		*(volatile uint8_t  *)0x40072084 // Interrupt Enable Register

  1494. #define USB_INTEN_STALLEN		(uint8_t)0x80			// 

  1495. #define USB_INTEN_ATTACHEN		(uint8_t)0x40			// 

  1496. #define USB_INTEN_RESUMEEN		(uint8_t)0x20			// 

  1497. #define USB_INTEN_SLEEPEN		(uint8_t)0x10			// 

  1498. #define USB_INTEN_TOKDNEEN		(uint8_t)0x08			// 

  1499. #define USB_INTEN_SOFTOKEN		(uint8_t)0x04			// 

  1500. #define USB_INTEN_ERROREN		(uint8_t)0x02			// 

  1501. #define USB_INTEN_USBRSTEN		(uint8_t)0x01			// 

  1502. #define USB0_ERRSTAT		*(volatile uint8_t  *)0x40072088 // Error Interrupt Status Register

  1503. #define USB_ERRSTAT_BTSERR		(uint8_t)0x80			// 

  1504. #define USB_ERRSTAT_DMAERR		(uint8_t)0x20			// 

  1505. #define USB_ERRSTAT_BTOERR		(uint8_t)0x10			// 

  1506. #define USB_ERRSTAT_DFN8		(uint8_t)0x08			// 

  1507. #define USB_ERRSTAT_CRC16		(uint8_t)0x04			// 

  1508. #define USB_ERRSTAT_CRC5EOF		(uint8_t)0x02			// 

  1509. #define USB_ERRSTAT_PIDERR		(uint8_t)0x01			// 

  1510. #define USB0_ERREN		*(volatile uint8_t  *)0x4007208C // Error Interrupt Enable Register

  1511. #define USB_ERREN_BTSERREN		(uint8_t)0x80			// 

  1512. #define USB_ERREN_DMAERREN		(uint8_t)0x20			// 

  1513. #define USB_ERREN_BTOERREN		(uint8_t)0x10			// 

  1514. #define USB_ERREN_DFN8EN		(uint8_t)0x08			// 

  1515. #define USB_ERREN_CRC16EN		(uint8_t)0x04			// 

  1516. #define USB_ERREN_CRC5EOFEN		(uint8_t)0x02			// 

  1517. #define USB_ERREN_PIDERREN		(uint8_t)0x01			// 

  1518. #define USB0_STAT		*(volatile uint8_t  *)0x40072090 // Status Register

  1519. #define USB_STAT_TX			(uint8_t)0x08			// 

  1520. #define USB_STAT_ODD			(uint8_t)0x04			// 

  1521. #define USB_STAT_ENDP(n)		(uint8_t)((n) >> 4)		// 

  1522. #define USB0_CTL		*(volatile uint8_t  *)0x40072094 // Control Register

  1523. #define USB_CTL_JSTATE			(uint8_t)0x80			// 

  1524. #define USB_CTL_SE0			(uint8_t)0x40			// 

  1525. #define USB_CTL_TXSUSPENDTOKENBUSY	(uint8_t)0x20			// 

  1526. #define USB_CTL_RESET			(uint8_t)0x10			// 

  1527. #define USB_CTL_HOSTMODEEN		(uint8_t)0x08			// 

  1528. #define USB_CTL_RESUME			(uint8_t)0x04			// 

  1529. #define USB_CTL_ODDRST			(uint8_t)0x02			// 

  1530. #define USB_CTL_USBENSOFEN		(uint8_t)0x01			// 

  1531. #define USB0_ADDR		*(volatile uint8_t  *)0x40072098 // Address Register

  1532. #define USB0_BDTPAGE1		*(volatile uint8_t  *)0x4007209C // BDT Page Register 1

  1533. #define USB0_FRMNUML		*(volatile uint8_t  *)0x400720A0 // Frame Number Register Low

  1534. #define USB0_FRMNUMH		*(volatile uint8_t  *)0x400720A4 // Frame Number Register High

  1535. #define USB0_TOKEN		*(volatile uint8_t  *)0x400720A8 // Token Register

  1536. #define USB0_SOFTHLD		*(volatile uint8_t  *)0x400720AC // SOF Threshold Register

  1537. #define USB0_BDTPAGE2		*(volatile uint8_t  *)0x400720B0 // BDT Page Register 2

  1538. #define USB0_BDTPAGE3		*(volatile uint8_t  *)0x400720B4 // BDT Page Register 3

  1539. #define USB0_ENDPT0		*(volatile uint8_t  *)0x400720C0 // Endpoint Control Register

  1540. #define USB_ENDPT_HOSTWOHUB		(uint8_t)0x80			// host only, enable low speed

  1541. #define USB_ENDPT_RETRYDIS		(uint8_t)0x40			// host only, set to disable NAK retry

  1542. #define USB_ENDPT_EPCTLDIS		(uint8_t)0x10			// 0=control, 1=bulk, interrupt, isync

  1543. #define USB_ENDPT_EPRXEN		(uint8_t)0x08			// enables the endpoint for RX transfers.

  1544. #define USB_ENDPT_EPTXEN		(uint8_t)0x04			// enables the endpoint for TX transfers.

  1545. #define USB_ENDPT_EPSTALL		(uint8_t)0x02			// set to stall endpoint

  1546. #define USB_ENDPT_EPHSHK		(uint8_t)0x01			// enable handshaking during a transaction, generally set unless Isochronous

  1547. #define USB0_ENDPT1		*(volatile uint8_t  *)0x400720C4 // Endpoint Control Register

  1548. #define USB0_ENDPT2		*(volatile uint8_t  *)0x400720C8 // Endpoint Control Register

  1549. #define USB0_ENDPT3		*(volatile uint8_t  *)0x400720CC // Endpoint Control Register

  1550. #define USB0_ENDPT4		*(volatile uint8_t  *)0x400720D0 // Endpoint Control Register

  1551. #define USB0_ENDPT5		*(volatile uint8_t  *)0x400720D4 // Endpoint Control Register

  1552. #define USB0_ENDPT6		*(volatile uint8_t  *)0x400720D8 // Endpoint Control Register

  1553. #define USB0_ENDPT7		*(volatile uint8_t  *)0x400720DC // Endpoint Control Register

  1554. #define USB0_ENDPT8		*(volatile uint8_t  *)0x400720E0 // Endpoint Control Register

  1555. #define USB0_ENDPT9		*(volatile uint8_t  *)0x400720E4 // Endpoint Control Register

  1556. #define USB0_ENDPT10		*(volatile uint8_t  *)0x400720E8 // Endpoint Control Register

  1557. #define USB0_ENDPT11		*(volatile uint8_t  *)0x400720EC // Endpoint Control Register

  1558. #define USB0_ENDPT12		*(volatile uint8_t  *)0x400720F0 // Endpoint Control Register

  1559. #define USB0_ENDPT13		*(volatile uint8_t  *)0x400720F4 // Endpoint Control Register

  1560. #define USB0_ENDPT14		*(volatile uint8_t  *)0x400720F8 // Endpoint Control Register

  1561. #define USB0_ENDPT15		*(volatile uint8_t  *)0x400720FC // Endpoint Control Register

  1562. #define USB0_USBCTRL		*(volatile uint8_t  *)0x40072100 // USB Control Register

  1563. #define USB_USBCTRL_SUSP		(uint8_t)0x80			// Places the USB transceiver into the suspend state.

  1564. #define USB_USBCTRL_PDE			(uint8_t)0x40			// Enables the weak pulldowns on the USB transceiver.

  1565. #define USB0_OBSERVE		*(volatile uint8_t  *)0x40072104 // USB OTG Observe Register

  1566. #define USB_OBSERVE_DPPU		(uint8_t)0x80			// 

  1567. #define USB_OBSERVE_DPPD		(uint8_t)0x40			// 

  1568. #define USB_OBSERVE_DMPD		(uint8_t)0x10			// 

  1569. #define USB0_CONTROL		*(volatile uint8_t  *)0x40072108 // USB OTG Control Register

  1570. #define USB_CONTROL_DPPULLUPNONOTG	(uint8_t)0x10			//  Provides control of the DP PULLUP in the USB OTG module, if USB is configured in non-OTG device mode.

  1571. #define USB0_USBTRC0		*(volatile uint8_t  *)0x4007210C // USB Transceiver Control Register 0

  1572. #define USB_USBTRC_USBRESET		(uint8_t)0x80			//

  1573. #define USB_USBTRC_USBRESMEN		(uint8_t)0x20			//

  1574. #define USB_USBTRC_SYNC_DET		(uint8_t)0x02			//

  1575. #define USB_USBTRC_USB_RESUME_INT	(uint8_t)0x01			//

  1576. #define USB0_USBFRMADJUST	*(volatile uint8_t  *)0x40072114 // Frame Adjust Register

  1577. 

  1578. // Chapter 41: USB Device Charger Detection Module (USBDCD)

  1579. #define USBDCD_CONTROL		*(volatile uint32_t *)0x40035000 // Control register

  1580. #define USBDCD_CLOCK		*(volatile uint32_t *)0x40035004 // Clock register

  1581. #define USBDCD_STATUS		*(volatile uint32_t *)0x40035008 // Status register

  1582. #define USBDCD_TIMER0		*(volatile uint32_t *)0x40035010 // TIMER0 register

  1583. #define USBDCD_TIMER1		*(volatile uint32_t *)0x40035014 // TIMER1 register

  1584. #define USBDCD_TIMER2		*(volatile uint32_t *)0x40035018 // TIMER2 register

  1585. 

  1586. // Chapter 43: SPI (DSPI)

  1587. #define SPI0_MCR		*(volatile uint32_t *)0x4002C000 // DSPI Module Configuration Register

  1588. #define SPI_MCR_MSTR			(uint32_t)0x80000000		// Master/Slave Mode Select

  1589. #define SPI_MCR_CONT_SCKE		(uint32_t)0x40000000		// 

  1590. #define SPI_MCR_DCONF(n)		(((n) & 3) << 28)		// 

  1591. #define SPI_MCR_FRZ			(uint32_t)0x08000000		// 

  1592. #define SPI_MCR_MTFE			(uint32_t)0x04000000		// 

  1593. #define SPI_MCR_ROOE			(uint32_t)0x01000000		// 

  1594. #define SPI_MCR_PCSIS(n)		(((n) & 0x1F) << 16)		//

  1595. #define SPI_MCR_DOZE			(uint32_t)0x00008000		// 

  1596. #define SPI_MCR_MDIS			(uint32_t)0x00004000		// 

  1597. #define SPI_MCR_DIS_TXF			(uint32_t)0x00002000		// 

  1598. #define SPI_MCR_DIS_RXF			(uint32_t)0x00001000		// 

  1599. #define SPI_MCR_CLR_TXF			(uint32_t)0x00000800		// 

  1600. #define SPI_MCR_CLR_RXF			(uint32_t)0x00000400		// 

  1601. #define SPI_MCR_SMPL_PT(n)		(((n) & 3) << 8)		//

  1602. #define SPI_MCR_HALT			(uint32_t)0x00000001		// 

  1603. #define SPI0_TCR		*(volatile uint32_t *)0x4002C008 // DSPI Transfer Count Register

  1604. #define SPI0_CTAR0		*(volatile uint32_t *)0x4002C00C // DSPI Clock and Transfer Attributes Register, In Master Mode

  1605. #define SPI_CTAR_DBR			(uint32_t)0x80000000		// Double Baud Rate

  1606. #define SPI_CTAR_FMSZ(n)		(((n) & 15) << 27)		// Frame Size (+1)

  1607. #define SPI_CTAR_CPOL			(uint32_t)0x04000000		// Clock Polarity

  1608. #define SPI_CTAR_CPHA			(uint32_t)0x02000000		// Clock Phase

  1609. #define SPI_CTAR_LSBFE			(uint32_t)0x01000000		// LSB First

  1610. #define SPI_CTAR_PCSSCK(n)		(((n) & 3) << 22)		// PCS to SCK Delay Prescaler

  1611. #define SPI_CTAR_PASC(n)		(((n) & 3) << 20)		// After SCK Delay Prescaler

  1612. #define SPI_CTAR_PDT(n)			(((n) & 3) << 18)		// Delay after Transfer Prescaler

  1613. #define SPI_CTAR_PBR(n)			(((n) & 3) << 16)		// Baud Rate Prescaler

  1614. #define SPI_CTAR_CSSCK(n)		(((n) & 15) << 12)		// PCS to SCK Delay Scaler

  1615. #define SPI_CTAR_ASC(n)			(((n) & 15) << 8)		// After SCK Delay Scaler

  1616. #define SPI_CTAR_DT(n)			(((n) & 15) << 4)		// Delay After Transfer Scaler

  1617. #define SPI_CTAR_BR(n)			(((n) & 15) << 0)		// Baud Rate Scaler

  1618. #define SPI0_CTAR0_SLAVE	*(volatile uint32_t *)0x4002C00C // DSPI Clock and Transfer Attributes Register, In Slave Mode

  1619. #define SPI0_CTAR1		*(volatile uint32_t *)0x4002C010 // DSPI Clock and Transfer Attributes Register, In Master Mode

  1620. #define SPI0_SR			*(volatile uint32_t *)0x4002C02C // DSPI Status Register

  1621. #define SPI_SR_TCF			(uint32_t)0x80000000		// Transfer Complete Flag

  1622. #define SPI_SR_TXRXS			(uint32_t)0x40000000		// TX and RX Status

  1623. #define SPI_SR_EOQF			(uint32_t)0x10000000		// End of Queue Flag

  1624. #define SPI_SR_TFUF			(uint32_t)0x08000000		// Transmit FIFO Underflow Flag

  1625. #define SPI_SR_TFFF			(uint32_t)0x02000000		// Transmit FIFO Fill Flag

  1626. #define SPI_SR_RFOF			(uint32_t)0x00080000		// Receive FIFO Overflow Flag

  1627. #define SPI_SR_RFDF			(uint32_t)0x00020000		// Receive FIFO Drain Flag

  1628. #define SPI0_RSER		*(volatile uint32_t *)0x4002C030 // DSPI DMA/Interrupt Request Select and Enable Register

  1629. #define SPI_RSER_TCF_RE			(uint32_t)0x80000000		// Transmission Complete Request Enable

  1630. #define SPI_RSER_EOQF_RE		(uint32_t)0x10000000		// DSPI Finished Request Request Enable

  1631. #define SPI_RSER_TFUF_RE		(uint32_t)0x08000000		// Transmit FIFO Underflow Request Enable

  1632. #define SPI_RSER_TFFF_RE		(uint32_t)0x02000000		// Transmit FIFO Fill Request Enable

  1633. #define SPI_RSER_TFFF_DIRS		(uint32_t)0x01000000		// Transmit FIFO FIll Dma or Interrupt Request Select

  1634. #define SPI_RSER_RFOF_RE		(uint32_t)0x00080000		// Receive FIFO Overflow Request Enable

  1635. #define SPI_RSER_RFDF_RE		(uint32_t)0x00020000		// Receive FIFO Drain Request Enable

  1636. #define SPI_RSER_RFDF_DIRS		(uint32_t)0x00010000		// Receive FIFO Drain DMA or Interrupt Request Select

  1637. #define SPI0_PUSHR		*(volatile uint32_t *)0x4002C034 // DSPI PUSH TX FIFO Register In Master Mode

  1638. #define SPI_PUSHR_CONT			(uint32_t)0x80000000		// 

  1639. #define SPI_PUSHR_CTAS(n)		(((n) & 7) << 28)		// 

  1640. #define SPI_PUSHR_EOQ			(uint32_t)0x08000000		// 

  1641. #define SPI_PUSHR_CTCNT			(uint32_t)0x04000000		// 

  1642. #define SPI_PUSHR_PCS(n)		(((n) & 31) << 16)		//

  1643. #define SPI0_PUSHR_SLAVE	*(volatile uint32_t *)0x4002C034 // DSPI PUSH TX FIFO Register In Slave Mode

  1644. #define SPI0_POPR		*(volatile uint32_t *)0x4002C038 // DSPI POP RX FIFO Register

  1645. #define SPI0_TXFR0		*(volatile uint32_t *)0x4002C03C // DSPI Transmit FIFO Registers

  1646. #define SPI0_TXFR1		*(volatile uint32_t *)0x4002C040 // DSPI Transmit FIFO Registers

  1647. #define SPI0_TXFR2		*(volatile uint32_t *)0x4002C044 // DSPI Transmit FIFO Registers

  1648. #define SPI0_TXFR3		*(volatile uint32_t *)0x4002C048 // DSPI Transmit FIFO Registers

  1649. #define SPI0_RXFR0		*(volatile uint32_t *)0x4002C07C // DSPI Receive FIFO Registers

  1650. #define SPI0_RXFR1		*(volatile uint32_t *)0x4002C080 // DSPI Receive FIFO Registers

  1651. #define SPI0_RXFR2		*(volatile uint32_t *)0x4002C084 // DSPI Receive FIFO Registers

  1652. #define SPI0_RXFR3		*(volatile uint32_t *)0x4002C088 // DSPI Receive FIFO Registers

  1653. typedef struct {

  1654. 	volatile uint32_t	MCR;	// 0

  1655. 	volatile uint32_t	unused1;// 4

  1656. 	volatile uint32_t	TCR;	// 8

  1657. 	volatile uint32_t	CTAR0;	// c

  1658. 	volatile uint32_t	CTAR1;	// 10

  1659. 	volatile uint32_t	CTAR2;	// 14

  1660. 	volatile uint32_t	CTAR3;	// 18

  1661. 	volatile uint32_t	CTAR4;	// 1c

  1662. 	volatile uint32_t	CTAR5;	// 20

  1663. 	volatile uint32_t	CTAR6;	// 24

  1664. 	volatile uint32_t	CTAR7;	// 28

  1665. 	volatile uint32_t	SR;	// 2c

  1666. 	volatile uint32_t	RSER;	// 30

  1667. 	volatile uint32_t	PUSHR;	// 34

  1668. 	volatile uint32_t	POPR;	// 38

  1669. 	volatile uint32_t	TXFR[16]; // 3c

  1670. 	volatile uint32_t	RXFR[16]; // 7c

  1671. } SPI_t;

  1672. #define SPI0		(*(SPI_t *)0x4002C000)

  1673. 

  1674. // Chapter 44: Inter-Integrated Circuit (I2C)

  1675. #define I2C0_A1			*(volatile uint8_t  *)0x40066000 // I2C Address Register 1

  1676. #define I2C0_F			*(volatile uint8_t  *)0x40066001 // I2C Frequency Divider register

  1677. #define I2C0_C1			*(volatile uint8_t  *)0x40066002 // I2C Control Register 1

  1678. #define I2C_C1_IICEN			(uint8_t)0x80			// I2C Enable

  1679. #define I2C_C1_IICIE			(uint8_t)0x40			// I2C Interrupt Enable

  1680. #define I2C_C1_MST			(uint8_t)0x20			// Master Mode Select

  1681. #define I2C_C1_TX			(uint8_t)0x10			// Transmit Mode Select

  1682. #define I2C_C1_TXAK			(uint8_t)0x08			// Transmit Acknowledge Enable

  1683. #define I2C_C1_RSTA			(uint8_t)0x04			// Repeat START

  1684. #define I2C_C1_WUEN			(uint8_t)0x02			// Wakeup Enable

  1685. #define I2C_C1_DMAEN			(uint8_t)0x01			// DMA Enable

  1686. #define I2C0_S			*(volatile uint8_t  *)0x40066003 // I2C Status register

  1687. #define I2C_S_TCF			(uint8_t)0x80			// Transfer Complete Flag

  1688. #define I2C_S_IAAS			(uint8_t)0x40			// Addressed As A Slave

  1689. #define I2C_S_BUSY			(uint8_t)0x20			// Bus Busy

  1690. #define I2C_S_ARBL			(uint8_t)0x10			// Arbitration Lost

  1691. #define I2C_S_RAM			(uint8_t)0x08			// Range Address Match

  1692. #define I2C_S_SRW			(uint8_t)0x04			// Slave Read/Write

  1693. #define I2C_S_IICIF			(uint8_t)0x02			// Interrupt Flag

  1694. #define I2C_S_RXAK			(uint8_t)0x01			// Receive Acknowledge

  1695. #define I2C0_D			*(volatile uint8_t  *)0x40066004 // I2C Data I/O register

  1696. #define I2C0_C2			*(volatile uint8_t  *)0x40066005 // I2C Control Register 2

  1697. #define I2C_C2_GCAEN			(uint8_t)0x80			// General Call Address Enable

  1698. #define I2C_C2_ADEXT			(uint8_t)0x40			// Address Extension

  1699. #define I2C_C2_HDRS			(uint8_t)0x20			// High Drive Select

  1700. #define I2C_C2_SBRC			(uint8_t)0x10			// Slave Baud Rate Control

  1701. #define I2C_C2_RMEN			(uint8_t)0x08			// Range Address Matching Enable

  1702. #define I2C_C2_AD(n)			((n) & 7)			// Slave Address, upper 3 bits

  1703. #define I2C0_FLT		*(volatile uint8_t  *)0x40066006 // I2C Programmable Input Glitch Filter register

  1704. #define I2C0_RA			*(volatile uint8_t  *)0x40066007 // I2C Range Address register

  1705. #define I2C0_SMB		*(volatile uint8_t  *)0x40066008 // I2C SMBus Control and Status register

  1706. #define I2C0_A2			*(volatile uint8_t  *)0x40066009 // I2C Address Register 2

  1707. #define I2C0_SLTH		*(volatile uint8_t  *)0x4006600A // I2C SCL Low Timeout Register High

  1708. #define I2C0_SLTL		*(volatile uint8_t  *)0x4006600B // I2C SCL Low Timeout Register Low

  1709. 

  1710. #define I2C1_A1			*(volatile uint8_t  *)0x40067000 // I2C Address Register 1

  1711. #define I2C1_F			*(volatile uint8_t  *)0x40067001 // I2C Frequency Divider register

  1712. #define I2C1_C1			*(volatile uint8_t  *)0x40067002 // I2C Control Register 1

  1713. #define I2C1_S			*(volatile uint8_t  *)0x40067003 // I2C Status register

  1714. #define I2C1_D			*(volatile uint8_t  *)0x40067004 // I2C Data I/O register

  1715. #define I2C1_C2			*(volatile uint8_t  *)0x40067005 // I2C Control Register 2

  1716. #define I2C1_FLT		*(volatile uint8_t  *)0x40067006 // I2C Programmable Input Glitch Filter register

  1717. #define I2C1_RA			*(volatile uint8_t  *)0x40067007 // I2C Range Address register

  1718. #define I2C1_SMB		*(volatile uint8_t  *)0x40067008 // I2C SMBus Control and Status register

  1719. #define I2C1_A2			*(volatile uint8_t  *)0x40067009 // I2C Address Register 2

  1720. #define I2C1_SLTH		*(volatile uint8_t  *)0x4006700A // I2C SCL Low Timeout Register High

  1721. #define I2C1_SLTL		*(volatile uint8_t  *)0x4006700B // I2C SCL Low Timeout Register Low

  1722. 

  1723. // Chapter 45: Universal Asynchronous Receiver/Transmitter (UART)

  1724. #define UART0_BDH		*(volatile uint8_t  *)0x4006A000 // UART Baud Rate Registers: High

  1725. #define UART0_BDL		*(volatile uint8_t  *)0x4006A001 // UART Baud Rate Registers: Low

  1726. #define UART0_C1		*(volatile uint8_t  *)0x4006A002 // UART Control Register 1

  1727. #define UART_C1_LOOPS			(uint8_t)0x80			// When LOOPS is set, the RxD pin is disconnected from the UART and the transmitter output is internally connected to the receiver input

  1728. #define UART_C1_UARTSWAI		(uint8_t)0x40			// UART Stops in Wait Mode

  1729. #define UART_C1_RSRC			(uint8_t)0x20			// When LOOPS is set, the RSRC field determines the source for the receiver shift register input

  1730. #define UART_C1_M			(uint8_t)0x10			// 9-bit or 8-bit Mode Select

  1731. #define UART_C1_WAKE			(uint8_t)0x08			// Determines which condition wakes the UART

  1732. #define UART_C1_ILT			(uint8_t)0x04			// Idle Line Type Select

  1733. #define UART_C1_PE			(uint8_t)0x02			// Parity Enable

  1734. #define UART_C1_PT			(uint8_t)0x01			// Parity Type, 0=even, 1=odd

  1735. #define UART0_C2		*(volatile uint8_t  *)0x4006A003 // UART Control Register 2

  1736. #define UART_C2_TIE			(uint8_t)0x80			// Transmitter Interrupt or DMA Transfer Enable.

  1737. #define UART_C2_TCIE			(uint8_t)0x40			// Transmission Complete Interrupt Enable

  1738. #define UART_C2_RIE			(uint8_t)0x20			// Receiver Full Interrupt or DMA Transfer Enable

  1739. #define UART_C2_ILIE			(uint8_t)0x10			// Idle Line Interrupt Enable

  1740. #define UART_C2_TE			(uint8_t)0x08			// Transmitter Enable

  1741. #define UART_C2_RE			(uint8_t)0x04			// Receiver Enable

  1742. #define UART_C2_RWU			(uint8_t)0x02			// Receiver Wakeup Control

  1743. #define UART_C2_SBK			(uint8_t)0x01			// Send Break

  1744. #define UART0_S1		*(volatile uint8_t  *)0x4006A004 // UART Status Register 1

  1745. #define UART_S1_TDRE			(uint8_t)0x80			// Transmit Data Register Empty Flag

  1746. #define UART_S1_TC			(uint8_t)0x40			// Transmit Complete Flag

  1747. #define UART_S1_RDRF			(uint8_t)0x20			// Receive Data Register Full Flag

  1748. #define UART_S1_IDLE			(uint8_t)0x10			// Idle Line Flag

  1749. #define UART_S1_OR			(uint8_t)0x08			// Receiver Overrun Flag

  1750. #define UART_S1_NF			(uint8_t)0x04			// Noise Flag

  1751. #define UART_S1_FE			(uint8_t)0x02			// Framing Error Flag

  1752. #define UART_S1_PF			(uint8_t)0x01			// Parity Error Flag

  1753. #define UART0_S2		*(volatile uint8_t  *)0x4006A005 // UART Status Register 2

  1754. #define UART0_C3		*(volatile uint8_t  *)0x4006A006 // UART Control Register 3

  1755. #define UART0_D			*(volatile uint8_t  *)0x4006A007 // UART Data Register

  1756. #define UART0_MA1		*(volatile uint8_t  *)0x4006A008 // UART Match Address Registers 1

  1757. #define UART0_MA2		*(volatile uint8_t  *)0x4006A009 // UART Match Address Registers 2

  1758. #define UART0_C4		*(volatile uint8_t  *)0x4006A00A // UART Control Register 4

  1759. #define UART0_C5		*(volatile uint8_t  *)0x4006A00B // UART Control Register 5

  1760. #define UART0_ED		*(volatile uint8_t  *)0x4006A00C // UART Extended Data Register

  1761. #define UART0_MODEM		*(volatile uint8_t  *)0x4006A00D // UART Modem Register

  1762. #define UART0_IR		*(volatile uint8_t  *)0x4006A00E // UART Infrared Register

  1763. #define UART0_PFIFO		*(volatile uint8_t  *)0x4006A010 // UART FIFO Parameters

  1764. #define UART_PFIFO_TXFE			(uint8_t)0x80

  1765. #define UART_PFIFO_RXFE			(uint8_t)0x08

  1766. #define UART0_CFIFO		*(volatile uint8_t  *)0x4006A011 // UART FIFO Control Register

  1767. #define UART_CFIFO_TXFLUSH		(uint8_t)0x80			// 

  1768. #define UART_CFIFO_RXFLUSH		(uint8_t)0x40			// 

  1769. #define UART_CFIFO_RXOFE		(uint8_t)0x04			// 

  1770. #define UART_CFIFO_TXOFE		(uint8_t)0x02			// 

  1771. #define UART_CFIFO_RXUFE		(uint8_t)0x01			// 

  1772. #define UART0_SFIFO		*(volatile uint8_t  *)0x4006A012 // UART FIFO Status Register

  1773. #define UART_SFIFO_TXEMPT		(uint8_t)0x80

  1774. #define UART_SFIFO_RXEMPT		(uint8_t)0x40

  1775. #define UART_SFIFO_RXOF			(uint8_t)0x04

  1776. #define UART_SFIFO_TXOF			(uint8_t)0x02

  1777. #define UART_SFIFO_RXUF			(uint8_t)0x01

  1778. #define UART0_TWFIFO		*(volatile uint8_t  *)0x4006A013 // UART FIFO Transmit Watermark

  1779. #define UART0_TCFIFO		*(volatile uint8_t  *)0x4006A014 // UART FIFO Transmit Count

  1780. #define UART0_RWFIFO		*(volatile uint8_t  *)0x4006A015 // UART FIFO Receive Watermark

  1781. #define UART0_RCFIFO		*(volatile uint8_t  *)0x4006A016 // UART FIFO Receive Count

  1782. #define UART0_C7816		*(volatile uint8_t  *)0x4006A018 // UART 7816 Control Register

  1783. #define UART0_IE7816		*(volatile uint8_t  *)0x4006A019 // UART 7816 Interrupt Enable Register

  1784. #define UART0_IS7816		*(volatile uint8_t  *)0x4006A01A // UART 7816 Interrupt Status Register

  1785. #define UART0_WP7816T0		*(volatile uint8_t  *)0x4006A01B // UART 7816 Wait Parameter Register

  1786. #define UART0_WP7816T1		*(volatile uint8_t  *)0x4006A01B // UART 7816 Wait Parameter Register

  1787. #define UART0_WN7816		*(volatile uint8_t  *)0x4006A01C // UART 7816 Wait N Register

  1788. #define UART0_WF7816		*(volatile uint8_t  *)0x4006A01D // UART 7816 Wait FD Register

  1789. #define UART0_ET7816		*(volatile uint8_t  *)0x4006A01E // UART 7816 Error Threshold Register

  1790. #define UART0_TL7816		*(volatile uint8_t  *)0x4006A01F // UART 7816 Transmit Length Register

  1791. #define UART0_C6		*(volatile uint8_t  *)0x4006A021 // UART CEA709.1-B Control Register 6

  1792. #define UART0_PCTH		*(volatile uint8_t  *)0x4006A022 // UART CEA709.1-B Packet Cycle Time Counter High

  1793. #define UART0_PCTL		*(volatile uint8_t  *)0x4006A023 // UART CEA709.1-B Packet Cycle Time Counter Low

  1794. #define UART0_B1T		*(volatile uint8_t  *)0x4006A024 // UART CEA709.1-B Beta1 Timer

  1795. #define UART0_SDTH		*(volatile uint8_t  *)0x4006A025 // UART CEA709.1-B Secondary Delay Timer High

  1796. #define UART0_SDTL		*(volatile uint8_t  *)0x4006A026 // UART CEA709.1-B Secondary Delay Timer Low

  1797. #define UART0_PRE		*(volatile uint8_t  *)0x4006A027 // UART CEA709.1-B Preamble

  1798. #define UART0_TPL		*(volatile uint8_t  *)0x4006A028 // UART CEA709.1-B Transmit Packet Length

  1799. #define UART0_IE		*(volatile uint8_t  *)0x4006A029 // UART CEA709.1-B Interrupt Enable Register

  1800. #define UART0_WB		*(volatile uint8_t  *)0x4006A02A // UART CEA709.1-B WBASE

  1801. #define UART0_S3		*(volatile uint8_t  *)0x4006A02B // UART CEA709.1-B Status Register

  1802. #define UART0_S4		*(volatile uint8_t  *)0x4006A02C // UART CEA709.1-B Status Register

  1803. #define UART0_RPL		*(volatile uint8_t  *)0x4006A02D // UART CEA709.1-B Received Packet Length

  1804. #define UART0_RPREL		*(volatile uint8_t  *)0x4006A02E // UART CEA709.1-B Received Preamble Length

  1805. #define UART0_CPW		*(volatile uint8_t  *)0x4006A02F // UART CEA709.1-B Collision Pulse Width

  1806. #define UART0_RIDT		*(volatile uint8_t  *)0x4006A030 // UART CEA709.1-B Receive Indeterminate Time

  1807. #define UART0_TIDT		*(volatile uint8_t  *)0x4006A031 // UART CEA709.1-B Transmit Indeterminate Time

  1808. #define UART1_BDH		*(volatile uint8_t  *)0x4006B000 // UART Baud Rate Registers: High

  1809. #define UART1_BDL		*(volatile uint8_t  *)0x4006B001 // UART Baud Rate Registers: Low

  1810. #define UART1_C1		*(volatile uint8_t  *)0x4006B002 // UART Control Register 1

  1811. #define UART1_C2		*(volatile uint8_t  *)0x4006B003 // UART Control Register 2

  1812. #define UART1_S1		*(volatile uint8_t  *)0x4006B004 // UART Status Register 1

  1813. #define UART1_S2		*(volatile uint8_t  *)0x4006B005 // UART Status Register 2

  1814. #define UART1_C3		*(volatile uint8_t  *)0x4006B006 // UART Control Register 3

  1815. #define UART1_D			*(volatile uint8_t  *)0x4006B007 // UART Data Register

  1816. #define UART1_MA1		*(volatile uint8_t  *)0x4006B008 // UART Match Address Registers 1

  1817. #define UART1_MA2		*(volatile uint8_t  *)0x4006B009 // UART Match Address Registers 2

  1818. #define UART1_C4		*(volatile uint8_t  *)0x4006B00A // UART Control Register 4

  1819. #define UART1_C5		*(volatile uint8_t  *)0x4006B00B // UART Control Register 5

  1820. #define UART1_ED		*(volatile uint8_t  *)0x4006B00C // UART Extended Data Register

  1821. #define UART1_MODEM		*(volatile uint8_t  *)0x4006B00D // UART Modem Register

  1822. #define UART1_IR		*(volatile uint8_t  *)0x4006B00E // UART Infrared Register

  1823. #define UART1_PFIFO		*(volatile uint8_t  *)0x4006B010 // UART FIFO Parameters

  1824. #define UART1_CFIFO		*(volatile uint8_t  *)0x4006B011 // UART FIFO Control Register

  1825. #define UART1_SFIFO		*(volatile uint8_t  *)0x4006B012 // UART FIFO Status Register

  1826. #define UART1_TWFIFO		*(volatile uint8_t  *)0x4006B013 // UART FIFO Transmit Watermark

  1827. #define UART1_TCFIFO		*(volatile uint8_t  *)0x4006B014 // UART FIFO Transmit Count

  1828. #define UART1_RWFIFO		*(volatile uint8_t  *)0x4006B015 // UART FIFO Receive Watermark

  1829. #define UART1_RCFIFO		*(volatile uint8_t  *)0x4006B016 // UART FIFO Receive Count

  1830. #define UART1_C7816		*(volatile uint8_t  *)0x4006B018 // UART 7816 Control Register

  1831. #define UART1_IE7816		*(volatile uint8_t  *)0x4006B019 // UART 7816 Interrupt Enable Register

  1832. #define UART1_IS7816		*(volatile uint8_t  *)0x4006B01A // UART 7816 Interrupt Status Register

  1833. #define UART1_WP7816T0		*(volatile uint8_t  *)0x4006B01B // UART 7816 Wait Parameter Register

  1834. #define UART1_WP7816T1		*(volatile uint8_t  *)0x4006B01B // UART 7816 Wait Parameter Register

  1835. #define UART1_WN7816		*(volatile uint8_t  *)0x4006B01C // UART 7816 Wait N Register

  1836. #define UART1_WF7816		*(volatile uint8_t  *)0x4006B01D // UART 7816 Wait FD Register

  1837. #define UART1_ET7816		*(volatile uint8_t  *)0x4006B01E // UART 7816 Error Threshold Register

  1838. #define UART1_TL7816		*(volatile uint8_t  *)0x4006B01F // UART 7816 Transmit Length Register

  1839. #define UART1_C6		*(volatile uint8_t  *)0x4006B021 // UART CEA709.1-B Control Register 6

  1840. #define UART1_PCTH		*(volatile uint8_t  *)0x4006B022 // UART CEA709.1-B Packet Cycle Time Counter High

  1841. #define UART1_PCTL		*(volatile uint8_t  *)0x4006B023 // UART CEA709.1-B Packet Cycle Time Counter Low

  1842. #define UART1_B1T		*(volatile uint8_t  *)0x4006B024 // UART CEA709.1-B Beta1 Timer

  1843. #define UART1_SDTH		*(volatile uint8_t  *)0x4006B025 // UART CEA709.1-B Secondary Delay Timer High

  1844. #define UART1_SDTL		*(volatile uint8_t  *)0x4006B026 // UART CEA709.1-B Secondary Delay Timer Low

  1845. #define UART1_PRE		*(volatile uint8_t  *)0x4006B027 // UART CEA709.1-B Preamble

  1846. #define UART1_TPL		*(volatile uint8_t  *)0x4006B028 // UART CEA709.1-B Transmit Packet Length

  1847. #define UART1_IE		*(volatile uint8_t  *)0x4006B029 // UART CEA709.1-B Interrupt Enable Register

  1848. #define UART1_WB		*(volatile uint8_t  *)0x4006B02A // UART CEA709.1-B WBASE

  1849. #define UART1_S3		*(volatile uint8_t  *)0x4006B02B // UART CEA709.1-B Status Register

  1850. #define UART1_S4		*(volatile uint8_t  *)0x4006B02C // UART CEA709.1-B Status Register

  1851. #define UART1_RPL		*(volatile uint8_t  *)0x4006B02D // UART CEA709.1-B Received Packet Length

  1852. #define UART1_RPREL		*(volatile uint8_t  *)0x4006B02E // UART CEA709.1-B Received Preamble Length

  1853. #define UART1_CPW		*(volatile uint8_t  *)0x4006B02F // UART CEA709.1-B Collision Pulse Width

  1854. #define UART1_RIDT		*(volatile uint8_t  *)0x4006B030 // UART CEA709.1-B Receive Indeterminate Time

  1855. #define UART1_TIDT		*(volatile uint8_t  *)0x4006B031 // UART CEA709.1-B Transmit Indeterminate Time

  1856. #define UART2_BDH		*(volatile uint8_t  *)0x4006C000 // UART Baud Rate Registers: High

  1857. #define UART2_BDL		*(volatile uint8_t  *)0x4006C001 // UART Baud Rate Registers: Low

  1858. #define UART2_C1		*(volatile uint8_t  *)0x4006C002 // UART Control Register 1

  1859. #define UART2_C2		*(volatile uint8_t  *)0x4006C003 // UART Control Register 2

  1860. #define UART2_S1		*(volatile uint8_t  *)0x4006C004 // UART Status Register 1

  1861. #define UART2_S2		*(volatile uint8_t  *)0x4006C005 // UART Status Register 2

  1862. #define UART2_C3		*(volatile uint8_t  *)0x4006C006 // UART Control Register 3

  1863. #define UART2_D			*(volatile uint8_t  *)0x4006C007 // UART Data Register

  1864. #define UART2_MA1		*(volatile uint8_t  *)0x4006C008 // UART Match Address Registers 1

  1865. #define UART2_MA2		*(volatile uint8_t  *)0x4006C009 // UART Match Address Registers 2

  1866. #define UART2_C4		*(volatile uint8_t  *)0x4006C00A // UART Control Register 4

  1867. #define UART2_C5		*(volatile uint8_t  *)0x4006C00B // UART Control Register 5

  1868. #define UART2_ED		*(volatile uint8_t  *)0x4006C00C // UART Extended Data Register

  1869. #define UART2_MODEM		*(volatile uint8_t  *)0x4006C00D // UART Modem Register

  1870. #define UART2_IR		*(volatile uint8_t  *)0x4006C00E // UART Infrared Register

  1871. #define UART2_PFIFO		*(volatile uint8_t  *)0x4006C010 // UART FIFO Parameters

  1872. #define UART2_CFIFO		*(volatile uint8_t  *)0x4006C011 // UART FIFO Control Register

  1873. #define UART2_SFIFO		*(volatile uint8_t  *)0x4006C012 // UART FIFO Status Register

  1874. #define UART2_TWFIFO		*(volatile uint8_t  *)0x4006C013 // UART FIFO Transmit Watermark

  1875. #define UART2_TCFIFO		*(volatile uint8_t  *)0x4006C014 // UART FIFO Transmit Count

  1876. #define UART2_RWFIFO		*(volatile uint8_t  *)0x4006C015 // UART FIFO Receive Watermark

  1877. #define UART2_RCFIFO		*(volatile uint8_t  *)0x4006C016 // UART FIFO Receive Count

  1878. #define UART2_C7816		*(volatile uint8_t  *)0x4006C018 // UART 7816 Control Register

  1879. #define UART2_IE7816		*(volatile uint8_t  *)0x4006C019 // UART 7816 Interrupt Enable Register

  1880. #define UART2_IS7816		*(volatile uint8_t  *)0x4006C01A // UART 7816 Interrupt Status Register

  1881. #define UART2_WP7816T0		*(volatile uint8_t  *)0x4006C01B // UART 7816 Wait Parameter Register

  1882. #define UART2_WP7816T1		*(volatile uint8_t  *)0x4006C01B // UART 7816 Wait Parameter Register

  1883. #define UART2_WN7816		*(volatile uint8_t  *)0x4006C01C // UART 7816 Wait N Register

  1884. #define UART2_WF7816		*(volatile uint8_t  *)0x4006C01D // UART 7816 Wait FD Register

  1885. #define UART2_ET7816		*(volatile uint8_t  *)0x4006C01E // UART 7816 Error Threshold Register

  1886. #define UART2_TL7816		*(volatile uint8_t  *)0x4006C01F // UART 7816 Transmit Length Register

  1887. #define UART2_C6		*(volatile uint8_t  *)0x4006C021 // UART CEA709.1-B Control Register 6

  1888. #define UART2_PCTH		*(volatile uint8_t  *)0x4006C022 // UART CEA709.1-B Packet Cycle Time Counter High

  1889. #define UART2_PCTL		*(volatile uint8_t  *)0x4006C023 // UART CEA709.1-B Packet Cycle Time Counter Low

  1890. #define UART2_B1T		*(volatile uint8_t  *)0x4006C024 // UART CEA709.1-B Beta1 Timer

  1891. #define UART2_SDTH		*(volatile uint8_t  *)0x4006C025 // UART CEA709.1-B Secondary Delay Timer High

  1892. #define UART2_SDTL		*(volatile uint8_t  *)0x4006C026 // UART CEA709.1-B Secondary Delay Timer Low

  1893. #define UART2_PRE		*(volatile uint8_t  *)0x4006C027 // UART CEA709.1-B Preamble

  1894. #define UART2_TPL		*(volatile uint8_t  *)0x4006C028 // UART CEA709.1-B Transmit Packet Length

  1895. #define UART2_IE		*(volatile uint8_t  *)0x4006C029 // UART CEA709.1-B Interrupt Enable Register

  1896. #define UART2_WB		*(volatile uint8_t  *)0x4006C02A // UART CEA709.1-B WBASE

  1897. #define UART2_S3		*(volatile uint8_t  *)0x4006C02B // UART CEA709.1-B Status Register

  1898. #define UART2_S4		*(volatile uint8_t  *)0x4006C02C // UART CEA709.1-B Status Register

  1899. #define UART2_RPL		*(volatile uint8_t  *)0x4006C02D // UART CEA709.1-B Received Packet Length

  1900. #define UART2_RPREL		*(volatile uint8_t  *)0x4006C02E // UART CEA709.1-B Received Preamble Length

  1901. #define UART2_CPW		*(volatile uint8_t  *)0x4006C02F // UART CEA709.1-B Collision Pulse Width

  1902. #define UART2_RIDT		*(volatile uint8_t  *)0x4006C030 // UART CEA709.1-B Receive Indeterminate Time

  1903. #define UART2_TIDT		*(volatile uint8_t  *)0x4006C031 // UART CEA709.1-B Transmit Indeterminate Time

  1904. 

  1905. // Chapter 46: Synchronous Audio Interface (SAI)

  1906. #define I2S0_TCSR		*(volatile uint32_t *)0x4002F000 // SAI Transmit Control Register

  1907. #define I2S_TCSR_TE			(uint32_t)0x80000000	// Transmitter Enable

  1908. #define I2S_TCSR_STOPE			(uint32_t)0x40000000	// Transmitter Enable in Stop mode

  1909. #define I2S_TCSR_DBGE			(uint32_t)0x20000000	// Transmitter Enable in Debug mode

  1910. #define I2S_TCSR_BCE			(uint32_t)0x10000000	// Bit Clock Enable

  1911. #define I2S_TCSR_FR			(uint32_t)0x02000000	// FIFO Reset

  1912. #define I2S_TCSR_SR			(uint32_t)0x01000000	// Software Reset

  1913. #define I2S_TCSR_WSF			(uint32_t)0x00100000	// Word Start Flag

  1914. #define I2S_TCSR_SEF			(uint32_t)0x00080000	// Sync Error Flag

  1915. #define I2S_TCSR_FEF			(uint32_t)0x00040000	// FIFO Error Flag (underrun)

  1916. #define I2S_TCSR_FWF			(uint32_t)0x00020000	// FIFO Warning Flag (empty)

  1917. #define I2S_TCSR_FRF			(uint32_t)0x00010000	// FIFO Request Flag (Data Ready)

  1918. #define I2S_TCSR_WSIE			(uint32_t)0x00001000	// Word Start Interrupt Enable

  1919. #define I2S_TCSR_SEIE			(uint32_t)0x00000800	// Sync Error Interrupt Enable

  1920. #define I2S_TCSR_FEIE			(uint32_t)0x00000400	// FIFO Error Interrupt Enable

  1921. #define I2S_TCSR_FWIE			(uint32_t)0x00000200	// FIFO Warning Interrupt Enable

  1922. #define I2S_TCSR_FRIE			(uint32_t)0x00000100	// FIFO Request Interrupt Enable

  1923. #define I2S_TCSR_FWDE			(uint32_t)0x00000002	// FIFO Warning DMA Enable

  1924. #define I2S_TCSR_FRDE			(uint32_t)0x00000001	// FIFO Request DMA Enable

  1925. #define I2S0_TCR1		*(volatile uint32_t *)0x4002F004 // SAI Transmit Configuration 1 Register

  1926. #define I2S_TCR1_TFW(n)			((uint32_t)n & 0x03)	      // Transmit FIFO watermark

  1927. #define I2S0_TCR2		*(volatile uint32_t *)0x4002F008 // SAI Transmit Configuration 2 Register

  1928. #define I2S_TCR2_DIV(n)			((uint32_t)n & 0xff)	      // Bit clock divide by (DIV+1)*2

  1929. #define I2S_TCR2_BCD			((uint32_t)1<<24)	      // Bit clock direction

  1930. #define I2S_TCR2_BCP			((uint32_t)1<<25)	      // Bit clock polarity

  1931. #define I2S_TCR2_MSEL(n)		((uint32_t)(n & 3)<<26)	      // MCLK select, 0=bus clock, 1=I2S0_MCLK

  1932. #define I2S_TCR2_BCI			((uint32_t)1<<28)	      // Bit clock input

  1933. #define I2S_TCR2_BCS			((uint32_t)1<<29)	      // Bit clock swap

  1934. #define I2S_TCR2_SYNC(n)		((uint32_t)(n & 3)<<30)	      // 0=async 1=sync with receiver

  1935. #define I2S0_TCR3		*(volatile uint32_t *)0x4002F00C // SAI Transmit Configuration 3 Register

  1936. #define I2S_TCR3_WDFL(n)		((uint32_t)n & 0x0f)	      // word flag configuration

  1937. #define I2S_TCR3_TCE			((uint32_t)0x10000)	      // transmit channel enable

  1938. #define I2S0_TCR4		*(volatile uint32_t *)0x4002F010 // SAI Transmit Configuration 4 Register

  1939. #define I2S_TCR4_FSD			((uint32_t)1)		      // Frame Sync Direction

  1940. #define I2S_TCR4_FSP			((uint32_t)2)		      // Frame Sync Polarity

  1941. #define I2S_TCR4_FSE			((uint32_t)8)		      // Frame Sync Early

  1942. #define I2S_TCR4_MF			((uint32_t)0x10)	      // MSB First

  1943. #define I2S_TCR4_SYWD(n)		((uint32_t)(n & 0x1f)<<8)     // Sync Width

  1944. #define I2S_TCR4_FRSZ(n)		((uint32_t)(n & 0x0f)<<16)    // Frame Size

  1945. #define I2S0_TCR5		*(volatile uint32_t *)0x4002F014 // SAI Transmit Configuration 5 Register

  1946. #define I2S_TCR5_FBT(n)			((uint32_t)(n & 0x1f)<<8)     // First Bit Shifted

  1947. #define I2S_TCR5_W0W(n)			((uint32_t)(n & 0x1f)<<16)    // Word 0 Width

  1948. #define I2S_TCR5_WNW(n)			((uint32_t)(n & 0x1f)<<24)    // Word N Width

  1949. #define I2S0_TDR0		*(volatile uint32_t *)0x4002F020 // SAI Transmit Data Register

  1950. #define I2S0_TDR1		*(volatile uint32_t *)0x4002F024 // SAI Transmit Data Register

  1951. #define I2S0_TFR0		*(volatile uint32_t *)0x4002F040 // SAI Transmit FIFO Register

  1952. #define I2S0_TFR1		*(volatile uint32_t *)0x4002F044 // SAI Transmit FIFO Register

  1953. #define I2S_TFR_RFP(n)			((uint32_t)n & 7)	      // read FIFO pointer

  1954. #define I2S_TFR_WFP(n)			((uint32_t)(n & 7)<<16)	      // write FIFO pointer

  1955. #define I2S0_TMR		*(volatile uint32_t *)0x4002F060 // SAI Transmit Mask Register

  1956. #define I2S_TMR_TWM(n)			((uint32_t)n & 0xFFFFFFFF)

  1957. #define I2S0_RCSR		*(volatile uint32_t *)0x4002F080 // SAI Receive Control Register

  1958. #define I2S_RCSR_RE			(uint32_t)0x80000000	// Receiver Enable

  1959. #define I2S_RCSR_STOPE			(uint32_t)0x40000000	// Receiver Enable in Stop mode

  1960. #define I2S_RCSR_DBGE			(uint32_t)0x20000000	// Receiver Enable in Debug mode

  1961. #define I2S_RCSR_BCE			(uint32_t)0x10000000	// Bit Clock Enable

  1962. #define I2S_RCSR_FR			(uint32_t)0x02000000	// FIFO Reset

  1963. #define I2S_RCSR_SR			(uint32_t)0x01000000	// Software Reset

  1964. #define I2S_RCSR_WSF			(uint32_t)0x00100000	// Word Start Flag

  1965. #define I2S_RCSR_SEF			(uint32_t)0x00080000	// Sync Error Flag

  1966. #define I2S_RCSR_FEF			(uint32_t)0x00040000	// FIFO Error Flag (underrun)

  1967. #define I2S_RCSR_FWF			(uint32_t)0x00020000	// FIFO Warning Flag (empty)

  1968. #define I2S_RCSR_FRF			(uint32_t)0x00010000	// FIFO Request Flag (Data Ready)

  1969. #define I2S_RCSR_WSIE			(uint32_t)0x00001000	// Word Start Interrupt Enable

  1970. #define I2S_RCSR_SEIE			(uint32_t)0x00000800	// Sync Error Interrupt Enable

  1971. #define I2S_RCSR_FEIE			(uint32_t)0x00000400	// FIFO Error Interrupt Enable

  1972. #define I2S_RCSR_FWIE			(uint32_t)0x00000200	// FIFO Warning Interrupt Enable

  1973. #define I2S_RCSR_FRIE			(uint32_t)0x00000100	// FIFO Request Interrupt Enable

  1974. #define I2S_RCSR_FWDE			(uint32_t)0x00000002	// FIFO Warning DMA Enable

  1975. #define I2S_RCSR_FRDE			(uint32_t)0x00000001	// FIFO Request DMA Enable

  1976. #define I2S0_RCR1		*(volatile uint32_t *)0x4002F084 // SAI Receive Configuration 1 Register

  1977. #define I2S_RCR1_RFW(n)			((uint32_t)n & 0x03)	      // Receive FIFO watermark

  1978. #define I2S0_RCR2		*(volatile uint32_t *)0x4002F088 // SAI Receive Configuration 2 Register

  1979. #define I2S_RCR2_DIV(n)			((uint32_t)n & 0xff)	      // Bit clock divide by (DIV+1)*2

  1980. #define I2S_RCR2_BCD			((uint32_t)1<<24)	      // Bit clock direction

  1981. #define I2S_RCR2_BCP			((uint32_t)1<<25)	      // Bit clock polarity

  1982. #define I2S_RCR2_MSEL(n)		((uint32_t)(n & 3)<<26)	      // MCLK select, 0=bus clock, 1=I2S0_MCLK

  1983. #define I2S_RCR2_BCI			((uint32_t)1<<28)	      // Bit clock input

  1984. #define I2S_RCR2_BCS			((uint32_t)1<<29)	      // Bit clock swap

  1985. #define I2S_RCR2_SYNC(n)		((uint32_t)(n & 3)<<30)	      // 0=async 1=sync with receiver

  1986. #define I2S0_RCR3		*(volatile uint32_t *)0x4002F08C // SAI Receive Configuration 3 Register

  1987. #define I2S_RCR3_WDFL(n)		((uint32_t)n & 0x0f)	      // word flag configuration

  1988. #define I2S_RCR3_RCE			((uint32_t)0x10000)	      // receive channel enable

  1989. #define I2S0_RCR4		*(volatile uint32_t *)0x4002F090 // SAI Receive Configuration 4 Register

  1990. #define I2S_RCR4_FSD			((uint32_t)1)		      // Frame Sync Direction

  1991. #define I2S_RCR4_FSP			((uint32_t)2)		      // Frame Sync Polarity

  1992. #define I2S_RCR4_FSE			((uint32_t)8)		      // Frame Sync Early

  1993. #define I2S_RCR4_MF			((uint32_t)0x10)	      // MSB First

  1994. #define I2S_RCR4_SYWD(n)		((uint32_t)(n & 0x1f)<<8)     // Sync Width

  1995. #define I2S_RCR4_FRSZ(n)		((uint32_t)(n & 0x0f)<<16)    // Frame Size

  1996. #define I2S0_RCR5		*(volatile uint32_t *)0x4002F094 // SAI Receive Configuration 5 Register

  1997. #define I2S_RCR5_FBT(n)			((uint32_t)(n & 0x1f)<<8)     // First Bit Shifted

  1998. #define I2S_RCR5_W0W(n)			((uint32_t)(n & 0x1f)<<16)    // Word 0 Width

  1999. #define I2S_RCR5_WNW(n)			((uint32_t)(n & 0x1f)<<24)    // Word N Width

  2000. #define I2S0_RDR0		*(volatile uint32_t *)0x4002F0A0 // SAI Receive Data Register

  2001. #define I2S0_RDR1		*(volatile uint32_t *)0x4002F0A4 // SAI Receive Data Register

  2002. #define I2S0_RFR0		*(volatile uint32_t *)0x4002F0C0 // SAI Receive FIFO Register

  2003. #define I2S0_RFR1		*(volatile uint32_t *)0x4002F0C4 // SAI Receive FIFO Register

  2004. #define I2S_RFR_RFP(n)			((uint32_t)n & 7)	      // read FIFO pointer

  2005. #define I2S_RFR_WFP(n)			((uint32_t)(n & 7)<<16)	      // write FIFO pointer

  2006. #define I2S0_RMR		*(volatile uint32_t *)0x4002F0E0 // SAI Receive Mask Register

  2007. #define I2S_RMR_RWM(n)			((uint32_t)n & 0xFFFFFFFF)

  2008. #define I2S0_MCR		*(volatile uint32_t *)0x4002F100 // SAI MCLK Control Register

  2009. #define I2S_MCR_DUF			((uint32_t)1<<31)	      // Divider Update Flag

  2010. #define I2S_MCR_MOE			((uint32_t)1<<30)	      // MCLK Output Enable

  2011. #define I2S_MCR_MICS(n)			((uint32_t)(n & 3)<<24)	      // MCLK Input Clock Select

  2012. #define I2S0_MDR		*(volatile uint32_t *)0x4002F104 // SAI MCLK Divide Register

  2013. #define I2S_MDR_FRACT(n)		((uint32_t)(n & 0xff)<<12)    // MCLK Fraction

  2014. #define I2S_MDR_DIVIDE(n)		((uint32_t)(n & 0xfff))	      // MCLK Divide

  2015. 

  2016. // Chapter 47: General-Purpose Input/Output (GPIO)

  2017. #define GPIOA_PDOR		*(volatile uint32_t *)0x400FF000 // Port Data Output Register

  2018. #define GPIOA_PSOR		*(volatile uint32_t *)0x400FF004 // Port Set Output Register

  2019. #define GPIOA_PCOR		*(volatile uint32_t *)0x400FF008 // Port Clear Output Register

  2020. #define GPIOA_PTOR		*(volatile uint32_t *)0x400FF00C // Port Toggle Output Register

  2021. #define GPIOA_PDIR		*(volatile uint32_t *)0x400FF010 // Port Data Input Register

  2022. #define GPIOA_PDDR		*(volatile uint32_t *)0x400FF014 // Port Data Direction Register

  2023. #define GPIOB_PDOR		*(volatile uint32_t *)0x400FF040 // Port Data Output Register

  2024. #define GPIOB_PSOR		*(volatile uint32_t *)0x400FF044 // Port Set Output Register

  2025. #define GPIOB_PCOR		*(volatile uint32_t *)0x400FF048 // Port Clear Output Register

  2026. #define GPIOB_PTOR		*(volatile uint32_t *)0x400FF04C // Port Toggle Output Register

  2027. #define GPIOB_PDIR		*(volatile uint32_t *)0x400FF050 // Port Data Input Register

  2028. #define GPIOB_PDDR		*(volatile uint32_t *)0x400FF054 // Port Data Direction Register

  2029. #define GPIOC_PDOR		*(volatile uint32_t *)0x400FF080 // Port Data Output Register

  2030. #define GPIOC_PSOR		*(volatile uint32_t *)0x400FF084 // Port Set Output Register

  2031. #define GPIOC_PCOR		*(volatile uint32_t *)0x400FF088 // Port Clear Output Register

  2032. #define GPIOC_PTOR		*(volatile uint32_t *)0x400FF08C // Port Toggle Output Register

  2033. #define GPIOC_PDIR		*(volatile uint32_t *)0x400FF090 // Port Data Input Register

  2034. #define GPIOC_PDDR		*(volatile uint32_t *)0x400FF094 // Port Data Direction Register

  2035. #define GPIOD_PDOR		*(volatile uint32_t *)0x400FF0C0 // Port Data Output Register

  2036. #define GPIOD_PSOR		*(volatile uint32_t *)0x400FF0C4 // Port Set Output Register

  2037. #define GPIOD_PCOR		*(volatile uint32_t *)0x400FF0C8 // Port Clear Output Register

  2038. #define GPIOD_PTOR		*(volatile uint32_t *)0x400FF0CC // Port Toggle Output Register

  2039. #define GPIOD_PDIR		*(volatile uint32_t *)0x400FF0D0 // Port Data Input Register

  2040. #define GPIOD_PDDR		*(volatile uint32_t *)0x400FF0D4 // Port Data Direction Register

  2041. #define GPIOE_PDOR		*(volatile uint32_t *)0x400FF100 // Port Data Output Register

  2042. #define GPIOE_PSOR		*(volatile uint32_t *)0x400FF104 // Port Set Output Register

  2043. #define GPIOE_PCOR		*(volatile uint32_t *)0x400FF108 // Port Clear Output Register

  2044. #define GPIOE_PTOR		*(volatile uint32_t *)0x400FF10C // Port Toggle Output Register

  2045. #define GPIOE_PDIR		*(volatile uint32_t *)0x400FF110 // Port Data Input Register

  2046. #define GPIOE_PDDR		*(volatile uint32_t *)0x400FF114 // Port Data Direction Register

  2047. 

  2048. // Chapter 48: Touch sense input (TSI)

  2049. #define TSI0_GENCS		*(volatile uint32_t *)0x40045000 // General Control and Status Register

  2050. #define TSI_GENCS_LPCLKS		(uint32_t)0x10000000		// 

  2051. #define TSI_GENCS_LPSCNITV(n)		(((n) & 15) << 24)		// 

  2052. #define TSI_GENCS_NSCN(n)		(((n) & 31) << 19)		// 

  2053. #define TSI_GENCS_PS(n)			(((n) & 7) << 16)		// 

  2054. #define TSI_GENCS_EOSF			(uint32_t)0x00008000		// 

  2055. #define TSI_GENCS_OUTRGF		(uint32_t)0x00004000		// 

  2056. #define TSI_GENCS_EXTERF		(uint32_t)0x00002000		// 

  2057. #define TSI_GENCS_OVRF			(uint32_t)0x00001000		// 

  2058. #define TSI_GENCS_SCNIP			(uint32_t)0x00000200		// 

  2059. #define TSI_GENCS_SWTS			(uint32_t)0x00000100		// 

  2060. #define TSI_GENCS_TSIEN			(uint32_t)0x00000080		// 

  2061. #define TSI_GENCS_TSIIE			(uint32_t)0x00000040		// 

  2062. #define TSI_GENCS_ERIE			(uint32_t)0x00000020		// 

  2063. #define TSI_GENCS_ESOR			(uint32_t)0x00000010		// 

  2064. #define TSI_GENCS_STM			(uint32_t)0x00000002		// 

  2065. #define TSI_GENCS_STPE			(uint32_t)0x00000001		// 

  2066. #define TSI0_SCANC		*(volatile uint32_t *)0x40045004 // SCAN Control Register

  2067. #define TSI_SCANC_REFCHRG(n)		(((n) & 15) << 24)		// 

  2068. #define TSI_SCANC_EXTCHRG(n)		(((n) & 7) << 16)		// 

  2069. #define TSI_SCANC_SMOD(n)		(((n) & 255) << 8)		// 

  2070. #define TSI_SCANC_AMCLKS(n)		(((n) & 3) << 3)		// 

  2071. #define TSI_SCANC_AMPSC(n)		(((n) & 7) << 0)		// 

  2072. #define TSI0_PEN		*(volatile uint32_t *)0x40045008 // Pin Enable Register

  2073. #define TSI0_WUCNTR		*(volatile uint32_t *)0x4004500C // Wake-Up Channel Counter Register

  2074. #define TSI0_CNTR1		*(volatile uint32_t *)0x40045100 // Counter Register

  2075. #define TSI0_CNTR3		*(volatile uint32_t *)0x40045104 // Counter Register

  2076. #define TSI0_CNTR5		*(volatile uint32_t *)0x40045108 // Counter Register

  2077. #define TSI0_CNTR7		*(volatile uint32_t *)0x4004510C // Counter Register

  2078. #define TSI0_CNTR9		*(volatile uint32_t *)0x40045110 // Counter Register

  2079. #define TSI0_CNTR11		*(volatile uint32_t *)0x40045114 // Counter Register

  2080. #define TSI0_CNTR13		*(volatile uint32_t *)0x40045118 // Counter Register

  2081. #define TSI0_CNTR15		*(volatile uint32_t *)0x4004511C // Counter Register

  2082. #define TSI0_THRESHOLD		*(volatile uint32_t *)0x40045120 // Low Power Channel Threshold Register

  2083. 

  2084. // Nested Vectored Interrupt Controller, Table 3-4 & ARMv7 ref, appendix B3.4 (page 750)

  2085. #define NVIC_ENABLE_IRQ(n)	(*((volatile uint32_t *)0xE000E100 + (n >> 5)) = (1 << (n & 31)))

  2086. #define NVIC_DISABLE_IRQ(n)	(*((volatile uint32_t *)0xE000E180 + (n >> 5)) = (1 << (n & 31)))

  2087. #define NVIC_SET_PENDING(n)	(*((volatile uint32_t *)0xE000E200 + (n >> 5)) = (1 << (n & 31)))

  2088. #define NVIC_CLEAR_PENDING(n)	(*((volatile uint32_t *)0xE000E280 + (n >> 5)) = (1 << (n & 31)))

  2089. 

  2090. #define NVIC_ISER0		*(volatile uint32_t *)0xE000E100

  2091. #define NVIC_ISER1		*(volatile uint32_t *)0xE000E104

  2092. #define NVIC_ICER0		*(volatile uint32_t *)0xE000E180

  2093. #define NVIC_ICER1		*(volatile uint32_t *)0xE000E184

  2094. 

  2095. // 0 = highest priority

  2096. // Cortex-M4: 0,16,32,48,64,80,96,112,128,144,160,176,192,208,224,240

  2097. // Cortex-M0: 0,64,128,192

  2098. #define NVIC_SET_PRIORITY(irqnum, priority)  (*((volatile uint8_t *)0xE000E400 + (irqnum)) = (uint8_t)(priority))

  2099. #define NVIC_GET_PRIORITY(irqnum) (*((uint8_t *)0xE000E400 + (irqnum)))

  2100. 

  2101. #if defined(__MK20DX128__)

  2102. #define IRQ_DMA_CH0		0

  2103. #define IRQ_DMA_CH1		1

  2104. #define IRQ_DMA_CH2		2

  2105. #define IRQ_DMA_CH3		3

  2106. #define IRQ_DMA_ERROR		4

  2107. #define IRQ_FTFL_COMPLETE	6

  2108. #define IRQ_FTFL_COLLISION	7

  2109. #define IRQ_LOW_VOLTAGE		8

  2110. #define IRQ_LLWU		9

  2111. #define IRQ_WDOG		10

  2112. #define IRQ_I2C0		11

  2113. #define IRQ_SPI0		12

  2114. #define IRQ_I2S0_TX		13

  2115. #define IRQ_I2S0_RX		14

  2116. #define IRQ_UART0_LON		15

  2117. #define IRQ_UART0_STATUS	16

  2118. #define IRQ_UART0_ERROR		17

  2119. #define IRQ_UART1_STATUS	18

  2120. #define IRQ_UART1_ERROR		19

  2121. #define IRQ_UART2_STATUS	20

  2122. #define IRQ_UART2_ERROR		21

  2123. #define IRQ_ADC0		22

  2124. #define IRQ_CMP0		23

  2125. #define IRQ_CMP1		24

  2126. #define IRQ_FTM0		25

  2127. #define IRQ_FTM1		26

  2128. #define IRQ_CMT			27

  2129. #define IRQ_RTC_ALARM		28

  2130. #define IRQ_RTC_SECOND		29

  2131. #define IRQ_PIT_CH0		30

  2132. #define IRQ_PIT_CH1		31

  2133. #define IRQ_PIT_CH2		32

  2134. #define IRQ_PIT_CH3		33

  2135. #define IRQ_PDB			34

  2136. #define IRQ_USBOTG		35

  2137. #define IRQ_USBDCD		36

  2138. #define IRQ_TSI			37

  2139. #define IRQ_MCG			38

  2140. #define IRQ_LPTMR		39

  2141. #define IRQ_PORTA		40

  2142. #define IRQ_PORTB		41

  2143. #define IRQ_PORTC		42

  2144. #define IRQ_PORTD		43

  2145. #define IRQ_PORTE		44

  2146. #define IRQ_SOFTWARE		45

  2147. #define NVIC_NUM_INTERRUPTS	46

  2148. 

  2149. #elif defined(__MK20DX256__)

  2150. #define IRQ_DMA_CH0		0

  2151. #define IRQ_DMA_CH1		1

  2152. #define IRQ_DMA_CH2		2

  2153. #define IRQ_DMA_CH3		3

  2154. #define IRQ_DMA_CH4		4

  2155. #define IRQ_DMA_CH5		5

  2156. #define IRQ_DMA_CH6		6

  2157. #define IRQ_DMA_CH7		7

  2158. #define IRQ_DMA_CH8		8

  2159. #define IRQ_DMA_CH9		9

  2160. #define IRQ_DMA_CH10		10

  2161. #define IRQ_DMA_CH11		11

  2162. #define IRQ_DMA_CH12		12

  2163. #define IRQ_DMA_CH13		13

  2164. #define IRQ_DMA_CH14		14

  2165. #define IRQ_DMA_CH15		15

  2166. #define IRQ_DMA_ERROR		16

  2167. #define IRQ_FTFL_COMPLETE	18

  2168. #define IRQ_FTFL_COLLISION	19

  2169. #define IRQ_LOW_VOLTAGE		20

  2170. #define IRQ_LLWU		21

  2171. #define IRQ_WDOG		22

  2172. #define IRQ_I2C0		24

  2173. #define IRQ_I2C1		25

  2174. #define IRQ_SPI0		26

  2175. #define IRQ_SPI1		27

  2176. #define IRQ_CAN_MESSAGE		29

  2177. #define IRQ_CAN_BUS_OFF		30

  2178. #define IRQ_CAN_ERROR		31

  2179. #define IRQ_CAN_TX_WARN		32

  2180. #define IRQ_CAN_RX_WARN		33

  2181. #define IRQ_CAN_WAKEUP		34

  2182. #define IRQ_I2S0_TX		35

  2183. #define IRQ_I2S0_RX		36

  2184. #define IRQ_UART0_LON		44

  2185. #define IRQ_UART0_STATUS	45

  2186. #define IRQ_UART0_ERROR		46

  2187. #define IRQ_UART1_STATUS	47

  2188. #define IRQ_UART1_ERROR		48

  2189. #define IRQ_UART2_STATUS	49

  2190. #define IRQ_UART2_ERROR		50

  2191. #define IRQ_ADC0		57

  2192. #define IRQ_ADC1		58

  2193. #define IRQ_CMP0		59

  2194. #define IRQ_CMP1		60

  2195. #define IRQ_CMP2		61

  2196. #define IRQ_FTM0		62

  2197. #define IRQ_FTM1		63

  2198. #define IRQ_FTM2		64

  2199. #define IRQ_CMT			65

  2200. #define IRQ_RTC_ALARM		66

  2201. #define IRQ_RTC_SECOND		67

  2202. #define IRQ_PIT_CH0		68

  2203. #define IRQ_PIT_CH1		69

  2204. #define IRQ_PIT_CH2		70

  2205. #define IRQ_PIT_CH3		71

  2206. #define IRQ_PDB			72

  2207. #define IRQ_USBOTG		73

  2208. #define IRQ_USBDCD		74

  2209. #define IRQ_DAC0		81

  2210. #define IRQ_TSI			83

  2211. #define IRQ_MCG			84

  2212. #define IRQ_LPTMR		85

  2213. #define IRQ_PORTA		87

  2214. #define IRQ_PORTB		88

  2215. #define IRQ_PORTC		89

  2216. #define IRQ_PORTD		90

  2217. #define IRQ_PORTE		91

  2218. #define IRQ_SOFTWARE		94

  2219. #define NVIC_NUM_INTERRUPTS	95

  2220. 

  2221. #endif

  2222. 

  2223. 

  2224. 

  2225. 

  2226. 

  2227. #define __disable_irq() asm volatile("CPSID i");

  2228. #define __enable_irq()	asm volatile("CPSIE i");

  2229. 

  2230. // System Control Space (SCS), ARMv7 ref manual, B3.2, page 708

  2231. #define SCB_CPUID		*(const	   uint32_t *)0xE000ED00 // CPUID Base Register

  2232. #define SCB_ICSR		*(volatile uint32_t *)0xE000ED04 // Interrupt Control and State

  2233. #define SCB_ICSR_PENDSTSET		(uint32_t)0x04000000

  2234. #define SCB_VTOR		*(volatile uint32_t *)0xE000ED08 // Vector Table Offset

  2235. #define SCB_AIRCR		*(volatile uint32_t *)0xE000ED0C // Application Interrupt and Reset Control

  2236. #define SCB_SCR			*(volatile uint32_t *)0xE000ED10 // System Control Register

  2237. #define SCB_CCR			*(volatile uint32_t *)0xE000ED14 // Configuration and Control

  2238. #define SCB_SHPR1		*(volatile uint32_t *)0xE000ED18 // System Handler Priority Register 1

  2239. #define SCB_SHPR2		*(volatile uint32_t *)0xE000ED1C // System Handler Priority Register 2

  2240. #define SCB_SHPR3		*(volatile uint32_t *)0xE000ED20 // System Handler Priority Register 3

  2241. #define SCB_SHCSR		*(volatile uint32_t *)0xE000ED24 // System Handler Control and State

  2242. #define SCB_CFSR		*(volatile uint32_t *)0xE000ED28 // Configurable Fault Status Register

  2243. #define SCB_HFSR		*(volatile uint32_t *)0xE000ED2C // HardFault Status

  2244. #define SCB_DFSR		*(volatile uint32_t *)0xE000ED30 // Debug Fault Status

  2245. #define SCB_MMFAR		*(volatile uint32_t *)0xE000ED34 // MemManage Fault Address

  2246. 

  2247. #define SYST_CSR		*(volatile uint32_t *)0xE000E010 // SysTick Control and Status

  2248. #define SYST_CSR_COUNTFLAG		(uint32_t)0x00010000

  2249. #define SYST_CSR_CLKSOURCE		(uint32_t)0x00000004

  2250. #define SYST_CSR_TICKINT		(uint32_t)0x00000002

  2251. #define SYST_CSR_ENABLE			(uint32_t)0x00000001

  2252. #define SYST_RVR		*(volatile uint32_t *)0xE000E014 // SysTick Reload Value Register

  2253. #define SYST_CVR		*(volatile uint32_t *)0xE000E018 // SysTick Current Value Register

  2254. #define SYST_CALIB		*(const	   uint32_t *)0xE000E01C // SysTick Calibration Value

  2255. 

  2256. 

  2257. #define ARM_DEMCR		*(volatile uint32_t *)0xE000EDFC // Debug Exception and Monitor Control

  2258. #define ARM_DEMCR_TRCENA		(1 << 24)	 // Enable debugging & monitoring blocks

  2259. #define ARM_DWT_CTRL		*(volatile uint32_t *)0xE0001000 // DWT control register

  2260. #define ARM_DWT_CTRL_CYCCNTENA		(1 << 0)		// Enable cycle count

  2261. #define ARM_DWT_CYCCNT		*(volatile uint32_t *)0xE0001004 // Cycle count register

  2262. 

  2263. extern int nvic_execution_priority(void);

  2264. 

  2265. extern void nmi_isr(void);

  2266. extern void hard_fault_isr(void);

  2267. extern void memmanage_fault_isr(void);

  2268. extern void bus_fault_isr(void);

  2269. extern void usage_fault_isr(void);

  2270. extern void svcall_isr(void);

  2271. extern void debugmonitor_isr(void);

  2272. extern void pendablesrvreq_isr(void);

  2273. extern void systick_isr(void);

  2274. extern void dma_ch0_isr(void);

  2275. extern void dma_ch1_isr(void);

  2276. extern void dma_ch2_isr(void);

  2277. extern void dma_ch3_isr(void);

  2278. extern void dma_ch4_isr(void);

  2279. extern void dma_ch5_isr(void);

  2280. extern void dma_ch6_isr(void);

  2281. extern void dma_ch7_isr(void);

  2282. extern void dma_ch8_isr(void);

  2283. extern void dma_ch9_isr(void);

  2284. extern void dma_ch10_isr(void);

  2285. extern void dma_ch11_isr(void);

  2286. extern void dma_ch12_isr(void);

  2287. extern void dma_ch13_isr(void);

  2288. extern void dma_ch14_isr(void);

  2289. extern void dma_ch15_isr(void);

  2290. extern void dma_error_isr(void);

  2291. extern void mcm_isr(void);

  2292. extern void flash_cmd_isr(void);

  2293. extern void flash_error_isr(void);

  2294. extern void low_voltage_isr(void);

  2295. extern void wakeup_isr(void);

  2296. extern void watchdog_isr(void);

  2297. extern void i2c0_isr(void);

  2298. extern void i2c1_isr(void);

  2299. extern void i2c2_isr(void);

  2300. extern void spi0_isr(void);

  2301. extern void spi1_isr(void);

  2302. extern void spi2_isr(void);

  2303. extern void sdhc_isr(void);

  2304. extern void can0_message_isr(void);

  2305. extern void can0_bus_off_isr(void);

  2306. extern void can0_error_isr(void);

  2307. extern void can0_tx_warn_isr(void);

  2308. extern void can0_rx_warn_isr(void);

  2309. extern void can0_wakeup_isr(void);

  2310. extern void i2s0_tx_isr(void);

  2311. extern void i2s0_rx_isr(void);

  2312. extern void uart0_lon_isr(void);

  2313. extern void uart0_status_isr(void);

  2314. extern void uart0_error_isr(void);

  2315. extern void uart1_status_isr(void);

  2316. extern void uart1_error_isr(void);

  2317. extern void uart2_status_isr(void);

  2318. extern void uart2_error_isr(void);

  2319. extern void uart3_status_isr(void);

  2320. extern void uart3_error_isr(void);

  2321. extern void uart4_status_isr(void);

  2322. extern void uart4_error_isr(void);

  2323. extern void uart5_status_isr(void);

  2324. extern void uart5_error_isr(void);

  2325. extern void adc0_isr(void);

  2326. extern void adc1_isr(void);

  2327. extern void cmp0_isr(void);

  2328. extern void cmp1_isr(void);

  2329. extern void cmp2_isr(void);

  2330. extern void ftm0_isr(void);

  2331. extern void ftm1_isr(void);

  2332. extern void ftm2_isr(void);

  2333. extern void ftm3_isr(void);

  2334. extern void cmt_isr(void);

  2335. extern void rtc_alarm_isr(void);

  2336. extern void rtc_seconds_isr(void);

  2337. extern void pit0_isr(void);

  2338. extern void pit1_isr(void);

  2339. extern void pit2_isr(void);

  2340. extern void pit3_isr(void);

  2341. extern void pdb_isr(void);

  2342. extern void usb_isr(void);

  2343. extern void usb_charge_isr(void);

  2344. extern void dac0_isr(void);

  2345. extern void dac1_isr(void);

  2346. extern void tsi0_isr(void);

  2347. extern void mcg_isr(void);

  2348. extern void lptmr_isr(void);

  2349. extern void porta_isr(void);

  2350. extern void portb_isr(void);

  2351. extern void portc_isr(void);

  2352. extern void portd_isr(void);

  2353. extern void porte_isr(void);

  2354. extern void software_isr(void);

  2355. 

  2356. 

  2357. 

  2358. #ifdef __cplusplus

  2359. }

  2360. #endif

  2361. #endif