瀏覽代碼

.

teensy4-core
Frank Bösing 10 年之前
父節點
當前提交
763dba3dca
共有 1 個檔案被更改,包括 1 行新增3 行删除
  1. +1
    -3
      teensy3/mk20dx128.c

+ 1
- 3
teensy3/mk20dx128.c 查看文件

@@ -451,10 +451,8 @@ void ResetHandler(void)
// configure USB for 48 MHz clock
#if F_CPU == 144000000
SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(2); // USB = 144 MHz PLL / 3
#elif F_CPU == 120000000
SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC; // USB = 120 MHz PLL / 2.5
#else
SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1); // USB = 96 MHz PLL / 2
SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1); // USB = 96 MHz PLL / 2
#endif
// USB uses PLL clock, trace is CPU clock, CLKOUT=OSCERCLK0
SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL(6);

Loading…
取消
儲存