Frank Bösing
10 years ago
1 changed files with 1 additions and 3 deletions
+ 1
- 3
teensy3/mk20dx128.c
View File
| // configure USB for 48 MHz clock | // configure USB for 48 MHz clock | ||||
| #if F_CPU == 144000000 | #if F_CPU == 144000000 | ||||
| SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(2); // USB = 144 MHz PLL / 3 | SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(2); // USB = 144 MHz PLL / 3 | ||||
| #elif F_CPU == 120000000 | |||||
| SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC; // USB = 120 MHz PLL / 2.5 | |||||
| #else | #else | ||||
| SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1); // USB = 96 MHz PLL / 2 | |||||
| SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1); // USB = 96 MHz PLL / 2 | |||||
| #endif | #endif | ||||
| // USB uses PLL clock, trace is CPU clock, CLKOUT=OSCERCLK0 | // USB uses PLL clock, trace is CPU clock, CLKOUT=OSCERCLK0 | ||||
| SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL(6); | SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL(6); |
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