| @@ -37,7 +37,16 @@ | |||
| // The preferred way to set SPI speed is with SPI.beginTransaction() | |||
| #if F_BUS == 120000000 | |||
| #if F_BUS == 128000000 | |||
| #define HAS_SPIFIFO | |||
| #define SPI_CLOCK_24MHz (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0)) //(128 / 3) * ((1+0)/2) = 21.3MHz | |||
| #define SPI_CLOCK_16MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(2)) //(128 / 2) * ((1+0)/4) | |||
| #define SPI_CLOCK_12MHz (SPI_CTAR_PBR(1) | SPI_CTAR_BR(2)) //(128 / 3) * ((1+0)/4) = 10.6 MHz | |||
| #define SPI_CLOCK_8MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(6)) //(128 / 2) * ((1+0)/8) | |||
| #define SPI_CLOCK_6MHz (SPI_CTAR_PBR(1) | SPI_CTAR_BR(6)) //(128 / 3) * ((1+0)/8) = 5.3 MHz | |||
| #define SPI_CLOCK_4MHz (SPI_CTAR_PBR(3) | SPI_CTAR_BR(6)) //(128 / 5) * ((1+0)/8) = 3.2MHz | |||
| #elif F_BUS == 120000000 | |||
| #define HAS_SPIFIFO | |||
| #define SPI_CLOCK_24MHz (SPI_CTAR_PBR(3) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(120 / 5) * ((1+1)/2) | |||
| #define SPI_CLOCK_16MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(2)) //(120 / 2) * ((1+0)/4) = 15 MHz | |||
| @@ -40,8 +40,12 @@ static uint8_t analog_reference_internal = 0; | |||
| // the alternate clock is connected to OSCERCLK (16 MHz). | |||
| // datasheet says ADC clock should be 2 to 12 MHz for 16 bit mode | |||
| // datasheet says ADC clock should be 1 to 18 MHz for 8-12 bit mode | |||
| #if F_BUS == 120000000 | |||
| #if F_BUS == 128000000 | |||
| #define ADC_CFG1_16BIT ADC_CFG1_ADIV(3) + ADC_CFG1_ADICLK(1) // 8 MHz | |||
| #define ADC_CFG1_12BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 16 MHz | |||
| #define ADC_CFG1_10BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 16 MHz | |||
| #define ADC_CFG1_8BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 16 MHz | |||
| #elif F_BUS == 120000000 | |||
| #define ADC_CFG1_16BIT ADC_CFG1_ADIV(3) + ADC_CFG1_ADICLK(1) // 7.5 MHz | |||
| #define ADC_CFG1_12BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 15 MHz | |||
| #define ADC_CFG1_10BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 15 MHz | |||
| @@ -127,7 +131,7 @@ static uint8_t analog_reference_internal = 0; | |||
| #define ADC_CFG1_10BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz | |||
| #define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz | |||
| #else | |||
| #error "F_BUS must be 120, 108, 96, 90, 80, 72, 64, 60, 56, 54, 48, 40, 36, 24, 4 or 2 MHz" | |||
| #error "F_BUS must be 128, 120, 108, 96, 90, 80, 72, 64, 60, 56, 54, 48, 40, 36, 24, 4 or 2 MHz" | |||
| #endif | |||
| void analog_init(void) | |||
| @@ -2023,7 +2023,9 @@ uint32_t micros(void); | |||
| static inline void delayMicroseconds(uint32_t) __attribute__((always_inline, unused)); | |||
| static inline void delayMicroseconds(uint32_t usec) | |||
| { | |||
| #if F_CPU == 240000000 | |||
| #if F_CPU == 256000000 | |||
| uint32_t n = usec * 85; | |||
| #elif F_CPU == 240000000 | |||
| uint32_t n = usec * 80; | |||
| #elif F_CPU == 216000000 | |||
| uint32_t n = usec * 72; | |||
| @@ -761,8 +761,14 @@ enum IRQ_NUMBER_t { | |||
| #endif // end of board-specific definitions | |||
| #if (F_CPU == 240000000) | |||
| #if (F_CPU == 256000000) | |||
| #define F_PLL 256000000 | |||
| #ifndef F_BUS | |||
| #define F_BUS 64000000 | |||
| //#define F_BUS 128000000 // all the usual overclocking caveats apply... | |||
| #endif | |||
| #define F_MEM 32000000 | |||
| #elif (F_CPU == 240000000) | |||
| #define F_PLL 240000000 | |||
| #ifndef F_BUS | |||
| #define F_BUS 60000000 | |||
| @@ -841,7 +841,12 @@ void ResetHandler(void) | |||
| SMC_PMCTRL = SMC_PMCTRL_RUNM(3); // enter HSRUN mode | |||
| while (SMC_PMSTAT != SMC_PMSTAT_HSRUN) ; // wait for HSRUN | |||
| #endif | |||
| #if F_CPU == 240000000 | |||
| #if F_CPU == 256000000 | |||
| //See table in 27.4.6 MCG Control 6 Register (MCG_C6) | |||
| //16 -> Multiply factor 32. 32*8MHz =256MHz | |||
| MCG_C5 = MCG_C5_PRDIV0(0); | |||
| MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(16); | |||
| #elif F_CPU == 240000000 | |||
| MCG_C5 = MCG_C5_PRDIV0(0); | |||
| MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(14); | |||
| #elif F_CPU == 216000000 | |||
| @@ -900,7 +905,18 @@ void ResetHandler(void) | |||
| #endif | |||
| #endif | |||
| // now program the clock dividers | |||
| #if F_CPU == 240000000 | |||
| #if F_CPU == 256000000 | |||
| // config divisors: 256 MHz core, 64 MHz bus, 32 MHz flash, USB = IRC48M | |||
| // TODO: gradual ramp-up for HSRUN mode | |||
| #if F_BUS == 64000000 | |||
| SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(3) | SIM_CLKDIV1_OUTDIV4(7); | |||
| #elif F_BUS == 128000000 | |||
| SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(7); | |||
| #else | |||
| #error "This F_CPU & F_BUS combination is not supported" | |||
| #endif | |||
| SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(0); | |||
| #elif F_CPU == 240000000 | |||
| // config divisors: 240 MHz core, 60 MHz bus, 30 MHz flash, USB = 240 / 5 | |||
| // TODO: gradual ramp-up for HSRUN mode | |||
| #if F_BUS == 60000000 | |||
| @@ -921,7 +937,8 @@ void ResetHandler(void) | |||
| #elif F_BUS == 72000000 | |||
| SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2) | SIM_CLKDIV1_OUTDIV4(7); | |||
| #elif F_BUS == 108000000 | |||
| SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(7); | |||
| SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(7); | |||
| #else | |||
| #error "This F_CPU & F_BUS combination is not supported" | |||
| #endif | |||
| @@ -1046,7 +1063,7 @@ void ResetHandler(void) | |||
| SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV4(1); | |||
| #endif | |||
| #else | |||
| #error "Error, F_CPU must be 192, 180, 168, 144, 120, 96, 72, 48, 24, 16, 8, 4, or 2 MHz" | |||
| #error "Error, F_CPU must be 256, 240, 216, 192, 180, 168, 144, 120, 96, 72, 48, 24, 16, 8, 4, or 2 MHz" | |||
| #endif | |||
| #if F_CPU > 16000000 | |||
| @@ -1055,11 +1072,13 @@ void ResetHandler(void) | |||
| // wait for PLL clock to be used | |||
| while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(3)) ; | |||
| // now we're in PEE mode | |||
| // USB uses PLL clock, trace is CPU clock, CLKOUT=OSCERCLK0 | |||
| // trace is CPU clock, CLKOUT=OSCERCLK0 | |||
| #if defined(KINETISK) | |||
| #if F_CPU == 216000000 || F_CPU == 180000000 | |||
| #if F_CPU == 256000000 || F_CPU == 216000000 || F_CPU == 180000000 | |||
| // USB uses IRC48 | |||
| SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_IRC48SEL | SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL(6); | |||
| #else | |||
| // USB uses PLL clock | |||
| SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL(6); | |||
| #endif | |||
| #elif defined(KINETISL) | |||
| @@ -1128,6 +1147,7 @@ void ResetHandler(void) | |||
| startup_late_hook(); | |||
| main(); | |||
| while (1) ; | |||
| } | |||
| @@ -1259,7 +1279,11 @@ int kinetis_hsrun_disable(void) | |||
| // the peripheral speed (F_BUS). Serial1 & Serial2 baud | |||
| // rates will be impacted, but most other peripherals | |||
| // will continue functioning at the same speed. | |||
| #if F_CPU == 240000000 && F_BUS == 60000000 | |||
| #if F_CPU == 256000000 && F_BUS == 64000000 | |||
| SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 3, 1, 7); // TODO: TEST | |||
| #elif F_CPU == 256000000 && F_BUS == 128000000 | |||
| SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 1, 1, 7); // TODO: TEST | |||
| #elif F_CPU == 240000000 && F_BUS == 60000000 | |||
| SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 3, 1, 7); // ok | |||
| #elif F_CPU == 240000000 && F_BUS == 80000000 | |||
| SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(2, 2, 2, 8); // ok | |||
| @@ -1305,7 +1329,11 @@ int kinetis_hsrun_enable(void) | |||
| SMC_PMCTRL = SMC_PMCTRL_RUNM(3); | |||
| while (SMC_PMSTAT != SMC_PMSTAT_HSRUN) {;} // wait | |||
| // Then configure clock for full speed | |||
| #if F_CPU == 240000000 && F_BUS == 60000000 | |||
| #if F_CPU == 256000000 && F_BUS == 64000000 | |||
| SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 3, 0, 7); | |||
| #elif F_CPU == 256000000 && F_BUS == 128000000 | |||
| SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 1, 0, 7); | |||
| #elif F_CPU == 240000000 && F_BUS == 60000000 | |||
| SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 3, 0, 7); | |||
| #elif F_CPU == 240000000 && F_BUS == 80000000 | |||
| SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 2, 0, 7); | |||
| @@ -456,7 +456,10 @@ extern void usb_init(void); | |||
| #endif | |||
| #if F_TIMER == 120000000 | |||
| #if F_TIMER == 128000000 | |||
| #define DEFAULT_FTM_MOD (65536 - 1) | |||
| #define DEFAULT_FTM_PRESCALE 2 | |||
| #elif F_TIMER == 120000000 | |||
| #define DEFAULT_FTM_MOD (61440 - 1) | |||
| #define DEFAULT_FTM_PRESCALE 2 | |||
| #elif F_TIMER == 108000000 | |||
| @@ -1206,7 +1209,9 @@ void delay(uint32_t ms) | |||
| } | |||
| // TODO: verify these result in correct timeouts... | |||
| #if F_CPU == 240000000 | |||
| #if F_CPU == 256000000 | |||
| #define PULSEIN_LOOPS_PER_USEC 34 | |||
| #elif F_CPU == 240000000 | |||
| #define PULSEIN_LOOPS_PER_USEC 33 | |||
| #elif F_CPU == 216000000 | |||
| #define PULSEIN_LOOPS_PER_USEC 31 | |||
| @@ -1129,7 +1129,7 @@ void usb_init(void) | |||
| #ifdef HAS_KINETIS_MPU | |||
| MPU_RGDAAC0 |= 0x03000000; | |||
| #endif | |||
| #if F_CPU == 180000000 || F_CPU == 216000000 | |||
| #if F_CPU == 180000000 || F_CPU == 216000000 || F_CPU == 256000000 | |||
| // if using IRC48M, turn on the USB clock recovery hardware | |||
| USB0_CLK_RECOVER_IRC_EN = USB_CLK_RECOVER_IRC_EN_IRC_EN | USB_CLK_RECOVER_IRC_EN_REG_EN; | |||
| USB0_CLK_RECOVER_CTRL = USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN | | |||
| @@ -48,8 +48,9 @@ static uint8_t transmit_previous_timeout=0; | |||
| // When the PC isn't listening, how long do we wait before discarding data? | |||
| #define TX_TIMEOUT_MSEC 30 | |||
| #if F_CPU == 240000000 | |||
| #if F_CPU == 256000000 | |||
| #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1706) | |||
| #elif F_CPU == 240000000 | |||
| #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1600) | |||
| #elif F_CPU == 216000000 | |||
| #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1440) | |||
| @@ -496,8 +496,9 @@ static uint8_t transmit_previous_timeout=0; | |||
| // When the PC isn't listening, how long do we wait before discarding data? | |||
| #define TX_TIMEOUT_MSEC 50 | |||
| #if F_CPU == 240000000 | |||
| #if F_CPU == 256000000 | |||
| #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1706) | |||
| #elif F_CPU == 240000000 | |||
| #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1600) | |||
| #elif F_CPU == 216000000 | |||
| #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1440) | |||
| @@ -76,8 +76,9 @@ static uint8_t tx_noautoflush=0; | |||
| // When the PC isn't listening, how long do we wait before discarding data? | |||
| #define TX_TIMEOUT_MSEC 40 | |||
| #if F_CPU == 240000000 | |||
| #if F_CPU == 256000000 | |||
| #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1706) | |||
| #elif F_CPU == 240000000 | |||
| #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1600) | |||
| #elif F_CPU == 216000000 | |||
| #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1440) | |||
| @@ -116,8 +116,9 @@ static uint8_t transmit_previous_timeout=0; | |||
| // When the PC isn't listening, how long do we wait before discarding data? | |||
| #define TX_TIMEOUT_MSEC 30 | |||
| #if F_CPU == 240000000 | |||
| #if F_CPU == 256000000 | |||
| #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1706) | |||
| #elif F_CPU == 240000000 | |||
| #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1600) | |||
| #elif F_CPU == 216000000 | |||
| #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1440) | |||
| @@ -138,8 +138,9 @@ void usb_seremu_flush_input(void) | |||
| // too short, we risk losing data during the stalls that are common with ordinary desktop | |||
| // software. If it's too long, we stall the user's program when no software is running. | |||
| #define TX_TIMEOUT_MSEC 30 | |||
| #if F_CPU == 240000000 | |||
| #if F_CPU == 256000000 | |||
| #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1706) | |||
| #elif F_CPU == 240000000 | |||
| #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1600) | |||
| #elif F_CPU == 216000000 | |||
| #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1440) | |||
| @@ -148,8 +148,9 @@ void usb_serial_flush_input(void) | |||
| // too short, we risk losing data during the stalls that are common with ordinary desktop | |||
| // software. If it's too long, we stall the user's program when no software is running. | |||
| #define TX_TIMEOUT_MSEC 70 | |||
| #if F_CPU == 240000000 | |||
| #if F_CPU == 256000000 | |||
| #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1706) | |||
| #elif F_CPU == 240000000 | |||
| #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1600) | |||
| #elif F_CPU == 216000000 | |||
| #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1440) | |||