| // Tunable parameters (relatively safe to edit these numbers) | // Tunable parameters (relatively safe to edit these numbers) | ||||
| //////////////////////////////////////////////////////////////// | //////////////////////////////////////////////////////////////// | ||||
| #define TX_BUFFER_SIZE 64 // number of outgoing bytes to buffer | |||||
| #define RX_BUFFER_SIZE 64 // number of incoming bytes to buffer | |||||
| #ifndef SERIAL1_TX_BUFFER_SIZE | |||||
| #define SERIAL1_TX_BUFFER_SIZE 64 // number of outgoing bytes to buffer | |||||
| #endif | |||||
| #ifndef SERIAL1_RX_BUFFER_SIZE | |||||
| #define SERIAL1_RX_BUFFER_SIZE 64 // number of incoming bytes to buffer | |||||
| #endif | |||||
| #define RTS_HIGH_WATERMARK 40 // RTS requests sender to pause | #define RTS_HIGH_WATERMARK 40 // RTS requests sender to pause | ||||
| #define RTS_LOW_WATERMARK 26 // RTS allows sender to resume | #define RTS_LOW_WATERMARK 26 // RTS allows sender to resume | ||||
| #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest | #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest | ||||
| #define use9Bits 0 | #define use9Bits 0 | ||||
| #endif | #endif | ||||
| static volatile BUFTYPE tx_buffer[TX_BUFFER_SIZE]; | |||||
| static volatile BUFTYPE rx_buffer[RX_BUFFER_SIZE]; | |||||
| static volatile BUFTYPE tx_buffer[SERIAL1_TX_BUFFER_SIZE]; | |||||
| static volatile BUFTYPE rx_buffer[SERIAL1_RX_BUFFER_SIZE]; | |||||
| static volatile uint8_t transmitting = 0; | static volatile uint8_t transmitting = 0; | ||||
| #if defined(KINETISK) | #if defined(KINETISK) | ||||
| static volatile uint8_t *transmit_pin=NULL; | static volatile uint8_t *transmit_pin=NULL; | ||||
| #define rts_assert() *(rts_pin+8) = rts_mask; | #define rts_assert() *(rts_pin+8) = rts_mask; | ||||
| #define rts_deassert() *(rts_pin+4) = rts_mask; | #define rts_deassert() *(rts_pin+4) = rts_mask; | ||||
| #endif | #endif | ||||
| #if TX_BUFFER_SIZE > 255 | |||||
| #if SERIAL1_TX_BUFFER_SIZE > 255 | |||||
| static volatile uint16_t tx_buffer_head = 0; | static volatile uint16_t tx_buffer_head = 0; | ||||
| static volatile uint16_t tx_buffer_tail = 0; | static volatile uint16_t tx_buffer_tail = 0; | ||||
| #else | #else | ||||
| static volatile uint8_t tx_buffer_head = 0; | static volatile uint8_t tx_buffer_head = 0; | ||||
| static volatile uint8_t tx_buffer_tail = 0; | static volatile uint8_t tx_buffer_tail = 0; | ||||
| #endif | #endif | ||||
| #if RX_BUFFER_SIZE > 255 | |||||
| #if SERIAL1_RX_BUFFER_SIZE > 255 | |||||
| static volatile uint16_t rx_buffer_head = 0; | static volatile uint16_t rx_buffer_head = 0; | ||||
| static volatile uint16_t rx_buffer_tail = 0; | static volatile uint16_t rx_buffer_tail = 0; | ||||
| #else | #else | ||||
| if (!(SIM_SCGC4 & SIM_SCGC4_UART0)) return; | if (!(SIM_SCGC4 & SIM_SCGC4_UART0)) return; | ||||
| if (transmit_pin) transmit_assert(); | if (transmit_pin) transmit_assert(); | ||||
| head = tx_buffer_head; | head = tx_buffer_head; | ||||
| if (++head >= TX_BUFFER_SIZE) head = 0; | |||||
| if (++head >= SERIAL1_TX_BUFFER_SIZE) head = 0; | |||||
| while (tx_buffer_tail == head) { | while (tx_buffer_tail == head) { | ||||
| int priority = nvic_execution_priority(); | int priority = nvic_execution_priority(); | ||||
| if (priority <= IRQ_PRIORITY) { | if (priority <= IRQ_PRIORITY) { | ||||
| if ((UART0_S1 & UART_S1_TDRE)) { | if ((UART0_S1 & UART_S1_TDRE)) { | ||||
| uint32_t tail = tx_buffer_tail; | uint32_t tail = tx_buffer_tail; | ||||
| if (++tail >= TX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL1_TX_BUFFER_SIZE) tail = 0; | |||||
| n = tx_buffer[tail]; | n = tx_buffer[tail]; | ||||
| if (use9Bits) UART0_C3 = (UART0_C3 & ~0x40) | ((n & 0x100) >> 2); | if (use9Bits) UART0_C3 = (UART0_C3 & ~0x40) | ((n & 0x100) >> 2); | ||||
| UART0_D = n; | UART0_D = n; | ||||
| if (transmit_pin) transmit_assert(); | if (transmit_pin) transmit_assert(); | ||||
| while (p < end) { | while (p < end) { | ||||
| head = tx_buffer_head; | head = tx_buffer_head; | ||||
| if (++head >= TX_BUFFER_SIZE) head = 0; | |||||
| if (++head >= SERIAL1_TX_BUFFER_SIZE) head = 0; | |||||
| if (tx_buffer_tail == head) { | if (tx_buffer_tail == head) { | ||||
| UART0_C2 = C2_TX_ACTIVE; | UART0_C2 = C2_TX_ACTIVE; | ||||
| do { | do { | ||||
| if (priority <= IRQ_PRIORITY) { | if (priority <= IRQ_PRIORITY) { | ||||
| if ((UART0_S1 & UART_S1_TDRE)) { | if ((UART0_S1 & UART_S1_TDRE)) { | ||||
| uint32_t tail = tx_buffer_tail; | uint32_t tail = tx_buffer_tail; | ||||
| if (++tail >= TX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL1_TX_BUFFER_SIZE) tail = 0; | |||||
| n = tx_buffer[tail]; | n = tx_buffer[tail]; | ||||
| if (use9Bits) UART0_C3 = (UART0_C3 & ~0x40) | ((n & 0x100) >> 2); | if (use9Bits) UART0_C3 = (UART0_C3 & ~0x40) | ((n & 0x100) >> 2); | ||||
| UART0_D = n; | UART0_D = n; | ||||
| head = tx_buffer_head; | head = tx_buffer_head; | ||||
| tail = tx_buffer_tail; | tail = tx_buffer_tail; | ||||
| if (head >= tail) return TX_BUFFER_SIZE - 1 - head + tail; | |||||
| if (head >= tail) return SERIAL1_TX_BUFFER_SIZE - 1 - head + tail; | |||||
| return tail - head - 1; | return tail - head - 1; | ||||
| } | } | ||||
| head = rx_buffer_head; | head = rx_buffer_head; | ||||
| tail = rx_buffer_tail; | tail = rx_buffer_tail; | ||||
| if (head >= tail) return head - tail; | if (head >= tail) return head - tail; | ||||
| return RX_BUFFER_SIZE + head - tail; | |||||
| return SERIAL1_RX_BUFFER_SIZE + head - tail; | |||||
| } | } | ||||
| int serial_getchar(void) | int serial_getchar(void) | ||||
| head = rx_buffer_head; | head = rx_buffer_head; | ||||
| tail = rx_buffer_tail; | tail = rx_buffer_tail; | ||||
| if (head == tail) return -1; | if (head == tail) return -1; | ||||
| if (++tail >= RX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL1_RX_BUFFER_SIZE) tail = 0; | |||||
| c = rx_buffer[tail]; | c = rx_buffer[tail]; | ||||
| rx_buffer_tail = tail; | rx_buffer_tail = tail; | ||||
| if (rts_pin) { | if (rts_pin) { | ||||
| int avail; | int avail; | ||||
| if (head >= tail) avail = head - tail; | if (head >= tail) avail = head - tail; | ||||
| else avail = RX_BUFFER_SIZE + head - tail; | |||||
| else avail = SERIAL1_RX_BUFFER_SIZE + head - tail; | |||||
| if (avail <= RTS_LOW_WATERMARK) rts_assert(); | if (avail <= RTS_LOW_WATERMARK) rts_assert(); | ||||
| } | } | ||||
| return c; | return c; | ||||
| head = rx_buffer_head; | head = rx_buffer_head; | ||||
| tail = rx_buffer_tail; | tail = rx_buffer_tail; | ||||
| if (head == tail) return -1; | if (head == tail) return -1; | ||||
| if (++tail >= RX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL1_RX_BUFFER_SIZE) tail = 0; | |||||
| return rx_buffer[tail]; | return rx_buffer[tail]; | ||||
| } | } | ||||
| n = UART0_D; | n = UART0_D; | ||||
| } | } | ||||
| newhead = head + 1; | newhead = head + 1; | ||||
| if (newhead >= RX_BUFFER_SIZE) newhead = 0; | |||||
| if (newhead >= SERIAL1_RX_BUFFER_SIZE) newhead = 0; | |||||
| if (newhead != tail) { | if (newhead != tail) { | ||||
| head = newhead; | head = newhead; | ||||
| rx_buffer[head] = n; | rx_buffer[head] = n; | ||||
| if (rts_pin) { | if (rts_pin) { | ||||
| int avail; | int avail; | ||||
| if (head >= tail) avail = head - tail; | if (head >= tail) avail = head - tail; | ||||
| else avail = RX_BUFFER_SIZE + head - tail; | |||||
| else avail = SERIAL1_RX_BUFFER_SIZE + head - tail; | |||||
| if (avail >= RTS_HIGH_WATERMARK) rts_deassert(); | if (avail >= RTS_HIGH_WATERMARK) rts_deassert(); | ||||
| } | } | ||||
| } | } | ||||
| tail = tx_buffer_tail; | tail = tx_buffer_tail; | ||||
| do { | do { | ||||
| if (tail == head) break; | if (tail == head) break; | ||||
| if (++tail >= TX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL1_TX_BUFFER_SIZE) tail = 0; | |||||
| avail = UART0_S1; | avail = UART0_S1; | ||||
| n = tx_buffer[tail]; | n = tx_buffer[tail]; | ||||
| if (use9Bits) UART0_C3 = (UART0_C3 & ~0x40) | ((n & 0x100) >> 2); | if (use9Bits) UART0_C3 = (UART0_C3 & ~0x40) | ((n & 0x100) >> 2); | ||||
| n = UART0_D; | n = UART0_D; | ||||
| if (use9Bits && (UART0_C3 & 0x80)) n |= 0x100; | if (use9Bits && (UART0_C3 & 0x80)) n |= 0x100; | ||||
| head = rx_buffer_head + 1; | head = rx_buffer_head + 1; | ||||
| if (head >= RX_BUFFER_SIZE) head = 0; | |||||
| if (head >= SERIAL1_RX_BUFFER_SIZE) head = 0; | |||||
| if (head != rx_buffer_tail) { | if (head != rx_buffer_tail) { | ||||
| rx_buffer[head] = n; | rx_buffer[head] = n; | ||||
| rx_buffer_head = head; | rx_buffer_head = head; | ||||
| if (head == tail) { | if (head == tail) { | ||||
| UART0_C2 = C2_TX_COMPLETING; | UART0_C2 = C2_TX_COMPLETING; | ||||
| } else { | } else { | ||||
| if (++tail >= TX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL1_TX_BUFFER_SIZE) tail = 0; | |||||
| n = tx_buffer[tail]; | n = tx_buffer[tail]; | ||||
| if (use9Bits) UART0_C3 = (UART0_C3 & ~0x40) | ((n & 0x100) >> 2); | if (use9Bits) UART0_C3 = (UART0_C3 & ~0x40) | ((n & 0x100) >> 2); | ||||
| UART0_D = n; | UART0_D = n; |
| // Tunable parameters (relatively safe to edit these numbers) | // Tunable parameters (relatively safe to edit these numbers) | ||||
| //////////////////////////////////////////////////////////////// | //////////////////////////////////////////////////////////////// | ||||
| #define TX_BUFFER_SIZE 64 // number of outgoing bytes to buffer | |||||
| #define RX_BUFFER_SIZE 64 // number of incoming bytes to buffer | |||||
| #ifndef SERIAL1_TX_BUFFER_SIZE | |||||
| #define SERIAL1_TX_BUFFER_SIZE 64 // number of outgoing bytes to buffer | |||||
| #endif | |||||
| #ifndef SERIAL1_RX_BUFFER_SIZE | |||||
| #define SERIAL1_RX_BUFFER_SIZE 64 // number of incoming bytes to buffer | |||||
| #endif | |||||
| #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest | #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest | ||||
| #define use9Bits 0 | #define use9Bits 0 | ||||
| #endif | #endif | ||||
| static volatile BUFTYPE tx_buffer[TX_BUFFER_SIZE]; | |||||
| static volatile BUFTYPE rx_buffer[RX_BUFFER_SIZE]; | |||||
| static volatile BUFTYPE tx_buffer[SERIAL1_TX_BUFFER_SIZE]; | |||||
| static volatile BUFTYPE rx_buffer[SERIAL1_RX_BUFFER_SIZE]; | |||||
| static volatile uint8_t transmitting = 0; | static volatile uint8_t transmitting = 0; | ||||
| #if defined(KINETISK) | #if defined(KINETISK) | ||||
| static volatile uint8_t *transmit_pin=NULL; | static volatile uint8_t *transmit_pin=NULL; | ||||
| #define transmit_assert() *(transmit_pin+4) = transmit_mask; | #define transmit_assert() *(transmit_pin+4) = transmit_mask; | ||||
| #define transmit_deassert() *(transmit_pin+8) = transmit_mask; | #define transmit_deassert() *(transmit_pin+8) = transmit_mask; | ||||
| #endif | #endif | ||||
| #if TX_BUFFER_SIZE > 255 | |||||
| #if SERIAL1_TX_BUFFER_SIZE > 255 | |||||
| static volatile uint16_t tx_buffer_head = 0; | static volatile uint16_t tx_buffer_head = 0; | ||||
| static volatile uint16_t tx_buffer_tail = 0; | static volatile uint16_t tx_buffer_tail = 0; | ||||
| #else | #else | ||||
| static volatile uint8_t tx_buffer_head = 0; | static volatile uint8_t tx_buffer_head = 0; | ||||
| static volatile uint8_t tx_buffer_tail = 0; | static volatile uint8_t tx_buffer_tail = 0; | ||||
| #endif | #endif | ||||
| #if RX_BUFFER_SIZE > 255 | |||||
| #if SERIAL1_RX_BUFFER_SIZE > 255 | |||||
| static volatile uint16_t rx_buffer_head = 0; | static volatile uint16_t rx_buffer_head = 0; | ||||
| static volatile uint16_t rx_buffer_tail = 0; | static volatile uint16_t rx_buffer_tail = 0; | ||||
| #else | #else | ||||
| if (!(SIM_SCGC4 & SIM_SCGC4_UART0)) return; | if (!(SIM_SCGC4 & SIM_SCGC4_UART0)) return; | ||||
| if (transmit_pin) transmit_assert(); | if (transmit_pin) transmit_assert(); | ||||
| head = tx_buffer_head; | head = tx_buffer_head; | ||||
| if (++head >= TX_BUFFER_SIZE) head = 0; | |||||
| if (++head >= SERIAL1_TX_BUFFER_SIZE) head = 0; | |||||
| while (tx_buffer_tail == head) { | while (tx_buffer_tail == head) { | ||||
| int priority = nvic_execution_priority(); | int priority = nvic_execution_priority(); | ||||
| if (priority <= IRQ_PRIORITY) { | if (priority <= IRQ_PRIORITY) { | ||||
| if ((UART0_S1 & UART_S1_TDRE)) { | if ((UART0_S1 & UART_S1_TDRE)) { | ||||
| uint32_t tail = tx_buffer_tail; | uint32_t tail = tx_buffer_tail; | ||||
| if (++tail >= TX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL1_TX_BUFFER_SIZE) tail = 0; | |||||
| n = tx_buffer[tail]; | n = tx_buffer[tail]; | ||||
| if (use9Bits) UART0_C3 = (UART0_C3 & ~0x40) | ((n & 0x100) >> 2); | if (use9Bits) UART0_C3 = (UART0_C3 & ~0x40) | ((n & 0x100) >> 2); | ||||
| UART0_D = n; | UART0_D = n; | ||||
| if (transmit_pin) transmit_assert(); | if (transmit_pin) transmit_assert(); | ||||
| while (p < end) { | while (p < end) { | ||||
| head = tx_buffer_head; | head = tx_buffer_head; | ||||
| if (++head >= TX_BUFFER_SIZE) head = 0; | |||||
| if (++head >= SERIAL1_TX_BUFFER_SIZE) head = 0; | |||||
| if (tx_buffer_tail == head) { | if (tx_buffer_tail == head) { | ||||
| UART0_C2 |= UART_C2_TIE; | UART0_C2 |= UART_C2_TIE; | ||||
| UART0_C2 &= ~UART_C2_TCIE; | UART0_C2 &= ~UART_C2_TCIE; | ||||
| if (priority <= IRQ_PRIORITY) { | if (priority <= IRQ_PRIORITY) { | ||||
| if ((UART0_S1 & UART_S1_TDRE)) { | if ((UART0_S1 & UART_S1_TDRE)) { | ||||
| uint32_t tail = tx_buffer_tail; | uint32_t tail = tx_buffer_tail; | ||||
| if (++tail >= TX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL1_TX_BUFFER_SIZE) tail = 0; | |||||
| n = tx_buffer[tail]; | n = tx_buffer[tail]; | ||||
| if (use9Bits) UART0_C3 = (UART0_C3 & ~0x40) | ((n & 0x100) >> 2); | if (use9Bits) UART0_C3 = (UART0_C3 & ~0x40) | ((n & 0x100) >> 2); | ||||
| UART0_D = n; | UART0_D = n; | ||||
| head = tx_buffer_head; | head = tx_buffer_head; | ||||
| tail = tx_buffer_tail; | tail = tx_buffer_tail; | ||||
| if (head >= tail) return TX_BUFFER_SIZE - 1 - head + tail; | |||||
| if (head >= tail) return SERIAL1_TX_BUFFER_SIZE - 1 - head + tail; | |||||
| return tail - head - 1; | return tail - head - 1; | ||||
| } | } | ||||
| head = rx_buffer_head; | head = rx_buffer_head; | ||||
| tail = rx_buffer_tail; | tail = rx_buffer_tail; | ||||
| if (head >= tail) return head - tail; | if (head >= tail) return head - tail; | ||||
| return RX_BUFFER_SIZE + head - tail; | |||||
| return SERIAL1_RX_BUFFER_SIZE + head - tail; | |||||
| } | } | ||||
| int serial_getchar(void) | int serial_getchar(void) | ||||
| head = rx_buffer_head; | head = rx_buffer_head; | ||||
| tail = rx_buffer_tail; | tail = rx_buffer_tail; | ||||
| if (head == tail) return -1; | if (head == tail) return -1; | ||||
| if (++tail >= RX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL1_RX_BUFFER_SIZE) tail = 0; | |||||
| c = rx_buffer[tail]; | c = rx_buffer[tail]; | ||||
| rx_buffer_tail = tail; | rx_buffer_tail = tail; | ||||
| #ifdef HAS_KINETISK_UART0_FIFO | #ifdef HAS_KINETISK_UART0_FIFO | ||||
| if ((UART0_C2 & (UART_C2_RIE | UART_C2_ILIE))==0) {//rx interrupt currently disabled | if ((UART0_C2 & (UART_C2_RIE | UART_C2_ILIE))==0) {//rx interrupt currently disabled | ||||
| int freespace; | int freespace; | ||||
| if (head >= tail) //rx head and tail would be unchanged from above if interrupts were disabled | if (head >= tail) //rx head and tail would be unchanged from above if interrupts were disabled | ||||
| freespace = RX_BUFFER_SIZE -1 + tail - head; | |||||
| freespace = SERIAL1_RX_BUFFER_SIZE -1 + tail - head; | |||||
| else | else | ||||
| freespace = tail - head - 1; | freespace = tail - head - 1; | ||||
| if (freespace >= UART0_RCFIFO) { | if (freespace >= UART0_RCFIFO) { | ||||
| head = rx_buffer_head; | head = rx_buffer_head; | ||||
| tail = rx_buffer_tail; | tail = rx_buffer_tail; | ||||
| if (head == tail) return -1; | if (head == tail) return -1; | ||||
| if (++tail >= RX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL1_RX_BUFFER_SIZE) tail = 0; | |||||
| return rx_buffer[tail]; | return rx_buffer[tail]; | ||||
| } | } | ||||
| tail = rx_buffer_tail; | tail = rx_buffer_tail; | ||||
| do { | do { | ||||
| newhead = head + 1; | newhead = head + 1; | ||||
| if (newhead >= RX_BUFFER_SIZE) newhead = 0; | |||||
| if (newhead >= SERIAL1_RX_BUFFER_SIZE) newhead = 0; | |||||
| if (UART0_MODEM & UART_MODEM_RXRTSE) { | if (UART0_MODEM & UART_MODEM_RXRTSE) { | ||||
| if (newhead == tail) { | if (newhead == tail) { | ||||
| UART0_C2 &= ~(UART_C2_RIE | UART_C2_ILIE);//disable rx interrupts | UART0_C2 &= ~(UART_C2_RIE | UART_C2_ILIE);//disable rx interrupts | ||||
| tail = tx_buffer_tail; | tail = tx_buffer_tail; | ||||
| do { | do { | ||||
| if (tail == head) break; | if (tail == head) break; | ||||
| if (++tail >= TX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL1_TX_BUFFER_SIZE) tail = 0; | |||||
| UART0_S1; | UART0_S1; | ||||
| n = tx_buffer[tail]; | n = tx_buffer[tail]; | ||||
| if (use9Bits) UART0_C3 = (UART0_C3 & ~0x40) | ((n & 0x100) >> 2); | if (use9Bits) UART0_C3 = (UART0_C3 & ~0x40) | ((n & 0x100) >> 2); | ||||
| if (UART0_S1 & UART_S1_RDRF) { | if (UART0_S1 & UART_S1_RDRF) { | ||||
| do { | do { | ||||
| head = rx_buffer_head + 1; | head = rx_buffer_head + 1; | ||||
| if (head >= RX_BUFFER_SIZE) head = 0; | |||||
| if (head >= SERIAL1_RX_BUFFER_SIZE) head = 0; | |||||
| if (UART0_MODEM & UART_MODEM_RXRTSE) { | if (UART0_MODEM & UART_MODEM_RXRTSE) { | ||||
| if (head == rx_buffer_tail) { | if (head == rx_buffer_tail) { | ||||
| UART0_C2 &= ~(UART_C2_RIE);//disable rx interrupts | UART0_C2 &= ~(UART_C2_RIE);//disable rx interrupts | ||||
| UART0_C2 |= UART_C2_TCIE; | UART0_C2 |= UART_C2_TCIE; | ||||
| UART0_C2 &= ~UART_C2_TIE; | UART0_C2 &= ~UART_C2_TIE; | ||||
| } else { | } else { | ||||
| if (++tail >= TX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL1_TX_BUFFER_SIZE) tail = 0; | |||||
| n = tx_buffer[tail]; | n = tx_buffer[tail]; | ||||
| if (use9Bits) UART0_C3 = (UART0_C3 & ~0x40) | ((n & 0x100) >> 2); | if (use9Bits) UART0_C3 = (UART0_C3 & ~0x40) | ((n & 0x100) >> 2); | ||||
| UART0_D = n; | UART0_D = n; |
| // Tunable parameters (relatively safe to edit these numbers) | // Tunable parameters (relatively safe to edit these numbers) | ||||
| //////////////////////////////////////////////////////////////// | //////////////////////////////////////////////////////////////// | ||||
| #define TX_BUFFER_SIZE 40 // number of outgoing bytes to buffer | |||||
| #define RX_BUFFER_SIZE 64 // number of incoming bytes to buffer | |||||
| #ifndef SERIAL2_TX_BUFFER_SIZE | |||||
| #define SERIAL2_TX_BUFFER_SIZE 40 // number of outgoing bytes to buffer | |||||
| #endif | |||||
| #ifndef SERIAL2_RX_BUFFER_SIZE | |||||
| #define SERIAL2_RX_BUFFER_SIZE 64 // number of incoming bytes to buffer | |||||
| #endif | |||||
| #define RTS_HIGH_WATERMARK 40 // RTS requests sender to pause | #define RTS_HIGH_WATERMARK 40 // RTS requests sender to pause | ||||
| #define RTS_LOW_WATERMARK 26 // RTS allows sender to resume | #define RTS_LOW_WATERMARK 26 // RTS allows sender to resume | ||||
| #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest | #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest | ||||
| #define use9Bits 0 | #define use9Bits 0 | ||||
| #endif | #endif | ||||
| static volatile BUFTYPE tx_buffer[TX_BUFFER_SIZE]; | |||||
| static volatile BUFTYPE rx_buffer[RX_BUFFER_SIZE]; | |||||
| static volatile BUFTYPE tx_buffer[SERIAL2_TX_BUFFER_SIZE]; | |||||
| static volatile BUFTYPE rx_buffer[SERIAL2_RX_BUFFER_SIZE]; | |||||
| static volatile uint8_t transmitting = 0; | static volatile uint8_t transmitting = 0; | ||||
| #if defined(KINETISK) | #if defined(KINETISK) | ||||
| static volatile uint8_t *transmit_pin=NULL; | static volatile uint8_t *transmit_pin=NULL; | ||||
| #define rts_assert() *(rts_pin+8) = rts_mask; | #define rts_assert() *(rts_pin+8) = rts_mask; | ||||
| #define rts_deassert() *(rts_pin+4) = rts_mask; | #define rts_deassert() *(rts_pin+4) = rts_mask; | ||||
| #endif | #endif | ||||
| #if TX_BUFFER_SIZE > 255 | |||||
| #if SERIAL2_TX_BUFFER_SIZE > 255 | |||||
| static volatile uint16_t tx_buffer_head = 0; | static volatile uint16_t tx_buffer_head = 0; | ||||
| static volatile uint16_t tx_buffer_tail = 0; | static volatile uint16_t tx_buffer_tail = 0; | ||||
| #else | #else | ||||
| static volatile uint8_t tx_buffer_head = 0; | static volatile uint8_t tx_buffer_head = 0; | ||||
| static volatile uint8_t tx_buffer_tail = 0; | static volatile uint8_t tx_buffer_tail = 0; | ||||
| #endif | #endif | ||||
| #if RX_BUFFER_SIZE > 255 | |||||
| #if SERIAL2_RX_BUFFER_SIZE > 255 | |||||
| static volatile uint16_t rx_buffer_head = 0; | static volatile uint16_t rx_buffer_head = 0; | ||||
| static volatile uint16_t rx_buffer_tail = 0; | static volatile uint16_t rx_buffer_tail = 0; | ||||
| #else | #else | ||||
| if (!(SIM_SCGC4 & SIM_SCGC4_UART1)) return; | if (!(SIM_SCGC4 & SIM_SCGC4_UART1)) return; | ||||
| if (transmit_pin) transmit_assert(); | if (transmit_pin) transmit_assert(); | ||||
| head = tx_buffer_head; | head = tx_buffer_head; | ||||
| if (++head >= TX_BUFFER_SIZE) head = 0; | |||||
| if (++head >= SERIAL2_TX_BUFFER_SIZE) head = 0; | |||||
| while (tx_buffer_tail == head) { | while (tx_buffer_tail == head) { | ||||
| int priority = nvic_execution_priority(); | int priority = nvic_execution_priority(); | ||||
| if (priority <= IRQ_PRIORITY) { | if (priority <= IRQ_PRIORITY) { | ||||
| if ((UART1_S1 & UART_S1_TDRE)) { | if ((UART1_S1 & UART_S1_TDRE)) { | ||||
| uint32_t tail = tx_buffer_tail; | uint32_t tail = tx_buffer_tail; | ||||
| if (++tail >= TX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL2_TX_BUFFER_SIZE) tail = 0; | |||||
| n = tx_buffer[tail]; | n = tx_buffer[tail]; | ||||
| if (use9Bits) UART1_C3 = (UART1_C3 & ~0x40) | ((n & 0x100) >> 2); | if (use9Bits) UART1_C3 = (UART1_C3 & ~0x40) | ((n & 0x100) >> 2); | ||||
| UART1_D = n; | UART1_D = n; | ||||
| if (transmit_pin) transmit_assert(); | if (transmit_pin) transmit_assert(); | ||||
| while (p < end) { | while (p < end) { | ||||
| head = tx_buffer_head; | head = tx_buffer_head; | ||||
| if (++head >= TX_BUFFER_SIZE) head = 0; | |||||
| if (++head >= SERIAL2_TX_BUFFER_SIZE) head = 0; | |||||
| if (tx_buffer_tail == head) { | if (tx_buffer_tail == head) { | ||||
| UART1_C2 = C2_TX_ACTIVE; | UART1_C2 = C2_TX_ACTIVE; | ||||
| do { | do { | ||||
| if (priority <= IRQ_PRIORITY) { | if (priority <= IRQ_PRIORITY) { | ||||
| if ((UART1_S1 & UART_S1_TDRE)) { | if ((UART1_S1 & UART_S1_TDRE)) { | ||||
| uint32_t tail = tx_buffer_tail; | uint32_t tail = tx_buffer_tail; | ||||
| if (++tail >= TX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL2_TX_BUFFER_SIZE) tail = 0; | |||||
| n = tx_buffer[tail]; | n = tx_buffer[tail]; | ||||
| if (use9Bits) UART1_C3 = (UART1_C3 & ~0x40) | ((n & 0x100) >> 2); | if (use9Bits) UART1_C3 = (UART1_C3 & ~0x40) | ((n & 0x100) >> 2); | ||||
| UART1_D = n; | UART1_D = n; | ||||
| head = tx_buffer_head; | head = tx_buffer_head; | ||||
| tail = tx_buffer_tail; | tail = tx_buffer_tail; | ||||
| if (head >= tail) return TX_BUFFER_SIZE - 1 - head + tail; | |||||
| if (head >= tail) return SERIAL2_TX_BUFFER_SIZE - 1 - head + tail; | |||||
| return tail - head - 1; | return tail - head - 1; | ||||
| } | } | ||||
| head = rx_buffer_head; | head = rx_buffer_head; | ||||
| tail = rx_buffer_tail; | tail = rx_buffer_tail; | ||||
| if (head >= tail) return head - tail; | if (head >= tail) return head - tail; | ||||
| return RX_BUFFER_SIZE + head - tail; | |||||
| return SERIAL2_RX_BUFFER_SIZE + head - tail; | |||||
| } | } | ||||
| int serial2_getchar(void) | int serial2_getchar(void) | ||||
| head = rx_buffer_head; | head = rx_buffer_head; | ||||
| tail = rx_buffer_tail; | tail = rx_buffer_tail; | ||||
| if (head == tail) return -1; | if (head == tail) return -1; | ||||
| if (++tail >= RX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL2_RX_BUFFER_SIZE) tail = 0; | |||||
| c = rx_buffer[tail]; | c = rx_buffer[tail]; | ||||
| rx_buffer_tail = tail; | rx_buffer_tail = tail; | ||||
| if (rts_pin) { | if (rts_pin) { | ||||
| int avail; | int avail; | ||||
| if (head >= tail) avail = head - tail; | if (head >= tail) avail = head - tail; | ||||
| else avail = RX_BUFFER_SIZE + head - tail; | |||||
| else avail = SERIAL2_RX_BUFFER_SIZE + head - tail; | |||||
| if (avail <= RTS_LOW_WATERMARK) rts_assert(); | if (avail <= RTS_LOW_WATERMARK) rts_assert(); | ||||
| } | } | ||||
| return c; | return c; | ||||
| head = rx_buffer_head; | head = rx_buffer_head; | ||||
| tail = rx_buffer_tail; | tail = rx_buffer_tail; | ||||
| if (head == tail) return -1; | if (head == tail) return -1; | ||||
| if (++tail >= RX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL2_RX_BUFFER_SIZE) tail = 0; | |||||
| return rx_buffer[tail]; | return rx_buffer[tail]; | ||||
| } | } | ||||
| n = UART1_D; | n = UART1_D; | ||||
| } | } | ||||
| newhead = head + 1; | newhead = head + 1; | ||||
| if (newhead >= RX_BUFFER_SIZE) newhead = 0; | |||||
| if (newhead >= SERIAL2_RX_BUFFER_SIZE) newhead = 0; | |||||
| if (newhead != tail) { | if (newhead != tail) { | ||||
| head = newhead; | head = newhead; | ||||
| rx_buffer[head] = n; | rx_buffer[head] = n; | ||||
| if (rts_pin) { | if (rts_pin) { | ||||
| int avail; | int avail; | ||||
| if (head >= tail) avail = head - tail; | if (head >= tail) avail = head - tail; | ||||
| else avail = RX_BUFFER_SIZE + head - tail; | |||||
| else avail = SERIAL2_RX_BUFFER_SIZE + head - tail; | |||||
| if (avail >= RTS_HIGH_WATERMARK) rts_deassert(); | if (avail >= RTS_HIGH_WATERMARK) rts_deassert(); | ||||
| } | } | ||||
| } | } | ||||
| tail = tx_buffer_tail; | tail = tx_buffer_tail; | ||||
| do { | do { | ||||
| if (tail == head) break; | if (tail == head) break; | ||||
| if (++tail >= TX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL2_TX_BUFFER_SIZE) tail = 0; | |||||
| avail = UART1_S1; | avail = UART1_S1; | ||||
| n = tx_buffer[tail]; | n = tx_buffer[tail]; | ||||
| if (use9Bits) UART1_C3 = (UART1_C3 & ~0x40) | ((n & 0x100) >> 2); | if (use9Bits) UART1_C3 = (UART1_C3 & ~0x40) | ((n & 0x100) >> 2); | ||||
| n = UART1_D; | n = UART1_D; | ||||
| if (use9Bits && (UART1_C3 & 0x80)) n |= 0x100; | if (use9Bits && (UART1_C3 & 0x80)) n |= 0x100; | ||||
| head = rx_buffer_head + 1; | head = rx_buffer_head + 1; | ||||
| if (head >= RX_BUFFER_SIZE) head = 0; | |||||
| if (head >= SERIAL2_RX_BUFFER_SIZE) head = 0; | |||||
| if (head != rx_buffer_tail) { | if (head != rx_buffer_tail) { | ||||
| rx_buffer[head] = n; | rx_buffer[head] = n; | ||||
| rx_buffer_head = head; | rx_buffer_head = head; | ||||
| if (head == tail) { | if (head == tail) { | ||||
| UART1_C2 = C2_TX_COMPLETING; | UART1_C2 = C2_TX_COMPLETING; | ||||
| } else { | } else { | ||||
| if (++tail >= TX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL2_TX_BUFFER_SIZE) tail = 0; | |||||
| n = tx_buffer[tail]; | n = tx_buffer[tail]; | ||||
| if (use9Bits) UART1_C3 = (UART1_C3 & ~0x40) | ((n & 0x100) >> 2); | if (use9Bits) UART1_C3 = (UART1_C3 & ~0x40) | ((n & 0x100) >> 2); | ||||
| UART1_D = n; | UART1_D = n; |
| // Tunable parameters (relatively safe to edit these numbers) | // Tunable parameters (relatively safe to edit these numbers) | ||||
| //////////////////////////////////////////////////////////////// | //////////////////////////////////////////////////////////////// | ||||
| #define TX_BUFFER_SIZE 40 // number of outgoing bytes to buffer | |||||
| #define RX_BUFFER_SIZE 64 // number of incoming bytes to buffer | |||||
| #ifndef SERIAL3_TX_BUFFER_SIZE | |||||
| #define SERIAL3_TX_BUFFER_SIZE 40 // number of outgoing bytes to buffer | |||||
| #endif | |||||
| #ifndef SERIAL3_RX_BUFFER_SIZE | |||||
| #define SERIAL3_RX_BUFFER_SIZE 64 // number of incoming bytes to buffer | |||||
| #endif | |||||
| #define RTS_HIGH_WATERMARK 40 // RTS requests sender to pause | #define RTS_HIGH_WATERMARK 40 // RTS requests sender to pause | ||||
| #define RTS_LOW_WATERMARK 26 // RTS allows sender to resume | #define RTS_LOW_WATERMARK 26 // RTS allows sender to resume | ||||
| #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest | #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest | ||||
| #define use9Bits 0 | #define use9Bits 0 | ||||
| #endif | #endif | ||||
| static volatile BUFTYPE tx_buffer[TX_BUFFER_SIZE]; | |||||
| static volatile BUFTYPE rx_buffer[RX_BUFFER_SIZE]; | |||||
| static volatile BUFTYPE tx_buffer[SERIAL3_TX_BUFFER_SIZE]; | |||||
| static volatile BUFTYPE rx_buffer[SERIAL3_RX_BUFFER_SIZE]; | |||||
| static volatile uint8_t transmitting = 0; | static volatile uint8_t transmitting = 0; | ||||
| #if defined(KINETISK) | #if defined(KINETISK) | ||||
| static volatile uint8_t *transmit_pin=NULL; | static volatile uint8_t *transmit_pin=NULL; | ||||
| #define rts_assert() *(rts_pin+8) = rts_mask; | #define rts_assert() *(rts_pin+8) = rts_mask; | ||||
| #define rts_deassert() *(rts_pin+4) = rts_mask; | #define rts_deassert() *(rts_pin+4) = rts_mask; | ||||
| #endif | #endif | ||||
| #if TX_BUFFER_SIZE > 255 | |||||
| #if SERIAL3_TX_BUFFER_SIZE > 255 | |||||
| static volatile uint16_t tx_buffer_head = 0; | static volatile uint16_t tx_buffer_head = 0; | ||||
| static volatile uint16_t tx_buffer_tail = 0; | static volatile uint16_t tx_buffer_tail = 0; | ||||
| #else | #else | ||||
| static volatile uint8_t tx_buffer_head = 0; | static volatile uint8_t tx_buffer_head = 0; | ||||
| static volatile uint8_t tx_buffer_tail = 0; | static volatile uint8_t tx_buffer_tail = 0; | ||||
| #endif | #endif | ||||
| #if RX_BUFFER_SIZE > 255 | |||||
| #if SERIAL3_RX_BUFFER_SIZE > 255 | |||||
| static volatile uint16_t rx_buffer_head = 0; | static volatile uint16_t rx_buffer_head = 0; | ||||
| static volatile uint16_t rx_buffer_tail = 0; | static volatile uint16_t rx_buffer_tail = 0; | ||||
| #else | #else | ||||
| if (!(SIM_SCGC4 & SIM_SCGC4_UART2)) return; | if (!(SIM_SCGC4 & SIM_SCGC4_UART2)) return; | ||||
| if (transmit_pin) transmit_assert(); | if (transmit_pin) transmit_assert(); | ||||
| head = tx_buffer_head; | head = tx_buffer_head; | ||||
| if (++head >= TX_BUFFER_SIZE) head = 0; | |||||
| if (++head >= SERIAL3_TX_BUFFER_SIZE) head = 0; | |||||
| while (tx_buffer_tail == head) { | while (tx_buffer_tail == head) { | ||||
| int priority = nvic_execution_priority(); | int priority = nvic_execution_priority(); | ||||
| if (priority <= IRQ_PRIORITY) { | if (priority <= IRQ_PRIORITY) { | ||||
| if ((UART2_S1 & UART_S1_TDRE)) { | if ((UART2_S1 & UART_S1_TDRE)) { | ||||
| uint32_t tail = tx_buffer_tail; | uint32_t tail = tx_buffer_tail; | ||||
| if (++tail >= TX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL3_TX_BUFFER_SIZE) tail = 0; | |||||
| n = tx_buffer[tail]; | n = tx_buffer[tail]; | ||||
| if (use9Bits) UART2_C3 = (UART2_C3 & ~0x40) | ((n & 0x100) >> 2); | if (use9Bits) UART2_C3 = (UART2_C3 & ~0x40) | ((n & 0x100) >> 2); | ||||
| UART2_D = n; | UART2_D = n; | ||||
| head = tx_buffer_head; | head = tx_buffer_head; | ||||
| tail = tx_buffer_tail; | tail = tx_buffer_tail; | ||||
| if (head >= tail) return TX_BUFFER_SIZE - 1 - head + tail; | |||||
| if (head >= tail) return SERIAL3_TX_BUFFER_SIZE - 1 - head + tail; | |||||
| return tail - head - 1; | return tail - head - 1; | ||||
| } | } | ||||
| head = rx_buffer_head; | head = rx_buffer_head; | ||||
| tail = rx_buffer_tail; | tail = rx_buffer_tail; | ||||
| if (head >= tail) return head - tail; | if (head >= tail) return head - tail; | ||||
| return RX_BUFFER_SIZE + head - tail; | |||||
| return SERIAL3_RX_BUFFER_SIZE + head - tail; | |||||
| } | } | ||||
| int serial3_getchar(void) | int serial3_getchar(void) | ||||
| head = rx_buffer_head; | head = rx_buffer_head; | ||||
| tail = rx_buffer_tail; | tail = rx_buffer_tail; | ||||
| if (head == tail) return -1; | if (head == tail) return -1; | ||||
| if (++tail >= RX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL3_RX_BUFFER_SIZE) tail = 0; | |||||
| c = rx_buffer[tail]; | c = rx_buffer[tail]; | ||||
| rx_buffer_tail = tail; | rx_buffer_tail = tail; | ||||
| if (rts_pin) { | if (rts_pin) { | ||||
| int avail; | int avail; | ||||
| if (head >= tail) avail = head - tail; | if (head >= tail) avail = head - tail; | ||||
| else avail = RX_BUFFER_SIZE + head - tail; | |||||
| else avail = SERIAL3_RX_BUFFER_SIZE + head - tail; | |||||
| if (avail <= RTS_LOW_WATERMARK) rts_assert(); | if (avail <= RTS_LOW_WATERMARK) rts_assert(); | ||||
| } | } | ||||
| return c; | return c; | ||||
| head = rx_buffer_head; | head = rx_buffer_head; | ||||
| tail = rx_buffer_tail; | tail = rx_buffer_tail; | ||||
| if (head == tail) return -1; | if (head == tail) return -1; | ||||
| if (++tail >= RX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL3_RX_BUFFER_SIZE) tail = 0; | |||||
| return rx_buffer[tail]; | return rx_buffer[tail]; | ||||
| } | } | ||||
| n = UART2_D; | n = UART2_D; | ||||
| } | } | ||||
| head = rx_buffer_head + 1; | head = rx_buffer_head + 1; | ||||
| if (head >= RX_BUFFER_SIZE) head = 0; | |||||
| if (head >= SERIAL3_RX_BUFFER_SIZE) head = 0; | |||||
| if (head != rx_buffer_tail) { | if (head != rx_buffer_tail) { | ||||
| rx_buffer[head] = n; | rx_buffer[head] = n; | ||||
| rx_buffer_head = head; | rx_buffer_head = head; | ||||
| int avail; | int avail; | ||||
| tail = tx_buffer_tail; | tail = tx_buffer_tail; | ||||
| if (head >= tail) avail = head - tail; | if (head >= tail) avail = head - tail; | ||||
| else avail = RX_BUFFER_SIZE + head - tail; | |||||
| else avail = SERIAL3_RX_BUFFER_SIZE + head - tail; | |||||
| if (avail >= RTS_HIGH_WATERMARK) rts_deassert(); | if (avail >= RTS_HIGH_WATERMARK) rts_deassert(); | ||||
| } | } | ||||
| } | } | ||||
| if (head == tail) { | if (head == tail) { | ||||
| UART2_C2 = C2_TX_COMPLETING; | UART2_C2 = C2_TX_COMPLETING; | ||||
| } else { | } else { | ||||
| if (++tail >= TX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL3_TX_BUFFER_SIZE) tail = 0; | |||||
| n = tx_buffer[tail]; | n = tx_buffer[tail]; | ||||
| if (use9Bits) UART2_C3 = (UART2_C3 & ~0x40) | ((n & 0x100) >> 2); | if (use9Bits) UART2_C3 = (UART2_C3 & ~0x40) | ((n & 0x100) >> 2); | ||||
| UART2_D = n; | UART2_D = n; |
| // Tunable parameters (relatively safe to edit these numbers) | // Tunable parameters (relatively safe to edit these numbers) | ||||
| //////////////////////////////////////////////////////////////// | //////////////////////////////////////////////////////////////// | ||||
| #define TX_BUFFER_SIZE 40 // number of outgoing bytes to buffer | |||||
| #define RX_BUFFER_SIZE 64 // number of incoming bytes to buffer | |||||
| #ifndef SERIAL4_TX_BUFFER_SIZE | |||||
| #define SERIAL4_TX_BUFFER_SIZE 40 // number of outgoing bytes to buffer | |||||
| #endif | |||||
| #ifndef SERIAL4_RX_BUFFER_SIZE | |||||
| #define SERIAL4_RX_BUFFER_SIZE 64 // number of incoming bytes to buffer | |||||
| #endif | |||||
| #define RTS_HIGH_WATERMARK 40 // RTS requests sender to pause | #define RTS_HIGH_WATERMARK 40 // RTS requests sender to pause | ||||
| #define RTS_LOW_WATERMARK 26 // RTS allows sender to resume | #define RTS_LOW_WATERMARK 26 // RTS allows sender to resume | ||||
| #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest | #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest | ||||
| #define use9Bits 0 | #define use9Bits 0 | ||||
| #endif | #endif | ||||
| static volatile BUFTYPE tx_buffer[TX_BUFFER_SIZE]; | |||||
| static volatile BUFTYPE rx_buffer[RX_BUFFER_SIZE]; | |||||
| static volatile BUFTYPE tx_buffer[SERIAL4_TX_BUFFER_SIZE]; | |||||
| static volatile BUFTYPE rx_buffer[SERIAL4_RX_BUFFER_SIZE]; | |||||
| static volatile uint8_t transmitting = 0; | static volatile uint8_t transmitting = 0; | ||||
| static volatile uint8_t *transmit_pin=NULL; | static volatile uint8_t *transmit_pin=NULL; | ||||
| #define transmit_assert() *transmit_pin = 1 | #define transmit_assert() *transmit_pin = 1 | ||||
| static volatile uint8_t *rts_pin=NULL; | static volatile uint8_t *rts_pin=NULL; | ||||
| #define rts_assert() *rts_pin = 0 | #define rts_assert() *rts_pin = 0 | ||||
| #define rts_deassert() *rts_pin = 1 | #define rts_deassert() *rts_pin = 1 | ||||
| #if TX_BUFFER_SIZE > 255 | |||||
| #if SERIAL4_TX_BUFFER_SIZE > 255 | |||||
| static volatile uint16_t tx_buffer_head = 0; | static volatile uint16_t tx_buffer_head = 0; | ||||
| static volatile uint16_t tx_buffer_tail = 0; | static volatile uint16_t tx_buffer_tail = 0; | ||||
| #else | #else | ||||
| static volatile uint8_t tx_buffer_head = 0; | static volatile uint8_t tx_buffer_head = 0; | ||||
| static volatile uint8_t tx_buffer_tail = 0; | static volatile uint8_t tx_buffer_tail = 0; | ||||
| #endif | #endif | ||||
| #if RX_BUFFER_SIZE > 255 | |||||
| #if SERIAL4_RX_BUFFER_SIZE > 255 | |||||
| static volatile uint16_t rx_buffer_head = 0; | static volatile uint16_t rx_buffer_head = 0; | ||||
| static volatile uint16_t rx_buffer_tail = 0; | static volatile uint16_t rx_buffer_tail = 0; | ||||
| #else | #else | ||||
| if (!(SIM_SCGC4 & SIM_SCGC4_UART3)) return; | if (!(SIM_SCGC4 & SIM_SCGC4_UART3)) return; | ||||
| if (transmit_pin) transmit_assert(); | if (transmit_pin) transmit_assert(); | ||||
| head = tx_buffer_head; | head = tx_buffer_head; | ||||
| if (++head >= TX_BUFFER_SIZE) head = 0; | |||||
| if (++head >= SERIAL4_TX_BUFFER_SIZE) head = 0; | |||||
| while (tx_buffer_tail == head) { | while (tx_buffer_tail == head) { | ||||
| int priority = nvic_execution_priority(); | int priority = nvic_execution_priority(); | ||||
| if (priority <= IRQ_PRIORITY) { | if (priority <= IRQ_PRIORITY) { | ||||
| if ((UART3_S1 & UART_S1_TDRE)) { | if ((UART3_S1 & UART_S1_TDRE)) { | ||||
| uint32_t tail = tx_buffer_tail; | uint32_t tail = tx_buffer_tail; | ||||
| if (++tail >= TX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL4_TX_BUFFER_SIZE) tail = 0; | |||||
| n = tx_buffer[tail]; | n = tx_buffer[tail]; | ||||
| if (use9Bits) UART3_C3 = (UART3_C3 & ~0x40) | ((n & 0x100) >> 2); | if (use9Bits) UART3_C3 = (UART3_C3 & ~0x40) | ((n & 0x100) >> 2); | ||||
| UART3_D = n; | UART3_D = n; | ||||
| head = tx_buffer_head; | head = tx_buffer_head; | ||||
| tail = tx_buffer_tail; | tail = tx_buffer_tail; | ||||
| if (head >= tail) return TX_BUFFER_SIZE - 1 - head + tail; | |||||
| if (head >= tail) return SERIAL4_TX_BUFFER_SIZE - 1 - head + tail; | |||||
| return tail - head - 1; | return tail - head - 1; | ||||
| } | } | ||||
| head = rx_buffer_head; | head = rx_buffer_head; | ||||
| tail = rx_buffer_tail; | tail = rx_buffer_tail; | ||||
| if (head >= tail) return head - tail; | if (head >= tail) return head - tail; | ||||
| return RX_BUFFER_SIZE + head - tail; | |||||
| return SERIAL4_RX_BUFFER_SIZE + head - tail; | |||||
| } | } | ||||
| int serial4_getchar(void) | int serial4_getchar(void) | ||||
| head = rx_buffer_head; | head = rx_buffer_head; | ||||
| tail = rx_buffer_tail; | tail = rx_buffer_tail; | ||||
| if (head == tail) return -1; | if (head == tail) return -1; | ||||
| if (++tail >= RX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL4_RX_BUFFER_SIZE) tail = 0; | |||||
| c = rx_buffer[tail]; | c = rx_buffer[tail]; | ||||
| rx_buffer_tail = tail; | rx_buffer_tail = tail; | ||||
| if (rts_pin) { | if (rts_pin) { | ||||
| int avail; | int avail; | ||||
| if (head >= tail) avail = head - tail; | if (head >= tail) avail = head - tail; | ||||
| else avail = RX_BUFFER_SIZE + head - tail; | |||||
| else avail = SERIAL4_RX_BUFFER_SIZE + head - tail; | |||||
| if (avail <= RTS_LOW_WATERMARK) rts_assert(); | if (avail <= RTS_LOW_WATERMARK) rts_assert(); | ||||
| } | } | ||||
| return c; | return c; | ||||
| head = rx_buffer_head; | head = rx_buffer_head; | ||||
| tail = rx_buffer_tail; | tail = rx_buffer_tail; | ||||
| if (head == tail) return -1; | if (head == tail) return -1; | ||||
| if (++tail >= RX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL4_RX_BUFFER_SIZE) tail = 0; | |||||
| return rx_buffer[tail]; | return rx_buffer[tail]; | ||||
| } | } | ||||
| n = UART3_D; | n = UART3_D; | ||||
| } | } | ||||
| head = rx_buffer_head + 1; | head = rx_buffer_head + 1; | ||||
| if (head >= RX_BUFFER_SIZE) head = 0; | |||||
| if (head >= SERIAL4_RX_BUFFER_SIZE) head = 0; | |||||
| if (head != rx_buffer_tail) { | if (head != rx_buffer_tail) { | ||||
| rx_buffer[head] = n; | rx_buffer[head] = n; | ||||
| rx_buffer_head = head; | rx_buffer_head = head; | ||||
| int avail; | int avail; | ||||
| tail = tx_buffer_tail; | tail = tx_buffer_tail; | ||||
| if (head >= tail) avail = head - tail; | if (head >= tail) avail = head - tail; | ||||
| else avail = RX_BUFFER_SIZE + head - tail; | |||||
| else avail = SERIAL4_RX_BUFFER_SIZE + head - tail; | |||||
| if (avail >= RTS_HIGH_WATERMARK) rts_deassert(); | if (avail >= RTS_HIGH_WATERMARK) rts_deassert(); | ||||
| } | } | ||||
| } | } | ||||
| if (head == tail) { | if (head == tail) { | ||||
| UART3_C2 = C2_TX_COMPLETING; | UART3_C2 = C2_TX_COMPLETING; | ||||
| } else { | } else { | ||||
| if (++tail >= TX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL4_TX_BUFFER_SIZE) tail = 0; | |||||
| n = tx_buffer[tail]; | n = tx_buffer[tail]; | ||||
| if (use9Bits) UART3_C3 = (UART3_C3 & ~0x40) | ((n & 0x100) >> 2); | if (use9Bits) UART3_C3 = (UART3_C3 & ~0x40) | ((n & 0x100) >> 2); | ||||
| UART3_D = n; | UART3_D = n; |
| // Tunable parameters (relatively safe to edit these numbers) | // Tunable parameters (relatively safe to edit these numbers) | ||||
| //////////////////////////////////////////////////////////////// | //////////////////////////////////////////////////////////////// | ||||
| #define TX_BUFFER_SIZE 40 // number of outgoing bytes to buffer | |||||
| #define RX_BUFFER_SIZE 64 // number of incoming bytes to buffer | |||||
| #ifndef SERIAL5_TX_BUFFER_SIZE | |||||
| #define SERIAL5_TX_BUFFER_SIZE 40 // number of outgoing bytes to buffer | |||||
| #endif | |||||
| #ifndef SERIAL5_RX_BUFFER_SIZE | |||||
| #define SERIAL5_RX_BUFFER_SIZE 64 // number of incoming bytes to buffer | |||||
| #endif | |||||
| #define RTS_HIGH_WATERMARK 40 // RTS requests sender to pause | #define RTS_HIGH_WATERMARK 40 // RTS requests sender to pause | ||||
| #define RTS_LOW_WATERMARK 26 // RTS allows sender to resume | #define RTS_LOW_WATERMARK 26 // RTS allows sender to resume | ||||
| #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest | #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest | ||||
| #define use9Bits 0 | #define use9Bits 0 | ||||
| #endif | #endif | ||||
| static volatile BUFTYPE tx_buffer[TX_BUFFER_SIZE]; | |||||
| static volatile BUFTYPE rx_buffer[RX_BUFFER_SIZE]; | |||||
| static volatile BUFTYPE tx_buffer[SERIAL5_TX_BUFFER_SIZE]; | |||||
| static volatile BUFTYPE rx_buffer[SERIAL5_RX_BUFFER_SIZE]; | |||||
| static volatile uint8_t transmitting = 0; | static volatile uint8_t transmitting = 0; | ||||
| static volatile uint8_t *transmit_pin=NULL; | static volatile uint8_t *transmit_pin=NULL; | ||||
| #define transmit_assert() *transmit_pin = 1 | #define transmit_assert() *transmit_pin = 1 | ||||
| static volatile uint8_t *rts_pin=NULL; | static volatile uint8_t *rts_pin=NULL; | ||||
| #define rts_assert() *rts_pin = 0 | #define rts_assert() *rts_pin = 0 | ||||
| #define rts_deassert() *rts_pin = 1 | #define rts_deassert() *rts_pin = 1 | ||||
| #if TX_BUFFER_SIZE > 255 | |||||
| #if SERIAL5_TX_BUFFER_SIZE > 255 | |||||
| static volatile uint16_t tx_buffer_head = 0; | static volatile uint16_t tx_buffer_head = 0; | ||||
| static volatile uint16_t tx_buffer_tail = 0; | static volatile uint16_t tx_buffer_tail = 0; | ||||
| #else | #else | ||||
| static volatile uint8_t tx_buffer_head = 0; | static volatile uint8_t tx_buffer_head = 0; | ||||
| static volatile uint8_t tx_buffer_tail = 0; | static volatile uint8_t tx_buffer_tail = 0; | ||||
| #endif | #endif | ||||
| #if RX_BUFFER_SIZE > 255 | |||||
| #if SERIAL5_RX_BUFFER_SIZE > 255 | |||||
| static volatile uint16_t rx_buffer_head = 0; | static volatile uint16_t rx_buffer_head = 0; | ||||
| static volatile uint16_t rx_buffer_tail = 0; | static volatile uint16_t rx_buffer_tail = 0; | ||||
| #else | #else | ||||
| if (!(SIM_SCGC1 & SIM_SCGC1_UART4)) return; | if (!(SIM_SCGC1 & SIM_SCGC1_UART4)) return; | ||||
| if (transmit_pin) transmit_assert(); | if (transmit_pin) transmit_assert(); | ||||
| head = tx_buffer_head; | head = tx_buffer_head; | ||||
| if (++head >= TX_BUFFER_SIZE) head = 0; | |||||
| if (++head >= SERIAL5_TX_BUFFER_SIZE) head = 0; | |||||
| while (tx_buffer_tail == head) { | while (tx_buffer_tail == head) { | ||||
| int priority = nvic_execution_priority(); | int priority = nvic_execution_priority(); | ||||
| if (priority <= IRQ_PRIORITY) { | if (priority <= IRQ_PRIORITY) { | ||||
| if ((UART4_S1 & UART_S1_TDRE)) { | if ((UART4_S1 & UART_S1_TDRE)) { | ||||
| uint32_t tail = tx_buffer_tail; | uint32_t tail = tx_buffer_tail; | ||||
| if (++tail >= TX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL5_TX_BUFFER_SIZE) tail = 0; | |||||
| n = tx_buffer[tail]; | n = tx_buffer[tail]; | ||||
| if (use9Bits) UART4_C3 = (UART4_C3 & ~0x40) | ((n & 0x100) >> 2); | if (use9Bits) UART4_C3 = (UART4_C3 & ~0x40) | ((n & 0x100) >> 2); | ||||
| UART4_D = n; | UART4_D = n; | ||||
| head = tx_buffer_head; | head = tx_buffer_head; | ||||
| tail = tx_buffer_tail; | tail = tx_buffer_tail; | ||||
| if (head >= tail) return TX_BUFFER_SIZE - 1 - head + tail; | |||||
| if (head >= tail) return SERIAL5_TX_BUFFER_SIZE - 1 - head + tail; | |||||
| return tail - head - 1; | return tail - head - 1; | ||||
| } | } | ||||
| head = rx_buffer_head; | head = rx_buffer_head; | ||||
| tail = rx_buffer_tail; | tail = rx_buffer_tail; | ||||
| if (head >= tail) return head - tail; | if (head >= tail) return head - tail; | ||||
| return RX_BUFFER_SIZE + head - tail; | |||||
| return SERIAL5_RX_BUFFER_SIZE + head - tail; | |||||
| } | } | ||||
| int serial5_getchar(void) | int serial5_getchar(void) | ||||
| head = rx_buffer_head; | head = rx_buffer_head; | ||||
| tail = rx_buffer_tail; | tail = rx_buffer_tail; | ||||
| if (head == tail) return -1; | if (head == tail) return -1; | ||||
| if (++tail >= RX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL5_RX_BUFFER_SIZE) tail = 0; | |||||
| c = rx_buffer[tail]; | c = rx_buffer[tail]; | ||||
| rx_buffer_tail = tail; | rx_buffer_tail = tail; | ||||
| if (rts_pin) { | if (rts_pin) { | ||||
| int avail; | int avail; | ||||
| if (head >= tail) avail = head - tail; | if (head >= tail) avail = head - tail; | ||||
| else avail = RX_BUFFER_SIZE + head - tail; | |||||
| else avail = SERIAL5_RX_BUFFER_SIZE + head - tail; | |||||
| if (avail <= RTS_LOW_WATERMARK) rts_assert(); | if (avail <= RTS_LOW_WATERMARK) rts_assert(); | ||||
| } | } | ||||
| return c; | return c; | ||||
| head = rx_buffer_head; | head = rx_buffer_head; | ||||
| tail = rx_buffer_tail; | tail = rx_buffer_tail; | ||||
| if (head == tail) return -1; | if (head == tail) return -1; | ||||
| if (++tail >= RX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL5_RX_BUFFER_SIZE) tail = 0; | |||||
| return rx_buffer[tail]; | return rx_buffer[tail]; | ||||
| } | } | ||||
| n = UART4_D; | n = UART4_D; | ||||
| } | } | ||||
| head = rx_buffer_head + 1; | head = rx_buffer_head + 1; | ||||
| if (head >= RX_BUFFER_SIZE) head = 0; | |||||
| if (head >= SERIAL5_RX_BUFFER_SIZE) head = 0; | |||||
| if (head != rx_buffer_tail) { | if (head != rx_buffer_tail) { | ||||
| rx_buffer[head] = n; | rx_buffer[head] = n; | ||||
| rx_buffer_head = head; | rx_buffer_head = head; | ||||
| int avail; | int avail; | ||||
| tail = tx_buffer_tail; | tail = tx_buffer_tail; | ||||
| if (head >= tail) avail = head - tail; | if (head >= tail) avail = head - tail; | ||||
| else avail = RX_BUFFER_SIZE + head - tail; | |||||
| else avail = SERIAL5_RX_BUFFER_SIZE + head - tail; | |||||
| if (avail >= RTS_HIGH_WATERMARK) rts_deassert(); | if (avail >= RTS_HIGH_WATERMARK) rts_deassert(); | ||||
| } | } | ||||
| } | } | ||||
| if (head == tail) { | if (head == tail) { | ||||
| UART4_C2 = C2_TX_COMPLETING; | UART4_C2 = C2_TX_COMPLETING; | ||||
| } else { | } else { | ||||
| if (++tail >= TX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL5_TX_BUFFER_SIZE) tail = 0; | |||||
| n = tx_buffer[tail]; | n = tx_buffer[tail]; | ||||
| if (use9Bits) UART4_C3 = (UART4_C3 & ~0x40) | ((n & 0x100) >> 2); | if (use9Bits) UART4_C3 = (UART4_C3 & ~0x40) | ((n & 0x100) >> 2); | ||||
| UART4_D = n; | UART4_D = n; |
| // Tunable parameters (relatively safe to edit these numbers) | // Tunable parameters (relatively safe to edit these numbers) | ||||
| //////////////////////////////////////////////////////////////// | //////////////////////////////////////////////////////////////// | ||||
| #define TX_BUFFER_SIZE 40 // number of outgoing bytes to buffer | |||||
| #define RX_BUFFER_SIZE 64 // number of incoming bytes to buffer | |||||
| #ifndef SERIAL6_TX_BUFFER_SIZE | |||||
| #define SERIAL6_TX_BUFFER_SIZE 40 // number of outgoing bytes to buffer | |||||
| #endif | |||||
| #ifndef SERIAL6_RX_BUFFER_SIZE | |||||
| #define SERIAL6_RX_BUFFER_SIZE 64 // number of incoming bytes to buffer | |||||
| #endif | |||||
| #define RTS_HIGH_WATERMARK 40 // RTS requests sender to pause | #define RTS_HIGH_WATERMARK 40 // RTS requests sender to pause | ||||
| #define RTS_LOW_WATERMARK 26 // RTS allows sender to resume | #define RTS_LOW_WATERMARK 26 // RTS allows sender to resume | ||||
| #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest | #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest | ||||
| #define use9Bits 0 | #define use9Bits 0 | ||||
| #endif | #endif | ||||
| static volatile BUFTYPE tx_buffer[TX_BUFFER_SIZE]; | |||||
| static volatile BUFTYPE rx_buffer[RX_BUFFER_SIZE]; | |||||
| static volatile BUFTYPE tx_buffer[SERIAL6_TX_BUFFER_SIZE]; | |||||
| static volatile BUFTYPE rx_buffer[SERIAL6_RX_BUFFER_SIZE]; | |||||
| static volatile uint8_t transmitting = 0; | static volatile uint8_t transmitting = 0; | ||||
| static volatile uint8_t *transmit_pin=NULL; | static volatile uint8_t *transmit_pin=NULL; | ||||
| #define transmit_assert() *transmit_pin = 1 | #define transmit_assert() *transmit_pin = 1 | ||||
| static volatile uint8_t *rts_pin=NULL; | static volatile uint8_t *rts_pin=NULL; | ||||
| #define rts_assert() *rts_pin = 0 | #define rts_assert() *rts_pin = 0 | ||||
| #define rts_deassert() *rts_pin = 1 | #define rts_deassert() *rts_pin = 1 | ||||
| #if TX_BUFFER_SIZE > 255 | |||||
| #if SERIAL6_TX_BUFFER_SIZE > 255 | |||||
| static volatile uint16_t tx_buffer_head = 0; | static volatile uint16_t tx_buffer_head = 0; | ||||
| static volatile uint16_t tx_buffer_tail = 0; | static volatile uint16_t tx_buffer_tail = 0; | ||||
| #else | #else | ||||
| static volatile uint8_t tx_buffer_head = 0; | static volatile uint8_t tx_buffer_head = 0; | ||||
| static volatile uint8_t tx_buffer_tail = 0; | static volatile uint8_t tx_buffer_tail = 0; | ||||
| #endif | #endif | ||||
| #if RX_BUFFER_SIZE > 255 | |||||
| #if SERIAL6_RX_BUFFER_SIZE > 255 | |||||
| static volatile uint16_t rx_buffer_head = 0; | static volatile uint16_t rx_buffer_head = 0; | ||||
| static volatile uint16_t rx_buffer_tail = 0; | static volatile uint16_t rx_buffer_tail = 0; | ||||
| #else | #else | ||||
| if (!(SIM_SCGC1 & SIM_SCGC1_UART5)) return; | if (!(SIM_SCGC1 & SIM_SCGC1_UART5)) return; | ||||
| if (transmit_pin) transmit_assert(); | if (transmit_pin) transmit_assert(); | ||||
| head = tx_buffer_head; | head = tx_buffer_head; | ||||
| if (++head >= TX_BUFFER_SIZE) head = 0; | |||||
| if (++head >= SERIAL6_TX_BUFFER_SIZE) head = 0; | |||||
| while (tx_buffer_tail == head) { | while (tx_buffer_tail == head) { | ||||
| int priority = nvic_execution_priority(); | int priority = nvic_execution_priority(); | ||||
| if (priority <= IRQ_PRIORITY) { | if (priority <= IRQ_PRIORITY) { | ||||
| if ((UART5_S1 & UART_S1_TDRE)) { | if ((UART5_S1 & UART_S1_TDRE)) { | ||||
| uint32_t tail = tx_buffer_tail; | uint32_t tail = tx_buffer_tail; | ||||
| if (++tail >= TX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL6_TX_BUFFER_SIZE) tail = 0; | |||||
| n = tx_buffer[tail]; | n = tx_buffer[tail]; | ||||
| if (use9Bits) UART5_C3 = (UART5_C3 & ~0x40) | ((n & 0x100) >> 2); | if (use9Bits) UART5_C3 = (UART5_C3 & ~0x40) | ((n & 0x100) >> 2); | ||||
| UART5_D = n; | UART5_D = n; | ||||
| head = tx_buffer_head; | head = tx_buffer_head; | ||||
| tail = tx_buffer_tail; | tail = tx_buffer_tail; | ||||
| if (head >= tail) return TX_BUFFER_SIZE - 1 - head + tail; | |||||
| if (head >= tail) return SERIAL6_TX_BUFFER_SIZE - 1 - head + tail; | |||||
| return tail - head - 1; | return tail - head - 1; | ||||
| } | } | ||||
| head = rx_buffer_head; | head = rx_buffer_head; | ||||
| tail = rx_buffer_tail; | tail = rx_buffer_tail; | ||||
| if (head >= tail) return head - tail; | if (head >= tail) return head - tail; | ||||
| return RX_BUFFER_SIZE + head - tail; | |||||
| return SERIAL6_RX_BUFFER_SIZE + head - tail; | |||||
| } | } | ||||
| int serial6_getchar(void) | int serial6_getchar(void) | ||||
| head = rx_buffer_head; | head = rx_buffer_head; | ||||
| tail = rx_buffer_tail; | tail = rx_buffer_tail; | ||||
| if (head == tail) return -1; | if (head == tail) return -1; | ||||
| if (++tail >= RX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL6_RX_BUFFER_SIZE) tail = 0; | |||||
| c = rx_buffer[tail]; | c = rx_buffer[tail]; | ||||
| rx_buffer_tail = tail; | rx_buffer_tail = tail; | ||||
| if (rts_pin) { | if (rts_pin) { | ||||
| int avail; | int avail; | ||||
| if (head >= tail) avail = head - tail; | if (head >= tail) avail = head - tail; | ||||
| else avail = RX_BUFFER_SIZE + head - tail; | |||||
| else avail = SERIAL6_RX_BUFFER_SIZE + head - tail; | |||||
| if (avail <= RTS_LOW_WATERMARK) rts_assert(); | if (avail <= RTS_LOW_WATERMARK) rts_assert(); | ||||
| } | } | ||||
| return c; | return c; | ||||
| head = rx_buffer_head; | head = rx_buffer_head; | ||||
| tail = rx_buffer_tail; | tail = rx_buffer_tail; | ||||
| if (head == tail) return -1; | if (head == tail) return -1; | ||||
| if (++tail >= RX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL6_RX_BUFFER_SIZE) tail = 0; | |||||
| return rx_buffer[tail]; | return rx_buffer[tail]; | ||||
| } | } | ||||
| n = UART5_D; | n = UART5_D; | ||||
| } | } | ||||
| head = rx_buffer_head + 1; | head = rx_buffer_head + 1; | ||||
| if (head >= RX_BUFFER_SIZE) head = 0; | |||||
| if (head >= SERIAL6_RX_BUFFER_SIZE) head = 0; | |||||
| if (head != rx_buffer_tail) { | if (head != rx_buffer_tail) { | ||||
| rx_buffer[head] = n; | rx_buffer[head] = n; | ||||
| rx_buffer_head = head; | rx_buffer_head = head; | ||||
| int avail; | int avail; | ||||
| tail = tx_buffer_tail; | tail = tx_buffer_tail; | ||||
| if (head >= tail) avail = head - tail; | if (head >= tail) avail = head - tail; | ||||
| else avail = RX_BUFFER_SIZE + head - tail; | |||||
| else avail = SERIAL6_RX_BUFFER_SIZE + head - tail; | |||||
| if (avail >= RTS_HIGH_WATERMARK) rts_deassert(); | if (avail >= RTS_HIGH_WATERMARK) rts_deassert(); | ||||
| } | } | ||||
| } | } | ||||
| if (head == tail) { | if (head == tail) { | ||||
| UART5_C2 = C2_TX_COMPLETING; | UART5_C2 = C2_TX_COMPLETING; | ||||
| } else { | } else { | ||||
| if (++tail >= TX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL6_TX_BUFFER_SIZE) tail = 0; | |||||
| n = tx_buffer[tail]; | n = tx_buffer[tail]; | ||||
| if (use9Bits) UART5_C3 = (UART5_C3 & ~0x40) | ((n & 0x100) >> 2); | if (use9Bits) UART5_C3 = (UART5_C3 & ~0x40) | ((n & 0x100) >> 2); | ||||
| UART5_D = n; | UART5_D = n; |
| // Tunable parameters (relatively safe to edit these numbers) | // Tunable parameters (relatively safe to edit these numbers) | ||||
| //////////////////////////////////////////////////////////////// | //////////////////////////////////////////////////////////////// | ||||
| #define TX_BUFFER_SIZE 40 // number of outgoing bytes to buffer | |||||
| #define RX_BUFFER_SIZE 64 // number of incoming bytes to buffer | |||||
| #ifndef SERIAL6_TX_BUFFER_SIZE | |||||
| #define SERIAL6_TX_BUFFER_SIZE 40 // number of outgoing bytes to buffer | |||||
| #endif | |||||
| #ifndef SERIAL6_RX_BUFFER_SIZE | |||||
| #define SERIAL6_RX_BUFFER_SIZE 64 // number of incoming bytes to buffer | |||||
| #endif | |||||
| #define RTS_HIGH_WATERMARK 40 // RTS requests sender to pause | #define RTS_HIGH_WATERMARK 40 // RTS requests sender to pause | ||||
| #define RTS_LOW_WATERMARK 26 // RTS allows sender to resume | #define RTS_LOW_WATERMARK 26 // RTS allows sender to resume | ||||
| #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest | #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest | ||||
| #define use9Bits 0 | #define use9Bits 0 | ||||
| #endif | #endif | ||||
| static volatile BUFTYPE tx_buffer[TX_BUFFER_SIZE]; | |||||
| static volatile BUFTYPE rx_buffer[RX_BUFFER_SIZE]; | |||||
| static volatile BUFTYPE tx_buffer[SERIAL6_TX_BUFFER_SIZE]; | |||||
| static volatile BUFTYPE rx_buffer[SERIAL6_RX_BUFFER_SIZE]; | |||||
| static volatile uint8_t transmitting = 0; | static volatile uint8_t transmitting = 0; | ||||
| static volatile uint8_t *transmit_pin=NULL; | static volatile uint8_t *transmit_pin=NULL; | ||||
| #define transmit_assert() *transmit_pin = 1 | #define transmit_assert() *transmit_pin = 1 | ||||
| static volatile uint8_t *rts_pin=NULL; | static volatile uint8_t *rts_pin=NULL; | ||||
| #define rts_assert() *rts_pin = 0 | #define rts_assert() *rts_pin = 0 | ||||
| #define rts_deassert() *rts_pin = 1 | #define rts_deassert() *rts_pin = 1 | ||||
| #if TX_BUFFER_SIZE > 255 | |||||
| #if SERIAL6_TX_BUFFER_SIZE > 255 | |||||
| static volatile uint16_t tx_buffer_head = 0; | static volatile uint16_t tx_buffer_head = 0; | ||||
| static volatile uint16_t tx_buffer_tail = 0; | static volatile uint16_t tx_buffer_tail = 0; | ||||
| #else | #else | ||||
| static volatile uint8_t tx_buffer_head = 0; | static volatile uint8_t tx_buffer_head = 0; | ||||
| static volatile uint8_t tx_buffer_tail = 0; | static volatile uint8_t tx_buffer_tail = 0; | ||||
| #endif | #endif | ||||
| #if RX_BUFFER_SIZE > 255 | |||||
| #if SERIAL6_RX_BUFFER_SIZE > 255 | |||||
| static volatile uint16_t rx_buffer_head = 0; | static volatile uint16_t rx_buffer_head = 0; | ||||
| static volatile uint16_t rx_buffer_tail = 0; | static volatile uint16_t rx_buffer_tail = 0; | ||||
| #else | #else | ||||
| if (!(SIM_SCGC2 & SIM_SCGC2_LPUART0)) return; | if (!(SIM_SCGC2 & SIM_SCGC2_LPUART0)) return; | ||||
| if (transmit_pin) transmit_assert(); | if (transmit_pin) transmit_assert(); | ||||
| head = tx_buffer_head; | head = tx_buffer_head; | ||||
| if (++head >= TX_BUFFER_SIZE) head = 0; | |||||
| if (++head >= SERIAL6_TX_BUFFER_SIZE) head = 0; | |||||
| while (tx_buffer_tail == head) { | while (tx_buffer_tail == head) { | ||||
| int priority = nvic_execution_priority(); | int priority = nvic_execution_priority(); | ||||
| if (priority <= IRQ_PRIORITY) { | if (priority <= IRQ_PRIORITY) { | ||||
| if ((LPUART0_STAT & LPUART_STAT_TDRE)) { | if ((LPUART0_STAT & LPUART_STAT_TDRE)) { | ||||
| uint32_t tail = tx_buffer_tail; | uint32_t tail = tx_buffer_tail; | ||||
| if (++tail >= TX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL6_TX_BUFFER_SIZE) tail = 0; | |||||
| n = tx_buffer[tail]; | n = tx_buffer[tail]; | ||||
| //if (use9Bits) UART5_C3 = (UART5_C3 & ~0x40) | ((n & 0x100) >> 2); | //if (use9Bits) UART5_C3 = (UART5_C3 & ~0x40) | ((n & 0x100) >> 2); | ||||
| LPUART0_DATA = n; | LPUART0_DATA = n; | ||||
| head = tx_buffer_head; | head = tx_buffer_head; | ||||
| tail = tx_buffer_tail; | tail = tx_buffer_tail; | ||||
| if (head >= tail) return TX_BUFFER_SIZE - 1 - head + tail; | |||||
| if (head >= tail) return SERIAL6_TX_BUFFER_SIZE - 1 - head + tail; | |||||
| return tail - head - 1; | return tail - head - 1; | ||||
| } | } | ||||
| head = rx_buffer_head; | head = rx_buffer_head; | ||||
| tail = rx_buffer_tail; | tail = rx_buffer_tail; | ||||
| if (head >= tail) return head - tail; | if (head >= tail) return head - tail; | ||||
| return RX_BUFFER_SIZE + head - tail; | |||||
| return SERIAL6_RX_BUFFER_SIZE + head - tail; | |||||
| } | } | ||||
| int serial6_getchar(void) | int serial6_getchar(void) | ||||
| head = rx_buffer_head; | head = rx_buffer_head; | ||||
| tail = rx_buffer_tail; | tail = rx_buffer_tail; | ||||
| if (head == tail) return -1; | if (head == tail) return -1; | ||||
| if (++tail >= RX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL6_RX_BUFFER_SIZE) tail = 0; | |||||
| c = rx_buffer[tail]; | c = rx_buffer[tail]; | ||||
| rx_buffer_tail = tail; | rx_buffer_tail = tail; | ||||
| if (rts_pin) { | if (rts_pin) { | ||||
| int avail; | int avail; | ||||
| if (head >= tail) avail = head - tail; | if (head >= tail) avail = head - tail; | ||||
| else avail = RX_BUFFER_SIZE + head - tail; | |||||
| else avail = SERIAL6_RX_BUFFER_SIZE + head - tail; | |||||
| if (avail <= RTS_LOW_WATERMARK) rts_assert(); | if (avail <= RTS_LOW_WATERMARK) rts_assert(); | ||||
| } | } | ||||
| return c; | return c; | ||||
| head = rx_buffer_head; | head = rx_buffer_head; | ||||
| tail = rx_buffer_tail; | tail = rx_buffer_tail; | ||||
| if (head == tail) return -1; | if (head == tail) return -1; | ||||
| if (++tail >= RX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL6_RX_BUFFER_SIZE) tail = 0; | |||||
| return rx_buffer[tail]; | return rx_buffer[tail]; | ||||
| } | } | ||||
| // } | // } | ||||
| n = LPUART0_DATA & 0x3ff; // use only the 10 data bits | n = LPUART0_DATA & 0x3ff; // use only the 10 data bits | ||||
| head = rx_buffer_head + 1; | head = rx_buffer_head + 1; | ||||
| if (head >= RX_BUFFER_SIZE) head = 0; | |||||
| if (head >= SERIAL6_RX_BUFFER_SIZE) head = 0; | |||||
| if (head != rx_buffer_tail) { | if (head != rx_buffer_tail) { | ||||
| rx_buffer[head] = n; | rx_buffer[head] = n; | ||||
| rx_buffer_head = head; | rx_buffer_head = head; | ||||
| int avail; | int avail; | ||||
| tail = tx_buffer_tail; | tail = tx_buffer_tail; | ||||
| if (head >= tail) avail = head - tail; | if (head >= tail) avail = head - tail; | ||||
| else avail = RX_BUFFER_SIZE + head - tail; | |||||
| else avail = SERIAL6_RX_BUFFER_SIZE + head - tail; | |||||
| if (avail >= RTS_HIGH_WATERMARK) rts_deassert(); | if (avail >= RTS_HIGH_WATERMARK) rts_deassert(); | ||||
| } | } | ||||
| } | } | ||||
| //LPUART0_CTRL &= ~LPUART_CTRL_TIE; | //LPUART0_CTRL &= ~LPUART_CTRL_TIE; | ||||
| //LPUART0_CTRL |= LPUART_CTRL_TCIE; // Actually wondering if we can just leave this one on... | //LPUART0_CTRL |= LPUART_CTRL_TCIE; // Actually wondering if we can just leave this one on... | ||||
| } else { | } else { | ||||
| if (++tail >= TX_BUFFER_SIZE) tail = 0; | |||||
| if (++tail >= SERIAL6_TX_BUFFER_SIZE) tail = 0; | |||||
| n = tx_buffer[tail]; | n = tx_buffer[tail]; | ||||
| //if (use9Bits) UART5_C3 = (UART5_C3 & ~0x40) | ((n & 0x100) >> 2); | //if (use9Bits) UART5_C3 = (UART5_C3 & ~0x40) | ((n & 0x100) >> 2); | ||||
| LPUART0_DATA = n; | LPUART0_DATA = n; |