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Merge pull request #205 from thewknd/serial-fix

fix serial5_set_tx and serial6_set_tx
teensy4-core
Paul Stoffregen 8 年之前
父節點
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c020d5e5c7
共有 3 個檔案被更改,包括 8 行新增8 行删除
  1. +2
    -2
      teensy3/serial5.c
  2. +2
    -2
      teensy3/serial6.c
  3. +4
    -4
      teensy3/serial6_lpuart.c

+ 2
- 2
teensy3/serial5.c 查看文件

@@ -85,7 +85,7 @@ static volatile uint8_t rx_buffer_head = 0;
static volatile uint8_t rx_buffer_tail = 0;
#endif

static uint8_t tx_pin_num = 34;
static uint8_t tx_pin_num = 33;

// UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS
// UART0 has 8 byte fifo, UART1 and UART2 have 1 byte buffer
@@ -171,7 +171,7 @@ void serial5_set_tx(uint8_t pin, uint8_t opendrain)

if (opendrain) pin |= 128;
if (pin == tx_pin_num) return;
if ((SIM_SCGC4 & SIM_SCGC4_UART2)) {
if ((SIM_SCGC1 & SIM_SCGC1_UART4)) {
switch (tx_pin_num & 127) {
case 33: CORE_PIN33_CONFIG = 0; break; // PTE24
}

+ 2
- 2
teensy3/serial6.c 查看文件

@@ -85,7 +85,7 @@ static volatile uint8_t rx_buffer_head = 0;
static volatile uint8_t rx_buffer_tail = 0;
#endif

static uint8_t tx_pin_num = 34;
static uint8_t tx_pin_num = 48;

// UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS
// UART0 has 8 byte fifo, UART1 and UART2 have 1 byte buffer
@@ -171,7 +171,7 @@ void serial6_set_tx(uint8_t pin, uint8_t opendrain)

if (opendrain) pin |= 128;
if (pin == tx_pin_num) return;
if ((SIM_SCGC4 & SIM_SCGC4_UART2)) {
if ((SIM_SCGC1 |= SIM_SCGC1_UART5)) {
switch (tx_pin_num & 127) {
case 48: CORE_PIN48_CONFIG = 0; break; // PTE24
}

+ 4
- 4
teensy3/serial6_lpuart.c 查看文件

@@ -93,7 +93,7 @@ static volatile uint8_t rx_buffer_head = 0;
static volatile uint8_t rx_buffer_tail = 0;
#endif

static uint8_t tx_pin_num = 34;
static uint8_t tx_pin_num = 48;

// UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS
// UART0 has 8 byte fifo, UART1 and UART2 have 1 byte buffer
@@ -254,7 +254,7 @@ void serial6_set_tx(uint8_t pin, uint8_t opendrain)

if (opendrain) pin |= 128;
if (pin == tx_pin_num) return;
if ((SIM_SCGC4 & SIM_SCGC4_UART2)) {
if ((SIM_SCGC2 & SIM_SCGC2_LPUART0)) {
switch (tx_pin_num & 127) {
case 48: CORE_PIN48_CONFIG = 0; break; // PTE24
}
@@ -264,7 +264,7 @@ void serial6_set_tx(uint8_t pin, uint8_t opendrain)
cfg = PORT_PCR_DSE | PORT_PCR_SRE;
}
switch (pin & 127) {
case 48: CORE_PIN48_CONFIG = cfg | PORT_PCR_MUX(3); break;
case 48: CORE_PIN48_CONFIG = cfg | PORT_PCR_MUX(5); break;
}
}
tx_pin_num = pin;
@@ -292,7 +292,7 @@ int serial6_set_cts(uint8_t pin)
{
if (!(SIM_SCGC2 & SIM_SCGC2_LPUART0)) return 0;
if (pin == 56) {
CORE_PIN56_CONFIG = PORT_PCR_MUX(3) | PORT_PCR_PE; // weak pulldown
CORE_PIN56_CONFIG = PORT_PCR_MUX(5) | PORT_PCR_PE; // weak pulldown
} else {
UART5_MODEM &= ~UART_MODEM_TXCTSE;
return 0;

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