fix serial5_set_tx and serial6_set_txteensy4-core
static volatile uint8_t rx_buffer_tail = 0; | static volatile uint8_t rx_buffer_tail = 0; | ||||
#endif | #endif | ||||
static uint8_t tx_pin_num = 34; | |||||
static uint8_t tx_pin_num = 33; | |||||
// UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS | // UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS | ||||
// UART0 has 8 byte fifo, UART1 and UART2 have 1 byte buffer | // UART0 has 8 byte fifo, UART1 and UART2 have 1 byte buffer | ||||
if (opendrain) pin |= 128; | if (opendrain) pin |= 128; | ||||
if (pin == tx_pin_num) return; | if (pin == tx_pin_num) return; | ||||
if ((SIM_SCGC4 & SIM_SCGC4_UART2)) { | |||||
if ((SIM_SCGC1 & SIM_SCGC1_UART4)) { | |||||
switch (tx_pin_num & 127) { | switch (tx_pin_num & 127) { | ||||
case 33: CORE_PIN33_CONFIG = 0; break; // PTE24 | case 33: CORE_PIN33_CONFIG = 0; break; // PTE24 | ||||
} | } |
static volatile uint8_t rx_buffer_tail = 0; | static volatile uint8_t rx_buffer_tail = 0; | ||||
#endif | #endif | ||||
static uint8_t tx_pin_num = 34; | |||||
static uint8_t tx_pin_num = 48; | |||||
// UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS | // UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS | ||||
// UART0 has 8 byte fifo, UART1 and UART2 have 1 byte buffer | // UART0 has 8 byte fifo, UART1 and UART2 have 1 byte buffer | ||||
if (opendrain) pin |= 128; | if (opendrain) pin |= 128; | ||||
if (pin == tx_pin_num) return; | if (pin == tx_pin_num) return; | ||||
if ((SIM_SCGC4 & SIM_SCGC4_UART2)) { | |||||
if ((SIM_SCGC1 |= SIM_SCGC1_UART5)) { | |||||
switch (tx_pin_num & 127) { | switch (tx_pin_num & 127) { | ||||
case 48: CORE_PIN48_CONFIG = 0; break; // PTE24 | case 48: CORE_PIN48_CONFIG = 0; break; // PTE24 | ||||
} | } |
static volatile uint8_t rx_buffer_tail = 0; | static volatile uint8_t rx_buffer_tail = 0; | ||||
#endif | #endif | ||||
static uint8_t tx_pin_num = 34; | |||||
static uint8_t tx_pin_num = 48; | |||||
// UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS | // UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS | ||||
// UART0 has 8 byte fifo, UART1 and UART2 have 1 byte buffer | // UART0 has 8 byte fifo, UART1 and UART2 have 1 byte buffer | ||||
if (opendrain) pin |= 128; | if (opendrain) pin |= 128; | ||||
if (pin == tx_pin_num) return; | if (pin == tx_pin_num) return; | ||||
if ((SIM_SCGC4 & SIM_SCGC4_UART2)) { | |||||
if ((SIM_SCGC2 & SIM_SCGC2_LPUART0)) { | |||||
switch (tx_pin_num & 127) { | switch (tx_pin_num & 127) { | ||||
case 48: CORE_PIN48_CONFIG = 0; break; // PTE24 | case 48: CORE_PIN48_CONFIG = 0; break; // PTE24 | ||||
} | } | ||||
cfg = PORT_PCR_DSE | PORT_PCR_SRE; | cfg = PORT_PCR_DSE | PORT_PCR_SRE; | ||||
} | } | ||||
switch (pin & 127) { | switch (pin & 127) { | ||||
case 48: CORE_PIN48_CONFIG = cfg | PORT_PCR_MUX(3); break; | |||||
case 48: CORE_PIN48_CONFIG = cfg | PORT_PCR_MUX(5); break; | |||||
} | } | ||||
} | } | ||||
tx_pin_num = pin; | tx_pin_num = pin; | ||||
{ | { | ||||
if (!(SIM_SCGC2 & SIM_SCGC2_LPUART0)) return 0; | if (!(SIM_SCGC2 & SIM_SCGC2_LPUART0)) return 0; | ||||
if (pin == 56) { | if (pin == 56) { | ||||
CORE_PIN56_CONFIG = PORT_PCR_MUX(3) | PORT_PCR_PE; // weak pulldown | |||||
CORE_PIN56_CONFIG = PORT_PCR_MUX(5) | PORT_PCR_PE; // weak pulldown | |||||
} else { | } else { | ||||
UART5_MODEM &= ~UART_MODEM_TXCTSE; | UART5_MODEM &= ~UART_MODEM_TXCTSE; | ||||
return 0; | return 0; |