Needed to add new Define for clock gate

Plus defines to use the new clock gate, plus correct case name for the
serial6 isr to match what is in system isr table

The T-LC and the new beta boards T3.6 and soon T3.5 hardware uarts have
ability to turn on 2 stop bits.  So enabled on these boards.

This is a WIP,  But I have now been able to create Serial6 on T3.4 beta,
and so far have tested Send/Receive basic stuff at 115200 and have tried
at several CPU speeds in MHZ (192, 216, 180, 120, 96)

Just in case the extra pads are added to bottom of 3.4/3.5 board,
define is in place...

Added define for SPI1 registers

fixes 136

50.6.2 SCAN Control register

Bug found by Chronologist, https://forum.pjrc.com/threads/29624-Using-TSI-for-capacitance-measurement

https://forum.pjrc.com/threads/25153-PDB0CH1-register-definitions

- Added bit definitions for the PIT
- limited Teensy LC to only two PITs
- added PIT_LTMR64 for Teensy LC