Fix Serial6 for Teensy 3.5

Needed to add new Define for clock gate

Plus defines to use the new clock gate, plus correct case name for the
serial6 isr to match what is in system isr table

When concat is same string to string, use memcpy

https://forum.pjrc.com/threads/35688-Something-wrong-with-Adding-a-String-to-itself!?p=111109#post111109

Enable Uart 2 stop bit capabilities

The T-LC and the new beta boards T3.6 and soon T3.5 hardware uarts have
ability to turn on 2 stop bits.  So enabled on these boards.

Beta Board names Change

Ser2 ser4 fixes

Was using UART2, should be UART3

On T3.2 if you do something like:
Serial2.setTX(31);
Serial2.setRX(26);
Serial2.begin(.9600);
...
Serial2.end();

It will on the end call will always reconfigure pins 9 and 10 to be
digital pins MUX = 1

Add serialEvent6 to yield

fixes #159

T3 5 beta serial6

missed pin 26 in SPIFIFO

Make update of these flags be hopefully interrupt safe

This is a WIP,  But I have now been able to create Serial6 on T3.4 beta,
and so far have tested Send/Receive basic stuff at 115200 and have tried
at several CPU speeds in MHZ (192, 216, 180, 120, 96)

T T3.4 T3.5 SPI2 support

trigger mode enable cmp register def

Serial2.setTx and Serial2.setRX should check Uart1

These two functions were checking (SIM_SCGC4 & SIM_SCGC4_UART2)
and should be testing (SIM_SCGC4 & SIM_SCGC4_UART1)

fix SDHC_XFERTYP_RSPTYP

fixes #145

Spi1 defined

PulseIn on LC issue

PulseIn may fail on LC as it is using *reg to test the value for on or
off, but on LC register is a bitmask associated with several IO pins.
So split off for LC to use the MASK value for the pin to test high and
low.

Warning did not update timings for this,  which may be necessary as adds
an & in the loop.  However when I tried TLC for 5000us timeout, it timed
out with 5138us, if I decremented the PULSEIN_LOOPS_PER_USEC by one,
then it timed out at 4398... This was at 49mhz.

Set FlexBus Clock Divider to correct value for 16, 8, 4 MHz