Swapped Core_Pin0_Padconfig and Pin1 pad config to match pin outs

Fix Bug - CSR_DONE be cleared to write the MAJORELINK or ESG bits

Page 982.
Fixes https://forum.pjrc.com/threads/54711-Teensy-4-0-First-Beta-Test?p=196233&viewfull=1#post196233
- maybe this is needed for T3x, too? too late here to check this now.

Update to my fork

t4 FLEXIO register masks are 32 bits

The FlexIO registers are 32 bits, the masks were all setup for 16 bits so the high word of registers were not updated

Drop CPU speed and TEMP when faulted offline

Update pwm.c

pwm.c: fix warnings

warning: 'flexpwm' may be used uninitialized in this function [-Wmaybe-uninitialized]
warning: 'qtimer' may be used uninitialized in this function [-Wmaybe-uninitialized]

Fix PFDs

CCmicros - micros version using Cycle counter

This fixes the PFDs for PLL2 - by default, it has totally wrong values. This sets the frequencies according to the diagram on Page 676.

The same fix is needed for PLL3 - I have code (same structure), but it does not work - Do have have any hints for me?
Is PLL3 even running? I not, can we start it? Or, if i is running - at which frequency, and  is there any non-std config?

for micros() Use: ARM Synchronization Primitives, include of arm_math.h

Get systick_isr data safely without disable interrupts, uses systick_safe_read as indicator variable

Stream find fix handle more cases

Stream find Bugfix

micros() unchanged - minor systick_isr() diversion - one line added to systick_isr.

T4 - SPI - Create structure

update FASTRUN

This saves a cycle - and checks both values to avoid _isr change of either value based on code/execution

Replace micros for one using CycCnt

Alternate micros() extends millis() using ARM_DWT_CYCCNT
> Also makes unused_interrupt_vector() weak to allow user override like Teensy3

align(32) funct_table for faster access

Add NULL func to disable debug

digitalWriteFast bugfix