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Teensy 4.1 core updated for C++20
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teensy-core-4.1/include/core/avr_emulation.h

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  1. /* Teensyduino Core Library

  2.  * http://www.pjrc.com/teensy/

  3.  * Copyright (c) 2019 PJRC.COM, LLC.

  4.  *

  5.  * Permission is hereby granted, free of charge, to any person obtaining

  6.  * a copy of this software and associated documentation files (the

  7.  * "Software"), to deal in the Software without restriction, including

  8.  * without limitation the rights to use, copy, modify, merge, publish,

  9.  * distribute, sublicense, and/or sell copies of the Software, and to

  10.  * permit persons to whom the Software is furnished to do so, subject to

  11.  * the following conditions:

  12.  *

  13.  * 1. The above copyright notice and this permission notice shall be

  14.  * included in all copies or substantial portions of the Software.

  15.  *

  16.  * 2. If the Software is incorporated into a build system that allows

  17.  * selection among a list of target devices, then similar target

  18.  * devices manufactured by PJRC.COM must be included in the list of

  19.  * target devices and selectable in the same manner.

  20.  *

  21.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

  22.  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

  23.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

  24.  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS

  25.  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN

  26.  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

  27.  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

  28.  * SOFTWARE.

  29.  */

  30. 

  31. #ifndef _avr_emulation_h_

  32. #define _avr_emulation_h_

  33. 

  34. #include "core/imxrt.h"

  35. #include "core/core_pins.h"

  36. #include "core/pins_arduino.h"

  37. 

  38. #ifdef __cplusplus

  39. 

  40. 

  41. // bitband addressing for atomic access to data direction register

  42. static inline void GPIO_SETBIT_ATOMIC(volatile uint32_t *reg, uint32_t mask) {

  43. 	__disable_irq();

  44. 	*reg |= mask;

  45. 	__enable_irq();

  46. }

  47. 

  48. static inline void GPIO_CLRBIT_ATOMIC(volatile uint32_t *reg, uint32_t mask) {

  49. 	__disable_irq();

  50. 	*reg &= ~mask;

  51. 	__enable_irq();

  52. }

  53. 

  54. #define CONFIG_PULLUP ( IOMUXC_PAD_DSE(7) | IOMUXC_PAD_PKE | IOMUXC_PAD_PUE | IOMUXC_PAD_PUS(3) | IOMUXC_PAD_HYS )

  55. #define CONFIG_NOPULLUP ( IOMUXC_PAD_DSE(7))

  56. 

  57. 

  58. // SPI Control Register ­ SPCR

  59. #define SPIE	7	// SPI Interrupt Enable - not supported

  60. #define SPE	6	// SPI Enable

  61. #define DORD	5	// DORD: Data Order

  62. #define MSTR	4	// MSTR: Master/Slave Select

  63. #define CPOL	3	// CPOL: Clock Polarity

  64. #define CPHA	2	// CPHA: Clock Phase

  65. #define SPR1	1	// Clock: 3 = 125 kHz, 2 = 250 kHz, 1 = 1 MHz, 0->4 MHz

  66. #define SPR0	0

  67. // SPI Status Register ­ SPSR

  68. #define SPIF	7	// SPIF: SPI Interrupt Flag

  69. #define WCOL	6	// WCOL: Write COLlision Flag - not implemented

  70. #define SPI2X	0	// SPI2X: Double SPI Speed Bit

  71. // SPI Data Register ­ SPDR

  72. 

  73. 

  74. class SPCRemulation;

  75. class SPSRemulation;

  76. class SPDRemulation;

  77. 

  78. class SPCRemulation

  79. {

  80. public:

  81. 	inline SPCRemulation & operator = (int val) __attribute__((always_inline)) {

  82. /*

  83. 		uint32_t ctar, mcr, sim6;

  84. 		//serial_print("SPCR=");

  85. 		//serial_phex(val);

  86. 		//serial_print("\n");

  87. 		sim6 = SIM_SCGC6;

  88. 		if (!(sim6 & SIM_SCGC6_SPI0)) {

  89. 			//serial_print("init1\n");

  90. 			SIM_SCGC6 = sim6 | SIM_SCGC6_SPI0;

  91. 			SPI0_CTAR0 = SPI_CTAR_FMSZ(7) | SPI_CTAR_PBR(1) | SPI_CTAR_BR(1) | SPI_CTAR_CSSCK(1);

  92. 		}

  93. 		if (!(val & (1<<SPE))) {

  94. 			SPI0_MCR |= SPI_MCR_MDIS; // TODO: use bitband for atomic access

  95. 		}

  96. 		ctar = SPI_CTAR_FMSZ(7) | SPI_CTAR_PBR(1);

  97. 		if (val & (1<<DORD))  ctar |= SPI_CTAR_LSBFE;

  98. 		if (val & (1<<CPOL))  ctar |= SPI_CTAR_CPOL;

  99. 		if (val & (1<<CPHA)) {

  100. 			ctar |= SPI_CTAR_CPHA;

  101. 			if ((val & 3) == 0) {

  102. 				ctar |= SPI_CTAR_BR(1) | SPI_CTAR_ASC(1);

  103. 			} else if ((val & 3) == 1) {

  104. 				ctar |= SPI_CTAR_BR(4) | SPI_CTAR_ASC(4);

  105. 			} else if ((val & 3) == 2) {

  106. 				ctar |= SPI_CTAR_BR(6) | SPI_CTAR_ASC(6);

  107. 			} else {

  108. 				ctar |= SPI_CTAR_BR(7) | SPI_CTAR_ASC(7);

  109. 			}

  110. 		} else {

  111. 			if ((val & 3) == 0) {

  112. 				ctar |= SPI_CTAR_BR(1) | SPI_CTAR_CSSCK(1);

  113. 			} else if ((val & 3) == 1) {

  114. 				ctar |= SPI_CTAR_BR(4) | SPI_CTAR_CSSCK(4);

  115. 			} else if ((val & 3) == 2) {

  116. 				ctar |= SPI_CTAR_BR(6) | SPI_CTAR_CSSCK(6);

  117. 			} else {

  118. 				ctar |= SPI_CTAR_BR(7) | SPI_CTAR_CSSCK(7);

  119. 			}

  120. 		}

  121. 		ctar |= (SPI0_CTAR0 & SPI_CTAR_DBR);

  122. 		update_ctar(ctar);

  123. 		mcr = SPI_MCR_DCONF(0) | SPI_MCR_PCSIS(0x1F);

  124. 		if (val & (1<<MSTR)) mcr |= SPI_MCR_MSTR;

  125. 		if (val & (1<<SPE)) {

  126. 			mcr &= ~(SPI_MCR_MDIS | SPI_MCR_HALT);

  127. 			SPI0_MCR = mcr;

  128. 			enable_pins();

  129. 		} else {

  130. 			mcr |= (SPI_MCR_MDIS | SPI_MCR_HALT);

  131. 			SPI0_MCR = mcr;

  132. 			disable_pins();

  133. 		}

  134. 		//serial_print("MCR:");

  135. 		//serial_phex32(SPI0_MCR);

  136. 		//serial_print(", CTAR0:");

  137. 		//serial_phex32(SPI0_CTAR0);

  138. 		//serial_print("\n");

  139. */

  140. 		return *this;

  141. 	}

  142. 	inline SPCRemulation & operator |= (int val) __attribute__((always_inline)) {

  143. /*

  144. 		uint32_t sim6;

  145. 		//serial_print("SPCR |= ");

  146. 		//serial_phex(val);

  147. 		//serial_print("\n");

  148. 		sim6 = SIM_SCGC6;

  149. 		if (!(sim6 & SIM_SCGC6_SPI0)) {

  150. 			//serial_print("init2\n");

  151. 			SIM_SCGC6 = sim6 | SIM_SCGC6_SPI0;

  152. 			SPI0_CTAR0 = SPI_CTAR_FMSZ(7) | SPI_CTAR_PBR(1) | SPI_CTAR_BR(1);

  153. 		}

  154. 		if (val & ((1<<DORD)|(1<<CPOL)|(1<<CPHA)|3)) {

  155. 			uint32_t ctar = SPI0_CTAR0;

  156. 			if (val & (1<<DORD)) ctar |= SPI_CTAR_LSBFE; // TODO: use bitband

  157. 			if (val & (1<<CPOL)) ctar |= SPI_CTAR_CPOL;

  158. 			if (val & (1<<CPHA) && !(ctar & SPI_CTAR_CPHA)) {

  159. 				ctar |= SPI_CTAR_CPHA;

  160. 				ctar &= 0xFFFF00FF;

  161. 				ctar |= SPI_CTAR_ASC(ctar & 15);

  162. 			}

  163. 			if ((val & 3) != 0) {

  164. 				uint32_t br = ctar & 15;

  165. 				uint32_t priorval;

  166. 				if (br <= 1) priorval = 0;

  167. 				else if (br <= 4) priorval = 1;

  168. 				else if (br <= 6) priorval = 2;

  169. 				else priorval = 3;

  170. 				uint32_t newval = priorval | (val & 3);

  171. 				if (newval != priorval) {

  172. 					if (newval == 0) br = 1;

  173. 					else if (newval == 0) br = 4;

  174. 					else if (newval == 0) br = 6;

  175. 					else br = 7;

  176. 					ctar &= 0xFFFF00F0; // clear BR, ASC, CSSCK

  177. 					if ((ctar & SPI_CTAR_CPHA)) {

  178. 						ctar |= SPI_CTAR_BR(br) | SPI_CTAR_ASC(br);

  179. 					} else {

  180. 						ctar |= SPI_CTAR_BR(br) | SPI_CTAR_CSSCK(br);

  181. 					}

  182. 				}

  183. 			}

  184. 			update_ctar(ctar);

  185. 		}

  186. 		if (val & (1<<MSTR)) SPI0_MCR |= SPI_MCR_MSTR;

  187. 		if (val & (1<<SPE)) {

  188. 			SPI0_MCR &= ~(SPI_MCR_MDIS | SPI_MCR_HALT);

  189. 			enable_pins();

  190. 		}

  191. 		//serial_print("MCR:");

  192. 		//serial_phex32(SPI0_MCR);

  193. 		//serial_print(", CTAR0:");

  194. 		//serial_phex32(SPI0_CTAR0);

  195. 		//serial_print("\n");

  196. */

  197. 		return *this;

  198. 	}

  199. 	inline SPCRemulation & operator &= (int val) __attribute__((always_inline)) {

  200. /*

  201. 		//serial_print("SPCR &= ");

  202. 		//serial_phex(val);

  203. 		//serial_print("\n");

  204. 		SIM_SCGC6 |= SIM_SCGC6_SPI0;

  205. 		if (!(val & (1<<SPE))) {

  206. 			SPI0_MCR |= (SPI_MCR_MDIS | SPI_MCR_HALT);

  207. 			disable_pins();

  208. 		}

  209. 		if ((val & ((1<<DORD)|(1<<CPOL)|(1<<CPHA)|3)) != ((1<<DORD)|(1<<CPOL)|(1<<CPHA)|3)) {

  210. 			uint32_t ctar = SPI0_CTAR0;

  211. 			if (!(val & (1<<DORD))) ctar &= ~SPI_CTAR_LSBFE; // TODO: use bitband

  212. 			if (!(val & (1<<CPOL))) ctar &= ~SPI_CTAR_CPOL;

  213. 			if (!(val & (1<<CPHA)) && (ctar & SPI_CTAR_CPHA)) {

  214. 				ctar &= ~SPI_CTAR_CPHA;

  215. 				ctar &= 0xFFFF00FF;

  216. 				ctar |= SPI_CTAR_CSSCK(ctar & 15);

  217. 			}

  218. 			if ((val & 3) != 3) {

  219. 				uint32_t br = ctar & 15;

  220. 				uint32_t priorval;

  221. 				if (br <= 1) priorval = 0;

  222. 				else if (br <= 4) priorval = 1;

  223. 				else if (br <= 6) priorval = 2;

  224. 				else priorval = 3;

  225. 				uint32_t newval = priorval & (val & 3);

  226. 				if (newval != priorval) {

  227. 					if (newval == 0) br = 1;

  228. 					else if (newval == 0) br = 4;

  229. 					else if (newval == 0) br = 6;

  230. 					else br = 7;

  231. 					ctar &= 0xFFFF00F0; // clear BR, ASC, CSSCK

  232. 					if ((ctar & SPI_CTAR_CPHA)) {

  233. 						ctar |= SPI_CTAR_BR(br) | SPI_CTAR_ASC(br);

  234. 					} else {

  235. 						ctar |= SPI_CTAR_BR(br) | SPI_CTAR_CSSCK(br);

  236. 					}

  237. 				}

  238. 			}

  239. 			update_ctar(ctar);

  240. 		}

  241. 		if (!(val & (1<<MSTR))) SPI0_MCR &= ~SPI_MCR_MSTR;

  242. */

  243. 		return *this;

  244. 	}

  245. 	inline int operator & (int val) const __attribute__((always_inline)) {

  246. 		int ret = 0;

  247. /*		

  248. 		//serial_print("SPCR & ");

  249. 		//serial_phex(val);

  250. 		//serial_print("\n");

  251. 		SIM_SCGC6 |= SIM_SCGC6_SPI0;

  252. 		if ((val & (1<<DORD)) && (SPI0_CTAR0 & SPI_CTAR_LSBFE)) ret |= (1<<DORD);

  253. 		if ((val & (1<<CPOL)) && (SPI0_CTAR0 & SPI_CTAR_CPOL)) ret |= (1<<CPOL);

  254. 		if ((val & (1<<CPHA)) && (SPI0_CTAR0 & SPI_CTAR_CPHA)) ret |= (1<<CPHA);

  255. 		if ((val & 3) != 0) {

  256. 			uint32_t dbr = SPI0_CTAR0 & 15;

  257. 			uint32_t spr10;

  258. 			if (dbr <= 1) {

  259. 				spr10 = 0;

  260. 			} else if (dbr <= 4) {

  261. 				spr10 |= (1<<SPR0);

  262. 			} else if (dbr <= 6) {

  263. 				spr10 |= (1<<SPR1);

  264. 			} else {

  265. 				spr10 |= (1<<SPR1)|(1<<SPR0);

  266. 			}

  267. 			ret |= spr10 & (val & 3);

  268. 		}

  269. 		if (val & (1<<SPE) && (!(SPI0_MCR & SPI_MCR_MDIS))) ret |= (1<<SPE);

  270. 		if (val & (1<<MSTR) && (SPI0_MCR & SPI_MCR_MSTR)) ret |= (1<<MSTR);

  271. 		//serial_print("ret = ");

  272. 		//serial_phex(ret);

  273. 		//serial_print("\n");

  274. */

  275. 		return ret;

  276. 	}

  277. 	operator int () const __attribute__((always_inline)) {

  278. 		int ret = 0;

  279. /*		

  280. 		if ((SIM_SCGC6 & SIM_SCGC6_SPI0)) {

  281. 			int ctar = SPI0_CTAR0;

  282. 			if (ctar & SPI_CTAR_LSBFE) ret |= (1<<DORD);

  283. 			if (ctar & SPI_CTAR_CPOL) ret |= (1<<CPOL);

  284. 			if (ctar & SPI_CTAR_CPHA) ret |= (1<<CPHA);

  285. 			ctar &= 15;

  286. 			if (ctar <= 1) {

  287. 			} else if (ctar <= 4) {

  288. 				ret |= (1<<SPR0);

  289. 			} else if (ctar <= 6) {

  290. 				ret |= (1<<SPR1);

  291. 			} else {

  292. 				ret |= (1<<SPR1)|(1<<SPR0);

  293. 			}

  294. 			int mcr = SPI0_MCR;

  295. 			if (!(mcr & SPI_MCR_MDIS)) ret |= (1<<SPE);

  296. 			if (mcr & SPI_MCR_MSTR) ret |= (1<<MSTR);

  297. 		}

  298. */

  299. 		return ret;

  300. 	}

  301. 	inline void setMOSI(uint8_t pin) __attribute__((always_inline)) {

  302. 	}

  303. 	inline void setMOSI_soft(uint8_t pin) __attribute__((always_inline)) {

  304. 	}

  305. 	inline void setMISO(uint8_t pin) __attribute__((always_inline)) {

  306. 	}

  307. 	inline void setSCK(uint8_t pin) __attribute__((always_inline)) {

  308. 	}

  309. 	friend class SPSRemulation;

  310. 	friend class SPIFIFOclass;

  311. private:

  312. 	static uint8_t pinout;

  313. public:

  314. 	inline void enable_pins(void) __attribute__((always_inline)) {

  315. 		//serial_print("enable_pins\n");

  316. 	}

  317. 	inline void disable_pins(void) __attribute__((always_inline)) {

  318. 	}

  319. };

  320. extern SPCRemulation SPCR;

  321. 

  322. 

  323. class SPSRemulation

  324. {

  325. public:

  326. 	inline SPSRemulation & operator = (int val) __attribute__((always_inline)) {

  327. 		//serial_print("SPSR=");

  328. 		//serial_phex(val);

  329. 		//serial_print("\n");

  330. /*

  331. 		uint32_t ctar = SPI0_CTAR0;

  332. 		if (val & (1<<SPI2X)) {

  333. 			ctar |= SPI_CTAR_DBR;

  334. 		} else {

  335. 			ctar &= ~SPI_CTAR_DBR;

  336. 		}

  337. 		SPCRemulation::update_ctar(ctar);

  338. 		//serial_print("MCR:");

  339. 		//serial_phex32(SPI0_MCR);

  340. 		//serial_print(", CTAR0:");

  341. 		//serial_phex32(SPI0_CTAR0);

  342. 		//serial_print("\n");

  343. */		

  344. 		return *this;

  345. 	}

  346. 	inline SPSRemulation & operator |= (int val) __attribute__((always_inline)) {

  347. /*

  348. 		//serial_print("SPSR |= ");

  349. 		//serial_phex(val);

  350. 		//serial_print("\n");

  351. 		if (val & (1<<SPI2X)) SPCRemulation::update_ctar(SPI0_CTAR0 |= SPI_CTAR_DBR);

  352. */

  353. 		return *this;

  354. 	}

  355. 	inline SPSRemulation & operator &= (int val) __attribute__((always_inline)) {

  356. /*

  357. 		//serial_print("SPSR &= ");

  358. 		//serial_phex(val);

  359. 		//serial_print("\n");

  360. 		if (!(val & (1<<SPI2X))) SPCRemulation::update_ctar(SPI0_CTAR0 &= ~SPI_CTAR_DBR);

  361. */

  362. 		return *this;

  363. 	}

  364. 	inline int operator & (int val) const __attribute__((always_inline)) {

  365. 		int ret = 0;

  366. 		//serial_print("SPSR & ");

  367. 		//serial_phex(val);

  368. 		//serial_print("\n");

  369. 		// TODO: using SPI_SR_TCF isn't quite right.  Control returns to the

  370. 		// caller after the final edge that captures data, which is 1/2 cycle

  371. 		// sooner than AVR returns.  At 500 kHz and slower SPI, this can make

  372. 		// a difference when digitalWrite is used to manually control the CS

  373. 		// pin, and perhaps it could matter at high clocks if faster register

  374. 		// access is used?  But does it really matter?  Do any SPI chips in

  375. 		// practice really perform differently if CS negates early, after the

  376. 		// final bit is clocked, but before the end of the whole clock cycle?

  377. 		if ((val & (1<<SPIF)) && ((LPSPI4_RSR & LPSPI_RSR_RXEMPTY) == 0)) ret = (1<<SPIF);

  378. 		//if ((val & (1<<SPI2X)) && (SPI0_CTAR0 & SPI_CTAR_DBR)) ret |= (1<<SPI2X);

  379. 		//delayMicroseconds(50000);

  380. 		return ret;

  381. 	}

  382. 	operator int () const __attribute__((always_inline)) {

  383. 		int ret = 0;

  384. 		//serial_print("SPSR (int)\n");

  385. 		if ((LPSPI4_RSR & LPSPI_RSR_RXEMPTY) == 0) ret = (1<<SPIF);

  386. 		//if (SPI0_CTAR0 & SPI_CTAR_DBR) ret |= (1<<SPI2X);

  387. 		return ret;

  388. 	}

  389. };

  390. extern SPSRemulation SPSR;

  391. 

  392. class SPDRemulation

  393. {

  394. public:

  395. 	inline SPDRemulation & operator = (int val) __attribute__((always_inline)) {

  396. 		//serial_print("SPDR = ");

  397. 		//serial_phex(val);

  398. 		//serial_print("\n");

  399. 		LPSPI4_CR = LPSPI_CR_RRF | LPSPI_CR_MEN;	// Module enabled anc clear the receive. 

  400. 		LPSPI4_TDR = (val & 255);

  401. 		return *this;

  402. 	}

  403. 	operator int () const __attribute__((always_inline)) {

  404. 		uint32_t val;

  405. 		val = LPSPI4_RDR & 255;

  406. 		return val;

  407. 	}

  408. };

  409. extern SPDRemulation SPDR;

  410. 

  411. class PORTDemulation

  412. {

  413. public:

  414. 	inline PORTDemulation & operator = (int val) __attribute__((always_inline)) {

  415. 		digitalWriteFast(0, (val & (1<<0)));

  416. 		if (!(CORE_PIN0_DDRREG & CORE_PIN0_BITMASK))

  417. 			CORE_PIN0_PADCONFIG = ((val & (1<<0)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  418. 		digitalWriteFast(1, (val & (1<<1)));

  419. 		if (!(CORE_PIN1_DDRREG & CORE_PIN1_BITMASK))

  420. 			CORE_PIN1_PADCONFIG = ((val & (1<<1)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  421. 		digitalWriteFast(2, (val & (1<<2)));

  422. 		if (!(CORE_PIN2_DDRREG & CORE_PIN2_BITMASK))

  423. 			CORE_PIN2_PADCONFIG = ((val & (1<<2)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  424. 		digitalWriteFast(3, (val & (1<<3)));

  425. 		if (!(CORE_PIN3_DDRREG & CORE_PIN3_BITMASK))

  426. 			CORE_PIN3_PADCONFIG = ((val & (1<<3)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  427. 		digitalWriteFast(4, (val & (1<<4)));

  428. 		if (!(CORE_PIN4_DDRREG & CORE_PIN4_BITMASK))

  429. 			CORE_PIN4_PADCONFIG = ((val & (1<<4)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  430. 		digitalWriteFast(5, (val & (1<<5)));

  431. 		if (!(CORE_PIN5_DDRREG & CORE_PIN5_BITMASK))

  432. 			CORE_PIN5_PADCONFIG = ((val & (1<<5)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  433. 		digitalWriteFast(6, (val & (1<<6)));

  434. 		if (!(CORE_PIN6_DDRREG & CORE_PIN6_BITMASK))

  435. 			CORE_PIN6_PADCONFIG = ((val & (1<<6)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  436. 		digitalWriteFast(7, (val & (1<<7)));

  437. 		if (!(CORE_PIN7_DDRREG & CORE_PIN7_BITMASK))

  438. 			CORE_PIN7_PADCONFIG = ((val & (1<<7)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  439. 		return *this;

  440. 	}

  441. 	inline PORTDemulation & operator |= (int val) __attribute__((always_inline)) {

  442. 		if (val & (1<<0)) {

  443. 			digitalWriteFast(0, HIGH);

  444. 			if (!(CORE_PIN0_DDRREG & CORE_PIN0_BITMASK)) CORE_PIN0_CONFIG = CONFIG_PULLUP;

  445. 		}

  446. 		if (val & (1<<1)) {

  447. 			digitalWriteFast(1, HIGH);

  448. 			if (!(CORE_PIN1_DDRREG & CORE_PIN1_BITMASK)) CORE_PIN1_CONFIG = CONFIG_PULLUP;

  449. 		}

  450. 		if (val & (1<<2)) {

  451. 			digitalWriteFast(2, HIGH);

  452. 			if (!(CORE_PIN2_DDRREG & CORE_PIN2_BITMASK)) CORE_PIN2_CONFIG = CONFIG_PULLUP;

  453. 		}

  454. 		if (val & (1<<3)) {

  455. 			digitalWriteFast(3, HIGH);

  456. 			if (!(CORE_PIN3_DDRREG & CORE_PIN3_BITMASK)) CORE_PIN3_CONFIG = CONFIG_PULLUP;

  457. 		}

  458. 		if (val & (1<<4)) {

  459. 			digitalWriteFast(4, HIGH);

  460. 			if (!(CORE_PIN4_DDRREG & CORE_PIN4_BITMASK)) CORE_PIN4_CONFIG = CONFIG_PULLUP;

  461. 		}

  462. 		if (val & (1<<5)) {

  463. 			digitalWriteFast(5, HIGH);

  464. 			if (!(CORE_PIN5_DDRREG & CORE_PIN5_BITMASK)) CORE_PIN5_CONFIG = CONFIG_PULLUP;

  465. 		}

  466. 		if (val & (1<<6)) {

  467. 			digitalWriteFast(6, HIGH);

  468. 			if (!(CORE_PIN6_DDRREG & CORE_PIN6_BITMASK)) CORE_PIN6_CONFIG = CONFIG_PULLUP;

  469. 		}

  470. 		if (val & (1<<7)) {

  471. 			digitalWriteFast(7, HIGH);

  472. 			if (!(CORE_PIN7_DDRREG & CORE_PIN7_BITMASK)) CORE_PIN7_CONFIG = CONFIG_PULLUP;

  473. 		}

  474. 		return *this;

  475. 	}

  476. 	inline PORTDemulation & operator &= (int val) __attribute__((always_inline)) {

  477. 		if (!(val & (1<<0))) {

  478. 			digitalWriteFast(0, LOW);

  479. 			if (!(CORE_PIN0_DDRREG & CORE_PIN0_BITMASK)) CORE_PIN0_CONFIG = CONFIG_NOPULLUP;

  480. 		}

  481. 		if (!(val & (1<<1))) {

  482. 			digitalWriteFast(1, LOW);

  483. 			if (!(CORE_PIN1_DDRREG & CORE_PIN1_BITMASK)) CORE_PIN1_CONFIG = CONFIG_NOPULLUP;

  484. 		}

  485. 		if (!(val & (1<<2))) {

  486. 			digitalWriteFast(2, LOW);

  487. 			if (!(CORE_PIN2_DDRREG & CORE_PIN2_BITMASK)) CORE_PIN2_CONFIG = CONFIG_NOPULLUP;

  488. 		}

  489. 		if (!(val & (1<<3))) {

  490. 			digitalWriteFast(3, LOW);

  491. 			if (!(CORE_PIN3_DDRREG & CORE_PIN3_BITMASK)) CORE_PIN3_CONFIG = CONFIG_NOPULLUP;

  492. 		}

  493. 		if (!(val & (1<<4))) {

  494. 			digitalWriteFast(4, LOW);

  495. 			if (!(CORE_PIN4_DDRREG & CORE_PIN4_BITMASK)) CORE_PIN4_CONFIG = CONFIG_NOPULLUP;

  496. 		}

  497. 		if (!(val & (1<<5))) {

  498. 			digitalWriteFast(5, LOW);

  499. 			if (!(CORE_PIN5_DDRREG & CORE_PIN5_BITMASK)) CORE_PIN5_CONFIG = CONFIG_NOPULLUP;

  500. 		}

  501. 		if (!(val & (1<<6))) {

  502. 			digitalWriteFast(6, LOW);

  503. 			if (!(CORE_PIN6_DDRREG & CORE_PIN6_BITMASK)) CORE_PIN6_CONFIG = CONFIG_NOPULLUP;

  504. 		}

  505. 		if (!(val & (1<<7))) {

  506. 			digitalWriteFast(7, LOW);

  507. 			if (!(CORE_PIN7_DDRREG & CORE_PIN7_BITMASK)) CORE_PIN7_CONFIG = CONFIG_NOPULLUP;

  508. 		}

  509. 		return *this;

  510. 	}

  511. };

  512. extern PORTDemulation PORTD;

  513. 

  514. class PINDemulation

  515. {

  516. public:

  517. 	inline int operator & (int val) const __attribute__((always_inline)) {

  518. 		int ret = 0;

  519. 		if ((val & (1<<0)) && digitalReadFast(0)) ret |= (1<<0);

  520. 		if ((val & (1<<1)) && digitalReadFast(1)) ret |= (1<<1);

  521. 		if ((val & (1<<2)) && digitalReadFast(2)) ret |= (1<<2);

  522. 		if ((val & (1<<3)) && digitalReadFast(3)) ret |= (1<<3);

  523. 		if ((val & (1<<4)) && digitalReadFast(4)) ret |= (1<<4);

  524. 		if ((val & (1<<5)) && digitalReadFast(5)) ret |= (1<<5);

  525. 		if ((val & (1<<6)) && digitalReadFast(6)) ret |= (1<<6);

  526. 		if ((val & (1<<7)) && digitalReadFast(7)) ret |= (1<<7);

  527. 		return ret;

  528. 	}

  529. 	operator int () const __attribute__((always_inline)) {

  530. 		int ret = 0;

  531. 		if (digitalReadFast(0)) ret |= (1<<0);

  532. 		if (digitalReadFast(1)) ret |= (1<<1);

  533. 		if (digitalReadFast(2)) ret |= (1<<2);

  534. 		if (digitalReadFast(3)) ret |= (1<<3);

  535. 		if (digitalReadFast(4)) ret |= (1<<4);

  536. 		if (digitalReadFast(5)) ret |= (1<<5);

  537. 		if (digitalReadFast(6)) ret |= (1<<6);

  538. 		if (digitalReadFast(7)) ret |= (1<<7);

  539. 		return ret;

  540. 	}

  541. };

  542. extern PINDemulation PIND;

  543. 

  544. class DDRDemulation

  545. {

  546. public:

  547. 	inline DDRDemulation & operator = (int val) __attribute__((always_inline)) {

  548. 		if (val & (1<<0)) set0(); else clr0();

  549. 		if (val & (1<<1)) set1(); else clr1();

  550. 		if (val & (1<<2)) set2(); else clr2();

  551. 		if (val & (1<<3)) set3(); else clr3();

  552. 		if (val & (1<<4)) set4(); else clr4();

  553. 		if (val & (1<<5)) set5(); else clr5();

  554. 		if (val & (1<<6)) set6(); else clr6();

  555. 		if (val & (1<<7)) set7(); else clr7();

  556. 		return *this;

  557. 	}

  558. 	inline DDRDemulation & operator |= (int val) __attribute__((always_inline)) {

  559. 		if (val & (1<<0)) set0();

  560. 		if (val & (1<<1)) set1();

  561. 		if (val & (1<<2)) set2();

  562. 		if (val & (1<<3)) set3();

  563. 		if (val & (1<<4)) set4();

  564. 		if (val & (1<<5)) set5();

  565. 		if (val & (1<<6)) set6();

  566. 		if (val & (1<<7)) set7();

  567. 		return *this;

  568. 	}

  569. 	inline DDRDemulation & operator &= (int val) __attribute__((always_inline)) {

  570. 		if (!(val & (1<<0))) clr0();

  571. 		if (!(val & (1<<1))) clr1();

  572. 		if (!(val & (1<<2))) clr2();

  573. 		if (!(val & (1<<3))) clr3();

  574. 		if (!(val & (1<<4))) clr4();

  575. 		if (!(val & (1<<5))) clr5();

  576. 		if (!(val & (1<<6))) clr6();

  577. 		if (!(val & (1<<7))) clr7();

  578. 		return *this;

  579. 	}

  580. private:

  581. 	inline void set0() __attribute__((always_inline)) {

  582. 		GPIO_SETBIT_ATOMIC(&CORE_PIN0_DDRREG, CORE_PIN0_BITMASK);

  583. 		CORE_PIN0_CONFIG = 5 | 0x10;

  584. 		CORE_PIN0_PADCONFIG = CONFIG_PULLUP;

  585. 	}

  586. 	inline void set1() __attribute__((always_inline)) {

  587. 		GPIO_SETBIT_ATOMIC(&CORE_PIN1_DDRREG, CORE_PIN1_BITMASK);

  588. 		CORE_PIN1_CONFIG = 5 | 0x10;

  589. 		CORE_PIN1_PADCONFIG = CONFIG_PULLUP;

  590. 	}

  591. 	inline void set2() __attribute__((always_inline)) {

  592. 		GPIO_SETBIT_ATOMIC(&CORE_PIN2_DDRREG, CORE_PIN2_BITMASK);

  593. 		CORE_PIN2_CONFIG = 5 | 0x10;

  594. 		CORE_PIN2_PADCONFIG = CONFIG_PULLUP;

  595. 	}

  596. 	inline void set3() __attribute__((always_inline)) {

  597. 		GPIO_SETBIT_ATOMIC(&CORE_PIN3_DDRREG, CORE_PIN3_BITMASK);

  598. 		CORE_PIN3_CONFIG = 5 | 0x10;

  599. 		CORE_PIN3_PADCONFIG = CONFIG_PULLUP;

  600. 	}

  601. 	inline void set4() __attribute__((always_inline)) {

  602. 		GPIO_SETBIT_ATOMIC(&CORE_PIN4_DDRREG, CORE_PIN4_BITMASK);

  603. 		CORE_PIN4_CONFIG = 5 | 0x10;

  604. 		CORE_PIN4_PADCONFIG = CONFIG_PULLUP;

  605. 	}

  606. 	inline void set5() __attribute__((always_inline)) {

  607. 		GPIO_SETBIT_ATOMIC(&CORE_PIN5_DDRREG, CORE_PIN5_BITMASK);

  608. 		CORE_PIN5_CONFIG = 5 | 0x10;

  609. 		CORE_PIN5_PADCONFIG = CONFIG_PULLUP;

  610. 	}

  611. 	inline void set6() __attribute__((always_inline)) {

  612. 		GPIO_SETBIT_ATOMIC(&CORE_PIN6_DDRREG, CORE_PIN6_BITMASK);

  613. 		CORE_PIN6_CONFIG = 5 | 0x10;

  614. 		CORE_PIN6_PADCONFIG = CONFIG_PULLUP;

  615. 	}

  616. 	inline void set7() __attribute__((always_inline)) {

  617. 		GPIO_SETBIT_ATOMIC(&CORE_PIN7_DDRREG, CORE_PIN7_BITMASK);

  618. 		CORE_PIN7_CONFIG = 5 | 0x10;

  619. 		CORE_PIN7_PADCONFIG = CONFIG_PULLUP;

  620. 	}

  621. 	inline void clr0() __attribute__((always_inline)) {

  622. 		CORE_PIN0_CONFIG = 5 | 0x10;

  623. 		CORE_PIN0_PADCONFIG = ((CORE_PIN0_PORTREG & CORE_PIN0_BITMASK)

  624. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  625. 		GPIO_CLRBIT_ATOMIC(&CORE_PIN0_DDRREG, CORE_PIN0_BITMASK);

  626. 	}

  627. 	inline void clr1() __attribute__((always_inline)) {

  628. 		CORE_PIN1_CONFIG = 5 | 0x10;

  629. 		CORE_PIN1_PADCONFIG = ((CORE_PIN1_PORTREG & CORE_PIN1_BITMASK)

  630. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  631. 		GPIO_CLRBIT_ATOMIC(&CORE_PIN1_DDRREG, CORE_PIN1_BITMASK);

  632. 	}

  633. 	inline void clr2() __attribute__((always_inline)) {

  634. 		CORE_PIN2_CONFIG = 5 | 0x10;

  635. 		CORE_PIN2_PADCONFIG = ((CORE_PIN2_PORTREG & CORE_PIN2_BITMASK)

  636. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  637. 		GPIO_CLRBIT_ATOMIC(&CORE_PIN2_DDRREG, CORE_PIN2_BITMASK);

  638. 	}

  639. 	inline void clr3() __attribute__((always_inline)) {

  640. 		CORE_PIN3_CONFIG = 5 | 0x10;

  641. 		CORE_PIN3_PADCONFIG = ((CORE_PIN3_PORTREG & CORE_PIN3_BITMASK)

  642. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  643. 		GPIO_CLRBIT_ATOMIC(&CORE_PIN3_DDRREG, CORE_PIN3_BITMASK);

  644. 	}

  645. 	inline void clr4() __attribute__((always_inline)) {

  646. 		CORE_PIN4_CONFIG = 5 | 0x10;

  647. 		CORE_PIN4_PADCONFIG = ((CORE_PIN4_PORTREG & CORE_PIN4_BITMASK)

  648. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  649. 		GPIO_CLRBIT_ATOMIC(&CORE_PIN4_DDRREG, CORE_PIN4_BITMASK);

  650. 	}

  651. 	inline void clr5() __attribute__((always_inline)) {

  652. 		CORE_PIN5_CONFIG = 5 | 0x10;

  653. 		CORE_PIN5_PADCONFIG = ((CORE_PIN5_PORTREG & CORE_PIN5_BITMASK)

  654. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  655. 		GPIO_CLRBIT_ATOMIC(&CORE_PIN5_DDRREG, CORE_PIN5_BITMASK);

  656. 	}

  657. 	inline void clr6() __attribute__((always_inline)) {

  658. 		CORE_PIN6_CONFIG = 5 | 0x10;

  659. 		CORE_PIN6_PADCONFIG = ((CORE_PIN6_PORTREG & CORE_PIN6_BITMASK)

  660. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  661. 		GPIO_CLRBIT_ATOMIC(&CORE_PIN6_DDRREG, CORE_PIN6_BITMASK);

  662. 	}

  663. 	inline void clr7() __attribute__((always_inline)) {

  664. 		CORE_PIN7_CONFIG = 5 | 0x10;

  665. 		CORE_PIN7_PADCONFIG = ((CORE_PIN7_PORTREG & CORE_PIN7_BITMASK)

  666. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  667. 		GPIO_CLRBIT_ATOMIC(&CORE_PIN7_DDRREG, CORE_PIN7_BITMASK);

  668. 	}

  669. };

  670. 

  671. extern DDRDemulation DDRD;

  672. 

  673. 

  674. 

  675. 

  676. 

  677. 

  678. class PORTBemulation

  679. {

  680. public:

  681. 	inline PORTBemulation & operator = (int val) __attribute__((always_inline)) {

  682. 		digitalWriteFast(8, (val & (1<<0)));

  683. 		if (!(CORE_PIN8_DDRREG & CORE_PIN8_BITMASK))

  684. 			CORE_PIN8_PADCONFIG = ((val & (1<<0)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  685. 		digitalWriteFast(9, (val & (1<<1)));

  686. 		if (!(CORE_PIN9_DDRREG & CORE_PIN9_BITMASK))

  687. 			CORE_PIN9_PADCONFIG = ((val & (1<<1)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  688. 		digitalWriteFast(10, (val & (1<<2)));

  689. 		if (!(CORE_PIN10_DDRREG & CORE_PIN10_BITMASK))

  690. 			CORE_PIN10_PADCONFIG = ((val & (1<<2)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  691. 		digitalWriteFast(11, (val & (1<<3)));

  692. 		if (!(CORE_PIN11_DDRREG & CORE_PIN11_BITMASK))

  693. 			CORE_PIN11_PADCONFIG = ((val & (1<<3)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  694. 		digitalWriteFast(12, (val & (1<<4)));

  695. 		if (!(CORE_PIN12_DDRREG & CORE_PIN12_BITMASK))

  696. 			CORE_PIN12_PADCONFIG = ((val & (1<<4)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  697. 		digitalWriteFast(13, (val & (1<<5)));

  698. 		if (!(CORE_PIN13_DDRREG & CORE_PIN13_BITMASK))

  699. 			CORE_PIN13_PADCONFIG = ((val & (1<<5)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  700. 		return *this;

  701. 	}

  702. 	inline PORTBemulation & operator |= (int val) __attribute__((always_inline)) {

  703. 		if (val & (1<<0)) {

  704. 			digitalWriteFast(8, HIGH);

  705. 			if (!(CORE_PIN7_DDRREG & CORE_PIN7_BITMASK)) CORE_PIN8_CONFIG = CONFIG_PULLUP;

  706. 		}

  707. 		if (val & (1<<1)) {

  708. 			digitalWriteFast(9, HIGH);

  709. 			if (!(CORE_PIN7_DDRREG & CORE_PIN7_BITMASK)) CORE_PIN9_CONFIG = CONFIG_PULLUP;

  710. 		}

  711. 		if (val & (1<<2)) {

  712. 			digitalWriteFast(10, HIGH);

  713. 			if (!(CORE_PIN10_DDRREG & CORE_PIN10_BITMASK)) CORE_PIN10_CONFIG = CONFIG_PULLUP;

  714. 		}

  715. 		if (val & (1<<3)) {

  716. 			digitalWriteFast(11, HIGH);

  717. 			if (!(CORE_PIN11_DDRREG & CORE_PIN11_BITMASK)) CORE_PIN11_CONFIG = CONFIG_PULLUP;

  718. 		}

  719. 		if (val & (1<<4)) {

  720. 			digitalWriteFast(12, HIGH);

  721. 			if (!(CORE_PIN12_DDRREG & CORE_PIN12_BITMASK)) CORE_PIN12_CONFIG = CONFIG_PULLUP;

  722. 		}

  723. 		if (val & (1<<5)) {

  724. 			digitalWriteFast(13, HIGH);

  725. 			if (!(CORE_PIN13_DDRREG & CORE_PIN13_BITMASK)) CORE_PIN13_CONFIG = CONFIG_PULLUP;

  726. 		}

  727. 		return *this;

  728. 	}

  729. 	inline PORTBemulation & operator &= (int val) __attribute__((always_inline)) {

  730. 		if (!(val & (1<<0))) {

  731. 			digitalWriteFast(8, LOW);

  732. 			if (!(CORE_PIN8_DDRREG & CORE_PIN8_BITMASK)) CORE_PIN8_CONFIG = CONFIG_NOPULLUP;

  733. 		}

  734. 		if (!(val & (1<<1))) {

  735. 			digitalWriteFast(9, LOW);

  736. 			if (!(CORE_PIN9_DDRREG & CORE_PIN9_BITMASK)) CORE_PIN9_CONFIG = CONFIG_NOPULLUP;

  737. 		}

  738. 		if (!(val & (1<<2))) {

  739. 			digitalWriteFast(10, LOW);

  740. 			if (!(CORE_PIN10_DDRREG & CORE_PIN10_BITMASK)) CORE_PIN10_CONFIG = CONFIG_NOPULLUP;

  741. 		}

  742. 		if (!(val & (1<<3))) {

  743. 			digitalWriteFast(11, LOW);

  744. 			if (!(CORE_PIN11_DDRREG & CORE_PIN11_BITMASK)) CORE_PIN11_CONFIG = CONFIG_NOPULLUP;

  745. 		}

  746. 		if (!(val & (1<<4))) {

  747. 			digitalWriteFast(12, LOW);

  748. 			if (!(CORE_PIN12_DDRREG & CORE_PIN12_BITMASK)) CORE_PIN12_CONFIG = CONFIG_NOPULLUP;

  749. 		}

  750. 		if (!(val & (1<<5))) {

  751. 			digitalWriteFast(13, LOW);

  752. 			if (!(CORE_PIN13_DDRREG & CORE_PIN13_BITMASK)) CORE_PIN13_CONFIG = CONFIG_NOPULLUP;

  753. 		}

  754. 		return *this;

  755. 	}

  756. };

  757. extern PORTBemulation PORTB;

  758. 

  759. class PINBemulation

  760. {

  761. public:

  762. 	inline int operator & (int val) const __attribute__((always_inline)) {

  763. 		int ret = 0;

  764. 		if ((val & (1<<0)) && digitalReadFast(8)) ret |= (1<<0);

  765. 		if ((val & (1<<1)) && digitalReadFast(9)) ret |= (1<<1);

  766. 		if ((val & (1<<2)) && digitalReadFast(10)) ret |= (1<<2);

  767. 		if ((val & (1<<3)) && digitalReadFast(11)) ret |= (1<<3);

  768. 		if ((val & (1<<4)) && digitalReadFast(12)) ret |= (1<<4);

  769. 		if ((val & (1<<5)) && digitalReadFast(13)) ret |= (1<<5);

  770. 		return ret;

  771. 	}

  772. 	operator int () const __attribute__((always_inline)) {

  773. 		int ret = 0;

  774. 		if (digitalReadFast(8)) ret |= (1<<0);

  775. 		if (digitalReadFast(9)) ret |= (1<<1);

  776. 		if (digitalReadFast(10)) ret |= (1<<2);

  777. 		if (digitalReadFast(11)) ret |= (1<<3);

  778. 		if (digitalReadFast(12)) ret |= (1<<4);

  779. 		if (digitalReadFast(13)) ret |= (1<<5);

  780. 		return ret;

  781. 	}

  782. };

  783. extern PINBemulation PINB;

  784. 

  785. class DDRBemulation

  786. {

  787. public:

  788. 	inline DDRBemulation & operator = (int val) __attribute__((always_inline)) {

  789. 		if (val & (1<<0)) set0(); else clr0();

  790. 		if (val & (1<<1)) set1(); else clr1();

  791. 		if (val & (1<<2)) set2(); else clr2();

  792. 		if (val & (1<<3)) set3(); else clr3();

  793. 		if (val & (1<<4)) set4(); else clr4();

  794. 		if (val & (1<<5)) set5(); else clr5();

  795. 		return *this;

  796. 	}

  797. 	inline DDRBemulation & operator |= (int val) __attribute__((always_inline)) {

  798. 		if (val & (1<<0)) set0();

  799. 		if (val & (1<<1)) set1();

  800. 		if (val & (1<<2)) set2();

  801. 		if (val & (1<<3)) set3();

  802. 		if (val & (1<<4)) set4();

  803. 		if (val & (1<<5)) set5();

  804. 		return *this;

  805. 	}

  806. 	inline DDRBemulation & operator &= (int val) __attribute__((always_inline)) {

  807. 		if (!(val & (1<<0))) clr0();

  808. 		if (!(val & (1<<1))) clr1();

  809. 		if (!(val & (1<<2))) clr2();

  810. 		if (!(val & (1<<3))) clr3();

  811. 		if (!(val & (1<<4))) clr4();

  812. 		if (!(val & (1<<5))) clr5();

  813. 		return *this;

  814. 	}

  815. private:

  816. 	inline void set0() __attribute__((always_inline)) {

  817. 		GPIO_SETBIT_ATOMIC(&CORE_PIN8_DDRREG, CORE_PIN8_BITMASK);

  818. 		CORE_PIN8_CONFIG = 5 | 0x10;

  819. 		CORE_PIN8_PADCONFIG = CONFIG_PULLUP;

  820. 	}

  821. 	inline void set1() __attribute__((always_inline)) {

  822. 		GPIO_SETBIT_ATOMIC(&CORE_PIN9_DDRREG, CORE_PIN9_BITMASK);

  823. 		CORE_PIN9_CONFIG = 5 | 0x10;

  824. 		CORE_PIN9_PADCONFIG = CONFIG_PULLUP;

  825. 	}

  826. 	inline void set2() __attribute__((always_inline)) {

  827. 		GPIO_SETBIT_ATOMIC(&CORE_PIN10_DDRREG, CORE_PIN10_BITMASK);

  828. 		CORE_PIN10_CONFIG = 5 | 0x10;

  829. 		CORE_PIN10_PADCONFIG = CONFIG_PULLUP;

  830. 	}

  831. 	inline void set3() __attribute__((always_inline)) {

  832. 		GPIO_SETBIT_ATOMIC(&CORE_PIN11_DDRREG, CORE_PIN11_BITMASK);

  833. 		CORE_PIN11_CONFIG = 5 | 0x10;

  834. 		CORE_PIN11_PADCONFIG = CONFIG_PULLUP;

  835. 	}

  836. 	inline void set4() __attribute__((always_inline)) {

  837. 		GPIO_SETBIT_ATOMIC(&CORE_PIN12_DDRREG, CORE_PIN12_BITMASK);

  838. 		CORE_PIN12_CONFIG = 5 | 0x10;

  839. 		CORE_PIN12_PADCONFIG = CONFIG_PULLUP;

  840. 	}

  841. 	inline void set5() __attribute__((always_inline)) {

  842. 		GPIO_SETBIT_ATOMIC(&CORE_PIN13_DDRREG, CORE_PIN13_BITMASK);

  843. 		CORE_PIN13_CONFIG = 5 | 0x10;

  844. 		CORE_PIN13_PADCONFIG = CONFIG_PULLUP;

  845. 	}

  846. 	inline void clr0() __attribute__((always_inline)) {

  847. 		CORE_PIN8_CONFIG = 5 | 0x10;

  848. 		CORE_PIN8_PADCONFIG = ((CORE_PIN8_PORTREG & CORE_PIN8_BITMASK)

  849. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  850. 		GPIO_CLRBIT_ATOMIC(&CORE_PIN8_DDRREG, CORE_PIN8_BITMASK);

  851. 	}

  852. 	inline void clr1() __attribute__((always_inline)) {

  853. 		CORE_PIN9_CONFIG = 5 | 0x10;

  854. 		CORE_PIN9_PADCONFIG = ((CORE_PIN9_PORTREG & CORE_PIN9_BITMASK)

  855. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  856. 		GPIO_CLRBIT_ATOMIC(&CORE_PIN9_DDRREG, CORE_PIN9_BITMASK);

  857. 	}

  858. 	inline void clr2() __attribute__((always_inline)) {

  859. 		CORE_PIN10_CONFIG = 5 | 0x10;

  860. 		CORE_PIN10_PADCONFIG = ((CORE_PIN10_PORTREG & CORE_PIN10_BITMASK)

  861. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  862. 		GPIO_CLRBIT_ATOMIC(&CORE_PIN10_DDRREG, CORE_PIN10_BITMASK);

  863. 	}

  864. 	inline void clr3() __attribute__((always_inline)) {

  865. 		CORE_PIN11_CONFIG = 5 | 0x10;

  866. 		CORE_PIN11_PADCONFIG = ((CORE_PIN11_PORTREG & CORE_PIN11_BITMASK)

  867. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  868. 		GPIO_CLRBIT_ATOMIC(&CORE_PIN11_DDRREG, CORE_PIN11_BITMASK);

  869. 	}

  870. 	inline void clr4() __attribute__((always_inline)) {

  871. 		CORE_PIN12_CONFIG = 5 | 0x10;

  872. 		CORE_PIN12_PADCONFIG = ((CORE_PIN12_PORTREG & CORE_PIN12_BITMASK)

  873. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  874. 		GPIO_CLRBIT_ATOMIC(&CORE_PIN12_DDRREG, CORE_PIN12_BITMASK);

  875. 	}

  876. 	inline void clr5() __attribute__((always_inline)) {

  877. 		CORE_PIN13_CONFIG = 5 | 0x10;

  878. 		CORE_PIN13_PADCONFIG = ((CORE_PIN13_PORTREG & CORE_PIN13_BITMASK)

  879. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  880. 		GPIO_CLRBIT_ATOMIC(&CORE_PIN13_DDRREG, CORE_PIN13_BITMASK);

  881. 	}

  882. };

  883. 

  884. extern DDRBemulation DDRB;

  885. 

  886. 

  887. 

  888. 

  889. 

  890. 

  891. class PORTCemulation

  892. {

  893. public:

  894. 	inline PORTCemulation & operator = (int val) __attribute__((always_inline)) {

  895. 		digitalWriteFast(14, (val & (1<<0)));

  896. 		if (!(CORE_PIN14_DDRREG & CORE_PIN14_BITMASK))

  897. 			CORE_PIN14_PADCONFIG = ((val & (1<<0)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  898. 		digitalWriteFast(15, (val & (1<<1)));

  899. 		if (!(CORE_PIN15_DDRREG & CORE_PIN15_BITMASK))

  900. 			CORE_PIN15_PADCONFIG = ((val & (1<<1)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  901. 		digitalWriteFast(16, (val & (1<<2)));

  902. 		if (!(CORE_PIN16_DDRREG & CORE_PIN16_BITMASK))

  903. 			CORE_PIN16_PADCONFIG = ((val & (1<<2)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  904. 		digitalWriteFast(17, (val & (1<<3)));

  905. 		if (!(CORE_PIN17_DDRREG & CORE_PIN17_BITMASK))

  906. 			CORE_PIN17_PADCONFIG = ((val & (1<<3)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  907. 		digitalWriteFast(18, (val & (1<<4)));

  908. 		if (!(CORE_PIN18_DDRREG & CORE_PIN18_BITMASK))

  909. 			CORE_PIN18_PADCONFIG = ((val & (1<<4)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  910. 		digitalWriteFast(19, (val & (1<<5)));

  911. 		if (!(CORE_PIN19_DDRREG & CORE_PIN19_BITMASK))

  912. 			CORE_PIN19_PADCONFIG = ((val & (1<<5)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  913. 		return *this;

  914. 	}

  915. 	inline PORTCemulation & operator |= (int val) __attribute__((always_inline)) {

  916. 		if (val & (1<<0)) {

  917. 			digitalWriteFast(14, HIGH);

  918. 			if (!(CORE_PIN14_DDRREG & CORE_PIN14_BITMASK)) CORE_PIN14_CONFIG = CONFIG_PULLUP;

  919. 		}

  920. 		if (val & (1<<1)) {

  921. 			digitalWriteFast(15, HIGH);

  922. 			if (!(CORE_PIN15_DDRREG & CORE_PIN15_BITMASK)) CORE_PIN15_CONFIG = CONFIG_PULLUP;

  923. 		}

  924. 		if (val & (1<<2)) {

  925. 			digitalWriteFast(16, HIGH);

  926. 			if (!(CORE_PIN16_DDRREG & CORE_PIN16_BITMASK)) CORE_PIN16_CONFIG = CONFIG_PULLUP;

  927. 		}

  928. 		if (val & (1<<3)) {

  929. 			digitalWriteFast(17, HIGH);

  930. 			if (!(CORE_PIN17_DDRREG & CORE_PIN17_BITMASK)) CORE_PIN17_CONFIG = CONFIG_PULLUP;

  931. 		}

  932. 		if (val & (1<<4)) {

  933. 			digitalWriteFast(18, HIGH);

  934. 			if (!(CORE_PIN18_DDRREG & CORE_PIN18_BITMASK)) CORE_PIN18_CONFIG = CONFIG_PULLUP;

  935. 		}

  936. 		if (val & (1<<5)) {

  937. 			digitalWriteFast(19, HIGH);

  938. 			if (!(CORE_PIN19_DDRREG & CORE_PIN19_BITMASK)) CORE_PIN19_CONFIG = CONFIG_PULLUP;

  939. 		}

  940. 		return *this;

  941. 	}

  942. 	inline PORTCemulation & operator &= (int val) __attribute__((always_inline)) {

  943. 		if (!(val & (1<<0))) {

  944. 			digitalWriteFast(14, LOW);

  945. 			if (!(CORE_PIN14_DDRREG & CORE_PIN14_BITMASK)) CORE_PIN14_CONFIG = CONFIG_NOPULLUP;

  946. 		}

  947. 		if (!(val & (1<<1))) {

  948. 			digitalWriteFast(15, LOW);

  949. 			if (!(CORE_PIN15_DDRREG & CORE_PIN15_BITMASK)) CORE_PIN15_CONFIG = CONFIG_NOPULLUP;

  950. 		}

  951. 		if (!(val & (1<<2))) {

  952. 			digitalWriteFast(16, LOW);

  953. 			if (!(CORE_PIN16_DDRREG & CORE_PIN16_BITMASK)) CORE_PIN16_CONFIG = CONFIG_NOPULLUP;

  954. 		}

  955. 		if (!(val & (1<<3))) {

  956. 			digitalWriteFast(17, LOW);

  957. 			if (!(CORE_PIN17_DDRREG & CORE_PIN17_BITMASK)) CORE_PIN17_CONFIG = CONFIG_NOPULLUP;

  958. 		}

  959. 		if (!(val & (1<<4))) {

  960. 			digitalWriteFast(18, LOW);

  961. 			if (!(CORE_PIN18_DDRREG & CORE_PIN18_BITMASK)) CORE_PIN18_CONFIG = CONFIG_NOPULLUP;

  962. 		}

  963. 		if (!(val & (1<<5))) {

  964. 			digitalWriteFast(19, LOW);

  965. 			if (!(CORE_PIN19_DDRREG & CORE_PIN19_BITMASK)) CORE_PIN19_CONFIG = CONFIG_NOPULLUP;

  966. 		}

  967. 		return *this;

  968. 	}

  969. };

  970. extern PORTCemulation PORTC;

  971. 

  972. class PINCemulation

  973. {

  974. public:

  975. 	inline int operator & (int val) const __attribute__((always_inline)) {

  976. 		int ret = 0;

  977. 		if ((val & (1<<0)) && digitalReadFast(14)) ret |= (1<<0);

  978. 		if ((val & (1<<1)) && digitalReadFast(15)) ret |= (1<<1);

  979. 		if ((val & (1<<2)) && digitalReadFast(16)) ret |= (1<<2);

  980. 		if ((val & (1<<3)) && digitalReadFast(17)) ret |= (1<<3);

  981. 		if ((val & (1<<4)) && digitalReadFast(18)) ret |= (1<<4);

  982. 		if ((val & (1<<5)) && digitalReadFast(19)) ret |= (1<<5);

  983. 		return ret;

  984. 	}

  985. 	operator int () const __attribute__((always_inline)) {

  986. 		int ret = 0;

  987. 		if (digitalReadFast(14)) ret |= (1<<0);

  988. 		if (digitalReadFast(15)) ret |= (1<<1);

  989. 		if (digitalReadFast(16)) ret |= (1<<2);

  990. 		if (digitalReadFast(17)) ret |= (1<<3);

  991. 		if (digitalReadFast(18)) ret |= (1<<4);

  992. 		if (digitalReadFast(19)) ret |= (1<<5);

  993. 		return ret;

  994. 	}

  995. };

  996. extern PINCemulation PINC;

  997. 

  998. class DDRCemulation

  999. {

  1000. public:

  1001. 	inline DDRCemulation & operator = (int val) __attribute__((always_inline)) {

  1002. 		if (val & (1<<0)) set0(); else clr0();

  1003. 		if (val & (1<<1)) set1(); else clr1();

  1004. 		if (val & (1<<2)) set2(); else clr2();

  1005. 		if (val & (1<<3)) set3(); else clr3();

  1006. 		if (val & (1<<4)) set4(); else clr4();

  1007. 		if (val & (1<<5)) set5(); else clr5();

  1008. 		return *this;

  1009. 	}

  1010. 	inline DDRCemulation & operator |= (int val) __attribute__((always_inline)) {

  1011. 		if (val & (1<<0)) set0();

  1012. 		if (val & (1<<1)) set1();

  1013. 		if (val & (1<<2)) set2();

  1014. 		if (val & (1<<3)) set3();

  1015. 		if (val & (1<<4)) set4();

  1016. 		if (val & (1<<5)) set5();

  1017. 		return *this;

  1018. 	}

  1019. 	inline DDRCemulation & operator &= (int val) __attribute__((always_inline)) {

  1020. 		if (!(val & (1<<0))) clr0();

  1021. 		if (!(val & (1<<1))) clr1();

  1022. 		if (!(val & (1<<2))) clr2();

  1023. 		if (!(val & (1<<3))) clr3();

  1024. 		if (!(val & (1<<4))) clr4();

  1025. 		if (!(val & (1<<5))) clr5();

  1026. 		return *this;

  1027. 	}

  1028. private:

  1029. 	inline void set0() __attribute__((always_inline)) {

  1030. 		GPIO_SETBIT_ATOMIC(&CORE_PIN14_DDRREG, CORE_PIN14_BITMASK);

  1031. 		CORE_PIN14_CONFIG = 5 | 0x10;

  1032. 		CORE_PIN14_PADCONFIG = CONFIG_PULLUP;

  1033. 	}

  1034. 	inline void set1() __attribute__((always_inline)) {

  1035. 		GPIO_SETBIT_ATOMIC(&CORE_PIN15_DDRREG, CORE_PIN15_BITMASK);

  1036. 		CORE_PIN15_CONFIG = 5 | 0x10;

  1037. 		CORE_PIN15_PADCONFIG = CONFIG_PULLUP;

  1038. 	}

  1039. 	inline void set2() __attribute__((always_inline)) {

  1040. 		GPIO_SETBIT_ATOMIC(&CORE_PIN16_DDRREG, CORE_PIN16_BITMASK);

  1041. 		CORE_PIN16_CONFIG = 5 | 0x10;

  1042. 		CORE_PIN16_PADCONFIG = CONFIG_PULLUP;

  1043. 	}

  1044. 	inline void set3() __attribute__((always_inline)) {

  1045. 		GPIO_SETBIT_ATOMIC(&CORE_PIN17_DDRREG, CORE_PIN17_BITMASK);

  1046. 		CORE_PIN17_CONFIG = 5 | 0x10;

  1047. 		CORE_PIN17_PADCONFIG = CONFIG_PULLUP;

  1048. 	}

  1049. 	inline void set4() __attribute__((always_inline)) {

  1050. 		GPIO_SETBIT_ATOMIC(&CORE_PIN18_DDRREG, CORE_PIN18_BITMASK);

  1051. 		CORE_PIN18_CONFIG = 5 | 0x10;

  1052. 		CORE_PIN18_PADCONFIG = CONFIG_PULLUP;

  1053. 	}

  1054. 	inline void set5() __attribute__((always_inline)) {

  1055. 		GPIO_SETBIT_ATOMIC(&CORE_PIN19_DDRREG, CORE_PIN19_BITMASK);

  1056. 		CORE_PIN19_CONFIG = 5 | 0x10;

  1057. 		CORE_PIN19_PADCONFIG = CONFIG_PULLUP;

  1058. 	}

  1059. 	inline void clr0() __attribute__((always_inline)) {

  1060. 		CORE_PIN14_CONFIG = 5 | 0x10;

  1061. 		CORE_PIN14_PADCONFIG = ((CORE_PIN14_PORTREG & CORE_PIN14_BITMASK)

  1062. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  1063. 		GPIO_CLRBIT_ATOMIC(&CORE_PIN14_DDRREG, CORE_PIN14_BITMASK);

  1064. 	}

  1065. 	inline void clr1() __attribute__((always_inline)) {

  1066. 		CORE_PIN15_CONFIG = 5 | 0x10;

  1067. 		CORE_PIN15_PADCONFIG = ((CORE_PIN15_PORTREG & CORE_PIN15_BITMASK)

  1068. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  1069. 		GPIO_CLRBIT_ATOMIC(&CORE_PIN15_DDRREG, CORE_PIN15_BITMASK);

  1070. 	}

  1071. 	inline void clr2() __attribute__((always_inline)) {

  1072. 		CORE_PIN16_CONFIG = 5 | 0x10;

  1073. 		CORE_PIN16_PADCONFIG = ((CORE_PIN16_PORTREG & CORE_PIN16_BITMASK)

  1074. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  1075. 		GPIO_CLRBIT_ATOMIC(&CORE_PIN16_DDRREG, CORE_PIN16_BITMASK);

  1076. 	}

  1077. 	inline void clr3() __attribute__((always_inline)) {

  1078. 		CORE_PIN17_CONFIG = 5 | 0x10;

  1079. 		CORE_PIN17_PADCONFIG = ((CORE_PIN17_PORTREG & CORE_PIN17_BITMASK)

  1080. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  1081. 		GPIO_CLRBIT_ATOMIC(&CORE_PIN17_DDRREG, CORE_PIN17_BITMASK);

  1082. 	}

  1083. 	inline void clr4() __attribute__((always_inline)) {

  1084. 		CORE_PIN18_CONFIG = 5 | 0x10;

  1085. 		CORE_PIN18_PADCONFIG = ((CORE_PIN18_PORTREG & CORE_PIN18_BITMASK)

  1086. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  1087. 		GPIO_CLRBIT_ATOMIC(&CORE_PIN18_DDRREG, CORE_PIN18_BITMASK);

  1088. 	}

  1089. 	inline void clr5() __attribute__((always_inline)) {

  1090. 		CORE_PIN19_CONFIG = 5 | 0x10;

  1091. 		CORE_PIN19_PADCONFIG = ((CORE_PIN19_PORTREG & CORE_PIN19_BITMASK)

  1092. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  1093. 		GPIO_CLRBIT_ATOMIC(&CORE_PIN19_DDRREG, CORE_PIN19_BITMASK);

  1094. 	}

  1095. };

  1096. 

  1097. extern DDRCemulation DDRC;

  1098. 

  1099. 

  1100. #define PINB0 0

  1101. #define PINB1 1

  1102. #define PINB2 2

  1103. #define PINB3 3

  1104. #define PINB4 4

  1105. #define PINB5 5

  1106. #define PINB6 6

  1107. #define PINB7 7

  1108. #define DDB0 0

  1109. #define DDB1 1

  1110. #define DDB2 2

  1111. #define DDB3 3

  1112. #define DDB4 4

  1113. #define DDB5 5

  1114. #define DDB6 6

  1115. #define DDB7 7

  1116. #define PORTB0 0

  1117. #define PORTB1 1

  1118. #define PORTB2 2

  1119. #define PORTB3 3

  1120. #define PORTB4 4

  1121. #define PORTB5 5

  1122. #define PORTB6 6

  1123. #define PORTB7 7

  1124. #define PINC0 0

  1125. #define PINC1 1

  1126. #define PINC2 2

  1127. #define PINC3 3

  1128. #define PINC4 4

  1129. #define PINC5 5

  1130. #define PINC6 6

  1131. #define DDC0 0

  1132. #define DDC1 1

  1133. #define DDC2 2

  1134. #define DDC3 3

  1135. #define DDC4 4

  1136. #define DDC5 5

  1137. #define DDC6 6

  1138. #define PORTC0 0

  1139. #define PORTC1 1

  1140. #define PORTC2 2

  1141. #define PORTC3 3

  1142. #define PORTC4 4

  1143. #define PORTC5 5

  1144. #define PORTC6 6

  1145. #define PIND0 0

  1146. #define PIND1 1

  1147. #define PIND2 2

  1148. #define PIND3 3

  1149. #define PIND4 4

  1150. #define PIND5 5

  1151. #define PIND6 6

  1152. #define PIND7 7

  1153. #define DDD0 0

  1154. #define DDD1 1

  1155. #define DDD2 2

  1156. #define DDD3 3

  1157. #define DDD4 4

  1158. #define DDD5 5

  1159. #define DDD6 6

  1160. #define DDD7 7

  1161. #define PORTD0 0

  1162. #define PORTD1 1

  1163. #define PORTD2 2

  1164. #define PORTD3 3

  1165. #define PORTD4 4

  1166. #define PORTD5 5

  1167. #define PORTD6 6

  1168. #define PORTD7 7

  1169. 

  1170. 

  1171. 

  1172. #endif // __cplusplus

  1173. 

  1174. #endif