(MKL26Z64) update for F_PLL <= 16MHz

teensy3/mk20dx128.c

@@ -554,7 +554,7 @@ void ResetHandler(void)
 	//  C2[LP] bit is written to 1
 #else
 	// enable capacitors for crystal
-	OSC0_CR = OSC_SC8P | OSC_SC2P | 0x80;
+	OSC0_CR = OSC_SC8P | OSC_SC2P | OSC_ERCLKEN;
 	// enable osc, 8-32 MHz range, low power mode
 	MCG_C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS;
 	// switch to crystal as clock source, FLL input = 16 MHz / 512