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(MKL26Z64) update for F_PLL <= 16MHz

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duff2013 9 years ago
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1fa14faf08
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      teensy3/mk20dx128.c

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teensy3/mk20dx128.c View File

// C2[LP] bit is written to 1 // C2[LP] bit is written to 1
#else #else
// enable capacitors for crystal // enable capacitors for crystal
OSC0_CR = OSC_SC8P | OSC_SC2P | 0x80;
OSC0_CR = OSC_SC8P | OSC_SC2P | OSC_ERCLKEN;
// enable osc, 8-32 MHz range, low power mode // enable osc, 8-32 MHz range, low power mode
MCG_C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS; MCG_C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS;
// switch to crystal as clock source, FLL input = 16 MHz / 512 // switch to crystal as clock source, FLL input = 16 MHz / 512

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