shifting both sides by 16 bit gives pretty good accuracy with fast code:
        movw    r3, #9155
        ldr     r2, .L2
        mul     r0, r3, r0
        lsrs    r0, r0, #1
        umull   r3, r0, r2, r0
        lsrs    r0, r0, #8
.L2:
        .word   144122641

with 984 MHz it allows nsec to be max ~143000  max which is plenty

This makes sense now, and would be useful for shorter wait-times. Could be used for PulseIn etc.  where we need defined very short delays.

- comment SRC_GPR1..SRC_GPR10 (used by the ROM code)

Deleted a duplicate define: #define CCM_CBCMR_PERIPH_CLK2_SEL_MASK		((uint32_t)(0x03 << 12))
 and added tempmon registers