fixes #159

Make update of these flags be hopefully interrupt safe

This is a WIP,  But I have now been able to create Serial6 on T3.4 beta,
and so far have tested Send/Receive basic stuff at 115200 and have tried
at several CPU speeds in MHZ (192, 216, 180, 120, 96)

These two functions were checking (SIM_SCGC4 & SIM_SCGC4_UART2)
and should be testing (SIM_SCGC4 & SIM_SCGC4_UART1)

fixes #145

PulseIn may fail on LC as it is using *reg to test the value for on or
off, but on LC register is a bitmask associated with several IO pins.
So split off for LC to use the MASK value for the pin to test high and
low.

Warning did not update timings for this,  which may be necessary as adds
an & in the loop.  However when I tried TLC for 5000us timeout, it timed
out with 5138us, if I decremented the PULSEIN_LOOPS_PER_USEC by one,
then it timed out at 4398... This was at 49mhz.

Just in case the extra pads are added to bottom of 3.4/3.5 board,
define is in place...

Added define for SPI1 registers

...were missing :)

On Serial 3 this addition is for all 3.x.  Before it was ifdefed to only
do work on Teensy_LC as there is only one valid TX pin.  But we now pass
in open drain as an option so this code should allow you to not turn it
on/off on Serial3 on all of these boards

and on Serial4 and Serial5 on the new boards.

Updated Serial2.
It had valid TX for T3.2 of 10 and 31, but 31 on T3.5 is RX4

Likewise RX for T3.2 of 9 and 26, but on T3.5 26 is RX1

fixes 136