The FlexIO registers are 32 bits, the masks were all setup for 16 bits so the high word of registers were not updated

I created a structure IMXRT_LPSPI_t
like what was done for UARTS.

I hopefully got all of the unused fields in properly to get the registers on the correct addresses.
Note: I did not update the other #define LPSPIn_ values but left them, likewise, I create a new define for each of the addresses.

That way we can double check I have everything properly aligned

Tempsense2 address correction and added analogreadaveraging code.

- comment SRC_GPR1..SRC_GPR10 (used by the ROM code)

Deleted a duplicate define: #define CCM_CBCMR_PERIPH_CLK2_SEL_MASK		((uint32_t)(0x03 << 12))
 and added tempmon registers