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  1. <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">

  2. <html>

  3. <!-- This file documents the GNU Assembler "as".

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  17. <title>BPF Opcodes (Using as)</title>

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  27. <link href="BPF_002dDependent.html#BPF_002dDependent" rel="up" title="BPF-Dependent">

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  59. </head>

  60. 

  61. <body lang="en">

  62. <a name="BPF-Opcodes"></a>

  63. <div class="header">

  64. <p>

  65. Previous: <a href="BPF-Directives.html#BPF-Directives" accesskey="p" rel="prev">BPF Directives</a>, Up: <a href="BPF_002dDependent.html#BPF_002dDependent" accesskey="u" rel="up">BPF-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>

  66. </div>

  67. <hr>

  68. <a name="Opcodes-5"></a>

  69. <h4 class="subsection">9.7.4 Opcodes</h4>

  70. 

  71. <a name="index-BPF-opcodes"></a>

  72. <a name="index-opcodes-for-BPF"></a>

  73. <p>In the instruction descriptions below the following field descriptors

  74. are used:

  75. </p>

  76. <dl compact="compact">

  77. <dt><code>%d</code></dt>

  78. <dd><p>Destination general-purpose register whose role is to be destination

  79. of an operation.

  80. </p></dd>

  81. <dt><code>%s</code></dt>

  82. <dd><p>Source general-purpose register whose role is to be the source of an

  83. operation.

  84. </p></dd>

  85. <dt><code>disp16</code></dt>

  86. <dd><p>16-bit signed PC-relative offset, measured in number of 64-bit words,

  87. minus one.

  88. </p></dd>

  89. <dt><code>disp32</code></dt>

  90. <dd><p>32-bit signed PC-relative offset, measured in number of 64-bit words,

  91. minus one.

  92. </p></dd>

  93. <dt><code>offset16</code></dt>

  94. <dd><p>Signed 16-bit immediate.

  95. </p></dd>

  96. <dt><code>imm32</code></dt>

  97. <dd><p>Signed 32-bit immediate.

  98. </p></dd>

  99. <dt><code>imm64</code></dt>

  100. <dd><p>Signed 64-bit immediate.

  101. </p></dd>

  102. </dl>

  103. 

  104. <a name="Arithmetic-instructions"></a>

  105. <h4 class="subsubsection">9.7.4.1 Arithmetic instructions</h4>

  106. 

  107. <p>The destination register in these instructions act like an

  108. accumulator.

  109. </p>

  110. <dl compact="compact">

  111. <dt><code>add %d, (%s|imm32)</code></dt>

  112. <dd><p>64-bit arithmetic addition.

  113. </p></dd>

  114. <dt><code>sub %d, (%s|imm32)</code></dt>

  115. <dd><p>64-bit arithmetic subtraction.

  116. </p></dd>

  117. <dt><code>mul %d, (%s|imm32)</code></dt>

  118. <dd><p>64-bit arithmetic multiplication.

  119. </p></dd>

  120. <dt><code>div %d, (%s|imm32)</code></dt>

  121. <dd><p>64-bit arithmetic integer division.

  122. </p></dd>

  123. <dt><code>mod %d, (%s|imm32)</code></dt>

  124. <dd><p>64-bit integer remainder.

  125. </p></dd>

  126. <dt><code>and %d, (%s|imm32)</code></dt>

  127. <dd><p>64-bit bit-wise &ldquo;and&rdquo; operation.

  128. </p></dd>

  129. <dt><code>or %d, (%s|imm32)</code></dt>

  130. <dd><p>64-bit bit-wise &ldquo;or&rdquo; operation.

  131. </p></dd>

  132. <dt><code>xor %d, (%s|imm32)</code></dt>

  133. <dd><p>64-bit bit-wise exclusive-or operation.

  134. </p></dd>

  135. <dt><code>lsh %d, (%s|imm32)</code></dt>

  136. <dd><p>64-bit left shift, by <code>%s</code> or <code>imm32</code> bits.

  137. </p></dd>

  138. <dt><code>rsh %d, (%s|imm32)</code></dt>

  139. <dd><p>64-bit right logical shift, by <code>%s</code> or <code>imm32</code> bits.

  140. </p></dd>

  141. <dt><code>arsh %d, (%s|imm32)</code></dt>

  142. <dd><p>64-bit right arithmetic shift, by <code>%s</code> or <code>imm32</code> bits.

  143. </p></dd>

  144. <dt><code>neg %d</code></dt>

  145. <dd><p>64-bit arithmetic negation.

  146. </p></dd>

  147. <dt><code>mov %d, (%s|imm32)</code></dt>

  148. <dd><p>Move the 64-bit value of <code>%s</code> in <code>%d</code>, or load <code>imm32</code>

  149. in <code>%d</code>.

  150. </p></dd>

  151. </dl>

  152. 

  153. <a name="g_t32_002dbit-arithmetic-instructions"></a>

  154. <h4 class="subsubsection">9.7.4.2 32-bit arithmetic instructions</h4>

  155. 

  156. <p>The destination register in these instructions act as an accumulator.

  157. </p>

  158. <dl compact="compact">

  159. <dt><code>add32 %d, (%s|imm32)</code></dt>

  160. <dd><p>32-bit arithmetic addition.

  161. </p></dd>

  162. <dt><code>sub32 %d, (%s|imm32)</code></dt>

  163. <dd><p>32-bit arithmetic subtraction.

  164. </p></dd>

  165. <dt><code>mul32 %d, (%s|imm32)</code></dt>

  166. <dd><p>32-bit arithmetic multiplication.

  167. </p></dd>

  168. <dt><code>div32 %d, (%s|imm32)</code></dt>

  169. <dd><p>32-bit arithmetic integer division.

  170. </p></dd>

  171. <dt><code>mod32 %d, (%s|imm32)</code></dt>

  172. <dd><p>32-bit integer remainder.

  173. </p></dd>

  174. <dt><code>and32 %d, (%s|imm32)</code></dt>

  175. <dd><p>32-bit bit-wise &ldquo;and&rdquo; operation.

  176. </p></dd>

  177. <dt><code>or32 %d, (%s|imm32)</code></dt>

  178. <dd><p>32-bit bit-wise &ldquo;or&rdquo; operation.

  179. </p></dd>

  180. <dt><code>xor32 %d, (%s|imm32)</code></dt>

  181. <dd><p>32-bit bit-wise exclusive-or operation.

  182. </p></dd>

  183. <dt><code>lsh32 %d, (%s|imm32)</code></dt>

  184. <dd><p>32-bit left shift, by <code>%s</code> or <code>imm32</code> bits.

  185. </p></dd>

  186. <dt><code>rsh32 %d, (%s|imm32)</code></dt>

  187. <dd><p>32-bit right logical shift, by <code>%s</code> or <code>imm32</code> bits.

  188. </p></dd>

  189. <dt><code>arsh32 %d, (%s|imm32)</code></dt>

  190. <dd><p>32-bit right arithmetic shift, by <code>%s</code> or <code>imm32</code> bits.

  191. </p></dd>

  192. <dt><code>neg32 %d</code></dt>

  193. <dd><p>32-bit arithmetic negation.

  194. </p></dd>

  195. <dt><code>mov32 %d, (%s|imm32)</code></dt>

  196. <dd><p>Move the 32-bit value of <code>%s</code> in <code>%d</code>, or load <code>imm32</code>

  197. in <code>%d</code>.

  198. </p></dd>

  199. </dl>

  200. 

  201. <a name="Endianness-conversion-instructions"></a>

  202. <h4 class="subsubsection">9.7.4.3 Endianness conversion instructions</h4>

  203. 

  204. <dl compact="compact">

  205. <dt><code>endle %d, (8|16|32)</code></dt>

  206. <dd><p>Convert the 8-bit, 16-bit or 32-bit value in <code>%d</code> to

  207. little-endian.

  208. </p></dd>

  209. <dt><code>endbe %d, (8|16|32)</code></dt>

  210. <dd><p>Convert the 8-bit, 16-bit or 32-bit value in <code>%d</code> to big-endian.

  211. </p></dd>

  212. </dl>

  213. 

  214. <a name="g_t64_002dbit-load-and-pseudo-maps"></a>

  215. <h4 class="subsubsection">9.7.4.4 64-bit load and pseudo maps</h4>

  216. 

  217. <dl compact="compact">

  218. <dt><code>lddw %d, imm64</code></dt>

  219. <dd><p>Load the given signed 64-bit immediate, or pseudo map descriptor, to

  220. the destination register <code>%d</code>.

  221. </p></dd>

  222. <dt><code>lddw %d, %map_fd(N)</code></dt>

  223. <dd><p>Load the address of the given pseudo map fd <em>N</em> to the

  224. destination register <code>%d</code>.

  225. </p></dd>

  226. </dl>

  227. 

  228. <a name="Load-instructions-for-socket-filters"></a>

  229. <h4 class="subsubsection">9.7.4.5 Load instructions for socket filters</h4>

  230. 

  231. <p>The following instructions are intended to be used in socket filters,

  232. and are therefore not general-purpose: they make assumptions on the

  233. contents of several registers.  See the file

  234. <samp>Documentation/networking/filter.txt</samp> in the Linux kernel source

  235. tree for more information.

  236. </p>

  237. <p>Absolute loads:

  238. </p>

  239. <dl compact="compact">

  240. <dt><code>ldabsdw imm32</code></dt>

  241. <dd><p>Absolute 64-bit load.

  242. </p></dd>

  243. <dt><code>ldabsw imm32</code></dt>

  244. <dd><p>Absolute 32-bit load.

  245. </p></dd>

  246. <dt><code>ldabsh imm32</code></dt>

  247. <dd><p>Absolute 16-bit load.

  248. </p></dd>

  249. <dt><code>ldabsb imm32</code></dt>

  250. <dd><p>Absolute 8-bit load.

  251. </p></dd>

  252. </dl>

  253. 

  254. <p>Indirect loads:

  255. </p>

  256. <dl compact="compact">

  257. <dt><code>ldinddw %s, imm32</code></dt>

  258. <dd><p>Indirect 64-bit load.

  259. </p></dd>

  260. <dt><code>ldindw %s, imm32</code></dt>

  261. <dd><p>Indirect 32-bit load.

  262. </p></dd>

  263. <dt><code>ldindh %s, imm32</code></dt>

  264. <dd><p>Indirect 16-bit load.

  265. </p></dd>

  266. <dt><code>ldindb %s, imm32</code></dt>

  267. <dd><p>Indirect 8-bit load.

  268. </p></dd>

  269. </dl>

  270. 

  271. <a name="Generic-load_002fstore-instructions"></a>

  272. <h4 class="subsubsection">9.7.4.6 Generic load/store instructions</h4>

  273. 

  274. <p>General-purpose load and store instructions are provided for several

  275. word sizes.

  276. </p>

  277. <p>Load to register instructions:

  278. </p>

  279. <dl compact="compact">

  280. <dt><code>ldxdw %d, [%s+offset16]</code></dt>

  281. <dd><p>Generic 64-bit load.

  282. </p></dd>

  283. <dt><code>ldxw %d, [%s+offset16]</code></dt>

  284. <dd><p>Generic 32-bit load.

  285. </p></dd>

  286. <dt><code>ldxh %d, [%s+offset16]</code></dt>

  287. <dd><p>Generic 16-bit load.

  288. </p></dd>

  289. <dt><code>ldxb %d, [%s+offset16]</code></dt>

  290. <dd><p>Generic 8-bit load.

  291. </p></dd>

  292. </dl>

  293. 

  294. <p>Store from register instructions:

  295. </p>

  296. <dl compact="compact">

  297. <dt><code>stxdw [%d+offset16], %s</code></dt>

  298. <dd><p>Generic 64-bit store.

  299. </p></dd>

  300. <dt><code>stxw [%d+offset16], %s</code></dt>

  301. <dd><p>Generic 32-bit store.

  302. </p></dd>

  303. <dt><code>stxh [%d+offset16], %s</code></dt>

  304. <dd><p>Generic 16-bit store.

  305. </p></dd>

  306. <dt><code>stxb [%d+offset16], %s</code></dt>

  307. <dd><p>Generic 8-bit store.

  308. </p></dd>

  309. </dl>

  310. 

  311. <p>Store from immediates instructions:

  312. </p>

  313. <dl compact="compact">

  314. <dt><code>stddw [%d+offset16], imm32</code></dt>

  315. <dd><p>Store immediate as 64-bit.

  316. </p></dd>

  317. <dt><code>stdw [%d+offset16], imm32</code></dt>

  318. <dd><p>Store immediate as 32-bit.

  319. </p></dd>

  320. <dt><code>stdh [%d+offset16], imm32</code></dt>

  321. <dd><p>Store immediate as 16-bit.

  322. </p></dd>

  323. <dt><code>stdb [%d+offset16], imm32</code></dt>

  324. <dd><p>Store immediate as 8-bit.

  325. </p></dd>

  326. </dl>

  327. 

  328. <a name="Jump-instructions"></a>

  329. <h4 class="subsubsection">9.7.4.7 Jump instructions</h4>

  330. 

  331. <p>eBPF provides the following compare-and-jump instructions, which

  332. compare the values of the two given registers, or the values of a

  333. register and an immediate, and perform a branch in case the comparison

  334. holds true.

  335. </p>

  336. <dl compact="compact">

  337. <dt><code>ja %d,(%s|imm32),disp16</code></dt>

  338. <dd><p>Jump-always.

  339. </p></dd>

  340. <dt><code>jeq %d,(%s|imm32),disp16</code></dt>

  341. <dd><p>Jump if equal.

  342. </p></dd>

  343. <dt><code>jgt %d,(%s|imm32),disp16</code></dt>

  344. <dd><p>Jump if greater.

  345. </p></dd>

  346. <dt><code>jge %d,(%s|imm32),disp16</code></dt>

  347. <dd><p>Jump if greater or equal.

  348. </p></dd>

  349. <dt><code>jlt %d,(%s|imm32),disp16</code></dt>

  350. <dd><p>Jump if lesser.

  351. </p></dd>

  352. <dt><code>jle %d,(%s|imm32),disp16</code></dt>

  353. <dd><p>Jump if lesser or equal.

  354. </p></dd>

  355. <dt><code>jset %d,(%s|imm32),disp16</code></dt>

  356. <dd><p>Jump if signed equal.

  357. </p></dd>

  358. <dt><code>jne %d,(%s|imm32),disp16</code></dt>

  359. <dd><p>Jump if not equal.

  360. </p></dd>

  361. <dt><code>jsgt %d,(%s|imm32),disp16</code></dt>

  362. <dd><p>Jump if signed greater.

  363. </p></dd>

  364. <dt><code>jsge %d,(%s|imm32),disp16</code></dt>

  365. <dd><p>Jump if signed greater or equal.

  366. </p></dd>

  367. <dt><code>jslt %d,(%s|imm32),disp16</code></dt>

  368. <dd><p>Jump if signed lesser.

  369. </p></dd>

  370. <dt><code>jsle %d,(%s|imm32),disp16</code></dt>

  371. <dd><p>Jump if signed lesser or equal.

  372. </p></dd>

  373. </dl>

  374. 

  375. <p>A call instruction is provided in order to perform calls to other eBPF

  376. functions, or to external kernel helpers:

  377. </p>

  378. <dl compact="compact">

  379. <dt><code>call (disp32|imm32)</code></dt>

  380. <dd><p>Jump and link to the offset <em>disp32</em>, or to the kernel helper

  381. function identified by <em>imm32</em>.

  382. </p></dd>

  383. </dl>

  384. 

  385. <p>Finally:

  386. </p>

  387. <dl compact="compact">

  388. <dt><code>exit</code></dt>

  389. <dd><p>Terminate the eBPF program.

  390. </p></dd>

  391. </dl>

  392. 

  393. <a name="Atomic-instructions"></a>

  394. <h4 class="subsubsection">9.7.4.8 Atomic instructions</h4>

  395. 

  396. <p>Atomic exchange-and-add instructions are provided in two flavors: one

  397. for swapping 64-bit quantities and another for 32-bit quantities.

  398. </p>

  399. <dl compact="compact">

  400. <dt><code>xadddw [%d+offset16],%s</code></dt>

  401. <dd><p>Exchange-and-add a 64-bit value at the specified location.

  402. </p></dd>

  403. <dt><code>xaddw [%d+offset16],%s</code></dt>

  404. <dd><p>Exchange-and-add a 32-bit value at the specified location.

  405. </p></dd>

  406. </dl>

  407. 

  408. 

  409. <hr>

  410. <div class="header">

  411. <p>

  412. Previous: <a href="BPF-Directives.html#BPF-Directives" accesskey="p" rel="prev">BPF Directives</a>, Up: <a href="BPF_002dDependent.html#BPF_002dDependent" accesskey="u" rel="up">BPF-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>

  413. </div>

  414. 

  415. 

  416. 

  417. </body>

  418. </html>