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  15. <title>NDS32-Ops (Using as)</title>
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  56. <a name="NDS32_002dOps"></a>
  57. <div class="header">
  58. <p>
  59. Previous: <a href="NDS32_002dRegs.html#NDS32_002dRegs" accesskey="p" rel="prev">NDS32-Regs</a>, Up: <a href="NDS32-Syntax.html#NDS32-Syntax" accesskey="u" rel="up">NDS32 Syntax</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
  60. </div>
  61. <hr>
  62. <a name="Pseudo-Instructions-1"></a>
  63. <h4 class="subsubsection">9.30.2.3 Pseudo Instructions</h4>
  64. <dl compact="compact">
  65. <dt><code>li rt5,imm32</code></dt>
  66. <dd><p>load 32-bit integer into register rt5. &lsquo;<samp>sethi rt5,hi20(imm32)</samp>&rsquo; and then
  67. &lsquo;<samp>ori rt5,reg,lo12(imm32)</samp>&rsquo;.
  68. </p>
  69. </dd>
  70. <dt><code>la rt5,var</code></dt>
  71. <dd><p>Load 32-bit address of var into register rt5. &lsquo;<samp>sethi rt5,hi20(var)</samp>&rsquo; and
  72. then &lsquo;<samp>ori reg,rt5,lo12(var)</samp>&rsquo;
  73. </p>
  74. </dd>
  75. <dt><code>l.[bhw] rt5,var</code></dt>
  76. <dd><p>Load value of var into register rt5. &lsquo;<samp>sethi $ta,hi20(var)</samp>&rsquo; and then
  77. &lsquo;<samp>l[bhw]i rt5,[$ta+lo12(var)]</samp>&rsquo;
  78. </p>
  79. </dd>
  80. <dt><code>l.[bh]s rt5,var</code></dt>
  81. <dd><p>Load value of var into register rt5. &lsquo;<samp>sethi $ta,hi20(var)</samp>&rsquo; and then
  82. &lsquo;<samp>l[bh]si rt5,[$ta+lo12(var)]</samp>&rsquo;
  83. </p>
  84. </dd>
  85. <dt><code>l.[bhw]p rt5,var,inc</code></dt>
  86. <dd><p>Load value of var into register rt5 and increment $ta by amount inc.
  87. &lsquo;<samp>la $ta,var</samp>&rsquo; and then &lsquo;<samp>l[bhw]i.bi rt5,[$ta],inc</samp>&rsquo;
  88. </p>
  89. </dd>
  90. <dt><code>l.[bhw]pc rt5,inc</code></dt>
  91. <dd><p>Continue loading value of var into register rt5 and increment $ta by amount inc.
  92. &lsquo;<samp>l[bhw]i.bi rt5,[$ta],inc.</samp>&rsquo;
  93. </p>
  94. </dd>
  95. <dt><code>l.[bh]sp rt5,var,inc</code></dt>
  96. <dd><p>Load value of var into register rt5 and increment $ta by amount inc.
  97. &lsquo;<samp>la $ta,var</samp>&rsquo; and then &lsquo;<samp>l[bh]si.bi rt5,[$ta],inc</samp>&rsquo;
  98. </p>
  99. </dd>
  100. <dt><code>l.[bh]spc rt5,inc</code></dt>
  101. <dd><p>Continue loading value of var into register rt5 and increment $ta by amount inc.
  102. &lsquo;<samp>l[bh]si.bi rt5,[$ta],inc.</samp>&rsquo;
  103. </p>
  104. </dd>
  105. <dt><code>s.[bhw] rt5,var</code></dt>
  106. <dd><p>Store register rt5 to var.
  107. &lsquo;<samp>sethi $ta,hi20(var)</samp>&rsquo; and then &lsquo;<samp>s[bhw]i rt5,[$ta+lo12(var)]</samp>&rsquo;
  108. </p>
  109. </dd>
  110. <dt><code>s.[bhw]p rt5,var,inc</code></dt>
  111. <dd><p>Store register rt5 to var and increment $ta by amount inc.
  112. &lsquo;<samp>la $ta,var</samp>&rsquo; and then &lsquo;<samp>s[bhw]i.bi rt5,[$ta],inc</samp>&rsquo;
  113. </p>
  114. </dd>
  115. <dt><code>s.[bhw]pc rt5,inc</code></dt>
  116. <dd><p>Continue storing register rt5 to var and increment $ta by amount inc.
  117. &lsquo;<samp>s[bhw]i.bi rt5,[$ta],inc.</samp>&rsquo;
  118. </p>
  119. </dd>
  120. <dt><code>not rt5,ra5</code></dt>
  121. <dd><p>Alias of &lsquo;<samp>nor rt5,ra5,ra5</samp>&rsquo;.
  122. </p>
  123. </dd>
  124. <dt><code>neg rt5,ra5</code></dt>
  125. <dd><p>Alias of &lsquo;<samp>subri rt5,ra5,0</samp>&rsquo;.
  126. </p>
  127. </dd>
  128. <dt><code>br rb5</code></dt>
  129. <dd><p>Depending on how it is assembled, it is translated into &lsquo;<samp>r5 rb5</samp>&rsquo;
  130. or &lsquo;<samp>jr rb5</samp>&rsquo;.
  131. </p>
  132. </dd>
  133. <dt><code>b label</code></dt>
  134. <dd><p>Branch to label depending on how it is assembled, it is translated into
  135. &lsquo;<samp>j8 label</samp>&rsquo;, &lsquo;<samp>j label</samp>&rsquo;, or &quot;&lsquo;<samp>la $ta,label</samp>&rsquo; &lsquo;<samp>br $ta</samp>&rsquo;&quot;.
  136. </p>
  137. </dd>
  138. <dt><code>bral rb5</code></dt>
  139. <dd><p>Alias of jral br5 depending on how it is assembled, it is translated
  140. into &lsquo;<samp>jral5 rb5</samp>&rsquo; or &lsquo;<samp>jral rb5</samp>&rsquo;.
  141. </p>
  142. </dd>
  143. <dt><code>bal fname</code></dt>
  144. <dd><p>Alias of jal fname depending on how it is assembled, it is translated into
  145. &lsquo;<samp>jal fname</samp>&rsquo; or &quot;&lsquo;<samp>la $ta,fname</samp>&rsquo; &lsquo;<samp>bral $ta</samp>&rsquo;&quot;.
  146. </p>
  147. </dd>
  148. <dt><code>call fname</code></dt>
  149. <dd><p>Call function fname same as &lsquo;<samp>jal fname</samp>&rsquo;.
  150. </p>
  151. </dd>
  152. <dt><code>move rt5,ra5</code></dt>
  153. <dd><p>For 16-bit, this is &lsquo;<samp>mov55 rt5,ra5</samp>&rsquo;.
  154. For no 16-bit, this is &lsquo;<samp>ori rt5,ra5,0</samp>&rsquo;.
  155. </p>
  156. </dd>
  157. <dt><code>move rt5,var</code></dt>
  158. <dd><p>This is the same as &lsquo;<samp>l.w rt5,var</samp>&rsquo;.
  159. </p>
  160. </dd>
  161. <dt><code>move rt5,imm32</code></dt>
  162. <dd><p>This is the same as &lsquo;<samp>li rt5,imm32</samp>&rsquo;.
  163. </p>
  164. </dd>
  165. <dt><code>pushm ra5,rb5</code></dt>
  166. <dd><p>Push contents of registers from ra5 to rb5 into stack.
  167. </p>
  168. </dd>
  169. <dt><code>push ra5</code></dt>
  170. <dd><p>Push content of register ra5 into stack. (same &lsquo;<samp>pushm ra5,ra5</samp>&rsquo;).
  171. </p>
  172. </dd>
  173. <dt><code>push.d var</code></dt>
  174. <dd><p>Push value of double-word variable var into stack.
  175. </p>
  176. </dd>
  177. <dt><code>push.w var</code></dt>
  178. <dd><p>Push value of word variable var into stack.
  179. </p>
  180. </dd>
  181. <dt><code>push.h var</code></dt>
  182. <dd><p>Push value of half-word variable var into stack.
  183. </p>
  184. </dd>
  185. <dt><code>push.b var</code></dt>
  186. <dd><p>Push value of byte variable var into stack.
  187. </p>
  188. </dd>
  189. <dt><code>pusha var</code></dt>
  190. <dd><p>Push 32-bit address of variable var into stack.
  191. </p>
  192. </dd>
  193. <dt><code>pushi imm32</code></dt>
  194. <dd><p>Push 32-bit immediate value into stack.
  195. </p>
  196. </dd>
  197. <dt><code>popm ra5,rb5</code></dt>
  198. <dd><p>Pop top of stack values into registers ra5 to rb5.
  199. </p>
  200. </dd>
  201. <dt><code>pop rt5</code></dt>
  202. <dd><p>Pop top of stack value into register. (same as &lsquo;<samp>popm rt5,rt5</samp>&rsquo;.)
  203. </p>
  204. </dd>
  205. <dt><code>pop.d var,ra5</code></dt>
  206. <dd><p>Pop value of double-word variable var from stack using register ra5
  207. as 2nd scratch register. (1st is $ta)
  208. </p>
  209. </dd>
  210. <dt><code>pop.w var,ra5</code></dt>
  211. <dd><p>Pop value of word variable var from stack using register ra5.
  212. </p>
  213. </dd>
  214. <dt><code>pop.h var,ra5</code></dt>
  215. <dd><p>Pop value of half-word variable var from stack using register ra5.
  216. </p>
  217. </dd>
  218. <dt><code>pop.b var,ra5</code></dt>
  219. <dd><p>Pop value of byte variable var from stack using register ra5.
  220. </p>
  221. </dd>
  222. </dl>
  223. <hr>
  224. <div class="header">
  225. <p>
  226. Previous: <a href="NDS32_002dRegs.html#NDS32_002dRegs" accesskey="p" rel="prev">NDS32-Regs</a>, Up: <a href="NDS32-Syntax.html#NDS32-Syntax" accesskey="u" rel="up">NDS32 Syntax</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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