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- <a name="i386_002dRegs"></a>
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- <p>
- Next: <a href="i386_002dPrefixes.html#i386_002dPrefixes" accesskey="n" rel="next">i386-Prefixes</a>, Previous: <a href="i386_002dMnemonics.html#i386_002dMnemonics" accesskey="p" rel="prev">i386-Mnemonics</a>, Up: <a href="i386_002dDependent.html#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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- <hr>
- <a name="Register-Naming"></a>
- <h4 class="subsection">9.16.5 Register Naming</h4>
-
- <a name="index-i386-registers"></a>
- <a name="index-registers_002c-i386"></a>
- <a name="index-x86_002d64-registers"></a>
- <a name="index-registers_002c-x86_002d64"></a>
- <p>Register operands are always prefixed with ‘<samp>%</samp>’. The 80386 registers
- consist of
- </p>
- <ul>
- <li> the 8 32-bit registers ‘<samp>%eax</samp>’ (the accumulator), ‘<samp>%ebx</samp>’,
- ‘<samp>%ecx</samp>’, ‘<samp>%edx</samp>’, ‘<samp>%edi</samp>’, ‘<samp>%esi</samp>’, ‘<samp>%ebp</samp>’ (the
- frame pointer), and ‘<samp>%esp</samp>’ (the stack pointer).
-
- </li><li> the 8 16-bit low-ends of these: ‘<samp>%ax</samp>’, ‘<samp>%bx</samp>’, ‘<samp>%cx</samp>’,
- ‘<samp>%dx</samp>’, ‘<samp>%di</samp>’, ‘<samp>%si</samp>’, ‘<samp>%bp</samp>’, and ‘<samp>%sp</samp>’.
-
- </li><li> the 8 8-bit registers: ‘<samp>%ah</samp>’, ‘<samp>%al</samp>’, ‘<samp>%bh</samp>’,
- ‘<samp>%bl</samp>’, ‘<samp>%ch</samp>’, ‘<samp>%cl</samp>’, ‘<samp>%dh</samp>’, and ‘<samp>%dl</samp>’ (These
- are the high-bytes and low-bytes of ‘<samp>%ax</samp>’, ‘<samp>%bx</samp>’,
- ‘<samp>%cx</samp>’, and ‘<samp>%dx</samp>’)
-
- </li><li> the 6 section registers ‘<samp>%cs</samp>’ (code section), ‘<samp>%ds</samp>’
- (data section), ‘<samp>%ss</samp>’ (stack section), ‘<samp>%es</samp>’, ‘<samp>%fs</samp>’,
- and ‘<samp>%gs</samp>’.
-
- </li><li> the 5 processor control registers ‘<samp>%cr0</samp>’, ‘<samp>%cr2</samp>’,
- ‘<samp>%cr3</samp>’, ‘<samp>%cr4</samp>’, and ‘<samp>%cr8</samp>’.
-
- </li><li> the 6 debug registers ‘<samp>%db0</samp>’, ‘<samp>%db1</samp>’, ‘<samp>%db2</samp>’,
- ‘<samp>%db3</samp>’, ‘<samp>%db6</samp>’, and ‘<samp>%db7</samp>’.
-
- </li><li> the 2 test registers ‘<samp>%tr6</samp>’ and ‘<samp>%tr7</samp>’.
-
- </li><li> the 8 floating point register stack ‘<samp>%st</samp>’ or equivalently
- ‘<samp>%st(0)</samp>’, ‘<samp>%st(1)</samp>’, ‘<samp>%st(2)</samp>’, ‘<samp>%st(3)</samp>’,
- ‘<samp>%st(4)</samp>’, ‘<samp>%st(5)</samp>’, ‘<samp>%st(6)</samp>’, and ‘<samp>%st(7)</samp>’.
- These registers are overloaded by 8 MMX registers ‘<samp>%mm0</samp>’,
- ‘<samp>%mm1</samp>’, ‘<samp>%mm2</samp>’, ‘<samp>%mm3</samp>’, ‘<samp>%mm4</samp>’, ‘<samp>%mm5</samp>’,
- ‘<samp>%mm6</samp>’ and ‘<samp>%mm7</samp>’.
-
- </li><li> the 8 128-bit SSE registers registers ‘<samp>%xmm0</samp>’, ‘<samp>%xmm1</samp>’, ‘<samp>%xmm2</samp>’,
- ‘<samp>%xmm3</samp>’, ‘<samp>%xmm4</samp>’, ‘<samp>%xmm5</samp>’, ‘<samp>%xmm6</samp>’ and ‘<samp>%xmm7</samp>’.
- </li></ul>
-
- <p>The AMD x86-64 architecture extends the register set by:
- </p>
- <ul>
- <li> enhancing the 8 32-bit registers to 64-bit: ‘<samp>%rax</samp>’ (the
- accumulator), ‘<samp>%rbx</samp>’, ‘<samp>%rcx</samp>’, ‘<samp>%rdx</samp>’, ‘<samp>%rdi</samp>’,
- ‘<samp>%rsi</samp>’, ‘<samp>%rbp</samp>’ (the frame pointer), ‘<samp>%rsp</samp>’ (the stack
- pointer)
-
- </li><li> the 8 extended registers ‘<samp>%r8</samp>’–‘<samp>%r15</samp>’.
-
- </li><li> the 8 32-bit low ends of the extended registers: ‘<samp>%r8d</samp>’–‘<samp>%r15d</samp>’.
-
- </li><li> the 8 16-bit low ends of the extended registers: ‘<samp>%r8w</samp>’–‘<samp>%r15w</samp>’.
-
- </li><li> the 8 8-bit low ends of the extended registers: ‘<samp>%r8b</samp>’–‘<samp>%r15b</samp>’.
-
- </li><li> the 4 8-bit registers: ‘<samp>%sil</samp>’, ‘<samp>%dil</samp>’, ‘<samp>%bpl</samp>’, ‘<samp>%spl</samp>’.
-
- </li><li> the 8 debug registers: ‘<samp>%db8</samp>’–‘<samp>%db15</samp>’.
-
- </li><li> the 8 128-bit SSE registers: ‘<samp>%xmm8</samp>’–‘<samp>%xmm15</samp>’.
- </li></ul>
-
- <p>With the AVX extensions more registers were made available:
- </p>
- <ul>
- <li> the 16 256-bit SSE ‘<samp>%ymm0</samp>’–‘<samp>%ymm15</samp>’ (only the first 8
- available in 32-bit mode). The bottom 128 bits are overlaid with the
- ‘<samp>xmm0</samp>’–‘<samp>xmm15</samp>’ registers.
-
- </li></ul>
-
- <p>The AVX512 extensions added the following registers:
- </p>
- <ul>
- <li> the 32 512-bit registers ‘<samp>%zmm0</samp>’–‘<samp>%zmm31</samp>’ (only the first 8
- available in 32-bit mode). The bottom 128 bits are overlaid with the
- ‘<samp>%xmm0</samp>’–‘<samp>%xmm31</samp>’ registers and the first 256 bits are
- overlaid with the ‘<samp>%ymm0</samp>’–‘<samp>%ymm31</samp>’ registers.
-
- </li><li> the 8 mask registers ‘<samp>%k0</samp>’–‘<samp>%k7</samp>’.
-
- </li></ul>
-
- <hr>
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- Next: <a href="i386_002dPrefixes.html#i386_002dPrefixes" accesskey="n" rel="next">i386-Prefixes</a>, Previous: <a href="i386_002dMnemonics.html#i386_002dMnemonics" accesskey="p" rel="prev">i386-Mnemonics</a>, Up: <a href="i386_002dDependent.html#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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