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  1. <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">

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  25. <title>MIPS Options (Using the GNU Compiler Collection (GCC))</title>

  26. 

  27. <meta name="description" content="MIPS Options (Using the GNU Compiler Collection (GCC))">

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  33. <link href="Option-Index.html#Option-Index" rel="index" title="Option Index">

  34. <link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">

  35. <link href="Submodel-Options.html#Submodel-Options" rel="up" title="Submodel Options">

  36. <link href="MMIX-Options.html#MMIX-Options" rel="next" title="MMIX Options">

  37. <link href="MicroBlaze-Options.html#MicroBlaze-Options" rel="prev" title="MicroBlaze Options">

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  67. </head>

  68. 

  69. <body lang="en">

  70. <a name="MIPS-Options"></a>

  71. <div class="header">

  72. <p>

  73. Next: <a href="MMIX-Options.html#MMIX-Options" accesskey="n" rel="next">MMIX Options</a>, Previous: <a href="MicroBlaze-Options.html#MicroBlaze-Options" accesskey="p" rel="prev">MicroBlaze Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>

  74. </div>

  75. <hr>

  76. <a name="MIPS-Options-1"></a>

  77. <h4 class="subsection">3.19.29 MIPS Options</h4>

  78. <a name="index-MIPS-options"></a>

  79. 

  80. <dl compact="compact">

  81. <dt><code>-EB</code></dt>

  82. <dd><a name="index-EB-2"></a>

  83. <p>Generate big-endian code.

  84. </p>

  85. </dd>

  86. <dt><code>-EL</code></dt>

  87. <dd><a name="index-EL-2"></a>

  88. <p>Generate little-endian code.  This is the default for &lsquo;<samp>mips*el-*-*</samp>&rsquo;

  89. configurations.

  90. </p>

  91. </dd>

  92. <dt><code>-march=<var>arch</var></code></dt>

  93. <dd><a name="index-march-8"></a>

  94. <p>Generate code that runs on <var>arch</var>, which can be the name of a

  95. generic MIPS ISA, or the name of a particular processor.

  96. The ISA names are:

  97. &lsquo;<samp>mips1</samp>&rsquo;, &lsquo;<samp>mips2</samp>&rsquo;, &lsquo;<samp>mips3</samp>&rsquo;, &lsquo;<samp>mips4</samp>&rsquo;,

  98. &lsquo;<samp>mips32</samp>&rsquo;, &lsquo;<samp>mips32r2</samp>&rsquo;, &lsquo;<samp>mips32r3</samp>&rsquo;, &lsquo;<samp>mips32r5</samp>&rsquo;,

  99. &lsquo;<samp>mips32r6</samp>&rsquo;, &lsquo;<samp>mips64</samp>&rsquo;, &lsquo;<samp>mips64r2</samp>&rsquo;, &lsquo;<samp>mips64r3</samp>&rsquo;,

  100. &lsquo;<samp>mips64r5</samp>&rsquo; and &lsquo;<samp>mips64r6</samp>&rsquo;.

  101. The processor names are:

  102. &lsquo;<samp>4kc</samp>&rsquo;, &lsquo;<samp>4km</samp>&rsquo;, &lsquo;<samp>4kp</samp>&rsquo;, &lsquo;<samp>4ksc</samp>&rsquo;,

  103. &lsquo;<samp>4kec</samp>&rsquo;, &lsquo;<samp>4kem</samp>&rsquo;, &lsquo;<samp>4kep</samp>&rsquo;, &lsquo;<samp>4ksd</samp>&rsquo;,

  104. &lsquo;<samp>5kc</samp>&rsquo;, &lsquo;<samp>5kf</samp>&rsquo;,

  105. &lsquo;<samp>20kc</samp>&rsquo;,

  106. &lsquo;<samp>24kc</samp>&rsquo;, &lsquo;<samp>24kf2_1</samp>&rsquo;, &lsquo;<samp>24kf1_1</samp>&rsquo;,

  107. &lsquo;<samp>24kec</samp>&rsquo;, &lsquo;<samp>24kef2_1</samp>&rsquo;, &lsquo;<samp>24kef1_1</samp>&rsquo;,

  108. &lsquo;<samp>34kc</samp>&rsquo;, &lsquo;<samp>34kf2_1</samp>&rsquo;, &lsquo;<samp>34kf1_1</samp>&rsquo;, &lsquo;<samp>34kn</samp>&rsquo;,

  109. &lsquo;<samp>74kc</samp>&rsquo;, &lsquo;<samp>74kf2_1</samp>&rsquo;, &lsquo;<samp>74kf1_1</samp>&rsquo;, &lsquo;<samp>74kf3_2</samp>&rsquo;,

  110. &lsquo;<samp>1004kc</samp>&rsquo;, &lsquo;<samp>1004kf2_1</samp>&rsquo;, &lsquo;<samp>1004kf1_1</samp>&rsquo;,

  111. &lsquo;<samp>i6400</samp>&rsquo;, &lsquo;<samp>i6500</samp>&rsquo;,

  112. &lsquo;<samp>interaptiv</samp>&rsquo;,

  113. &lsquo;<samp>loongson2e</samp>&rsquo;, &lsquo;<samp>loongson2f</samp>&rsquo;, &lsquo;<samp>loongson3a</samp>&rsquo;, &lsquo;<samp>gs464</samp>&rsquo;,

  114. &lsquo;<samp>gs464e</samp>&rsquo;, &lsquo;<samp>gs264e</samp>&rsquo;,

  115. &lsquo;<samp>m4k</samp>&rsquo;,

  116. &lsquo;<samp>m14k</samp>&rsquo;, &lsquo;<samp>m14kc</samp>&rsquo;, &lsquo;<samp>m14ke</samp>&rsquo;, &lsquo;<samp>m14kec</samp>&rsquo;,

  117. &lsquo;<samp>m5100</samp>&rsquo;, &lsquo;<samp>m5101</samp>&rsquo;,

  118. &lsquo;<samp>octeon</samp>&rsquo;, &lsquo;<samp>octeon+</samp>&rsquo;, &lsquo;<samp>octeon2</samp>&rsquo;, &lsquo;<samp>octeon3</samp>&rsquo;,

  119. &lsquo;<samp>orion</samp>&rsquo;,

  120. &lsquo;<samp>p5600</samp>&rsquo;, &lsquo;<samp>p6600</samp>&rsquo;,

  121. &lsquo;<samp>r2000</samp>&rsquo;, &lsquo;<samp>r3000</samp>&rsquo;, &lsquo;<samp>r3900</samp>&rsquo;, &lsquo;<samp>r4000</samp>&rsquo;, &lsquo;<samp>r4400</samp>&rsquo;,

  122. &lsquo;<samp>r4600</samp>&rsquo;, &lsquo;<samp>r4650</samp>&rsquo;, &lsquo;<samp>r4700</samp>&rsquo;, &lsquo;<samp>r5900</samp>&rsquo;,

  123. &lsquo;<samp>r6000</samp>&rsquo;, &lsquo;<samp>r8000</samp>&rsquo;,

  124. &lsquo;<samp>rm7000</samp>&rsquo;, &lsquo;<samp>rm9000</samp>&rsquo;,

  125. &lsquo;<samp>r10000</samp>&rsquo;, &lsquo;<samp>r12000</samp>&rsquo;, &lsquo;<samp>r14000</samp>&rsquo;, &lsquo;<samp>r16000</samp>&rsquo;,

  126. &lsquo;<samp>sb1</samp>&rsquo;,

  127. &lsquo;<samp>sr71000</samp>&rsquo;,

  128. &lsquo;<samp>vr4100</samp>&rsquo;, &lsquo;<samp>vr4111</samp>&rsquo;, &lsquo;<samp>vr4120</samp>&rsquo;, &lsquo;<samp>vr4130</samp>&rsquo;, &lsquo;<samp>vr4300</samp>&rsquo;,

  129. &lsquo;<samp>vr5000</samp>&rsquo;, &lsquo;<samp>vr5400</samp>&rsquo;, &lsquo;<samp>vr5500</samp>&rsquo;,

  130. &lsquo;<samp>xlr</samp>&rsquo; and &lsquo;<samp>xlp</samp>&rsquo;.

  131. The special value &lsquo;<samp>from-abi</samp>&rsquo; selects the

  132. most compatible architecture for the selected ABI (that is,

  133. &lsquo;<samp>mips1</samp>&rsquo; for 32-bit ABIs and &lsquo;<samp>mips3</samp>&rsquo; for 64-bit ABIs).

  134. </p>

  135. <p>The native Linux/GNU toolchain also supports the value &lsquo;<samp>native</samp>&rsquo;,

  136. which selects the best architecture option for the host processor.

  137. <samp>-march=native</samp> has no effect if GCC does not recognize

  138. the processor.

  139. </p>

  140. <p>In processor names, a final &lsquo;<samp>000</samp>&rsquo; can be abbreviated as &lsquo;<samp>k</samp>&rsquo;

  141. (for example, <samp>-march=r2k</samp>).  Prefixes are optional, and

  142. &lsquo;<samp>vr</samp>&rsquo; may be written &lsquo;<samp>r</samp>&rsquo;.

  143. </p>

  144. <p>Names of the form &lsquo;<samp><var>n</var>f2_1</samp>&rsquo; refer to processors with

  145. FPUs clocked at half the rate of the core, names of the form

  146. &lsquo;<samp><var>n</var>f1_1</samp>&rsquo; refer to processors with FPUs clocked at the same

  147. rate as the core, and names of the form &lsquo;<samp><var>n</var>f3_2</samp>&rsquo; refer to

  148. processors with FPUs clocked a ratio of 3:2 with respect to the core.

  149. For compatibility reasons, &lsquo;<samp><var>n</var>f</samp>&rsquo; is accepted as a synonym

  150. for &lsquo;<samp><var>n</var>f2_1</samp>&rsquo; while &lsquo;<samp><var>n</var>x</samp>&rsquo; and &lsquo;<samp><var>b</var>fx</samp>&rsquo; are

  151. accepted as synonyms for &lsquo;<samp><var>n</var>f1_1</samp>&rsquo;.

  152. </p>

  153. <p>GCC defines two macros based on the value of this option.  The first

  154. is <code>_MIPS_ARCH</code>, which gives the name of target architecture, as

  155. a string.  The second has the form <code>_MIPS_ARCH_<var>foo</var></code>,

  156. where <var>foo</var> is the capitalized value of <code>_MIPS_ARCH</code>.

  157. For example, <samp>-march=r2000</samp> sets <code>_MIPS_ARCH</code>

  158. to <code>&quot;r2000&quot;</code> and defines the macro <code>_MIPS_ARCH_R2000</code>.

  159. </p>

  160. <p>Note that the <code>_MIPS_ARCH</code> macro uses the processor names given

  161. above.  In other words, it has the full prefix and does not

  162. abbreviate &lsquo;<samp>000</samp>&rsquo; as &lsquo;<samp>k</samp>&rsquo;.  In the case of &lsquo;<samp>from-abi</samp>&rsquo;,

  163. the macro names the resolved architecture (either <code>&quot;mips1&quot;</code> or

  164. <code>&quot;mips3&quot;</code>).  It names the default architecture when no

  165. <samp>-march</samp> option is given.

  166. </p>

  167. </dd>

  168. <dt><code>-mtune=<var>arch</var></code></dt>

  169. <dd><a name="index-mtune-9"></a>

  170. <p>Optimize for <var>arch</var>.  Among other things, this option controls

  171. the way instructions are scheduled, and the perceived cost of arithmetic

  172. operations.  The list of <var>arch</var> values is the same as for

  173. <samp>-march</samp>.

  174. </p>

  175. <p>When this option is not used, GCC optimizes for the processor

  176. specified by <samp>-march</samp>.  By using <samp>-march</samp> and

  177. <samp>-mtune</samp> together, it is possible to generate code that

  178. runs on a family of processors, but optimize the code for one

  179. particular member of that family.

  180. </p>

  181. <p><samp>-mtune</samp> defines the macros <code>_MIPS_TUNE</code> and

  182. <code>_MIPS_TUNE_<var>foo</var></code>, which work in the same way as the

  183. <samp>-march</samp> ones described above.

  184. </p>

  185. </dd>

  186. <dt><code>-mips1</code></dt>

  187. <dd><a name="index-mips1"></a>

  188. <p>Equivalent to <samp>-march=mips1</samp>.

  189. </p>

  190. </dd>

  191. <dt><code>-mips2</code></dt>

  192. <dd><a name="index-mips2"></a>

  193. <p>Equivalent to <samp>-march=mips2</samp>.

  194. </p>

  195. </dd>

  196. <dt><code>-mips3</code></dt>

  197. <dd><a name="index-mips3"></a>

  198. <p>Equivalent to <samp>-march=mips3</samp>.

  199. </p>

  200. </dd>

  201. <dt><code>-mips4</code></dt>

  202. <dd><a name="index-mips4"></a>

  203. <p>Equivalent to <samp>-march=mips4</samp>.

  204. </p>

  205. </dd>

  206. <dt><code>-mips32</code></dt>

  207. <dd><a name="index-mips32"></a>

  208. <p>Equivalent to <samp>-march=mips32</samp>.

  209. </p>

  210. </dd>

  211. <dt><code>-mips32r3</code></dt>

  212. <dd><a name="index-mips32r3"></a>

  213. <p>Equivalent to <samp>-march=mips32r3</samp>.

  214. </p>

  215. </dd>

  216. <dt><code>-mips32r5</code></dt>

  217. <dd><a name="index-mips32r5"></a>

  218. <p>Equivalent to <samp>-march=mips32r5</samp>.

  219. </p>

  220. </dd>

  221. <dt><code>-mips32r6</code></dt>

  222. <dd><a name="index-mips32r6"></a>

  223. <p>Equivalent to <samp>-march=mips32r6</samp>.

  224. </p>

  225. </dd>

  226. <dt><code>-mips64</code></dt>

  227. <dd><a name="index-mips64"></a>

  228. <p>Equivalent to <samp>-march=mips64</samp>.

  229. </p>

  230. </dd>

  231. <dt><code>-mips64r2</code></dt>

  232. <dd><a name="index-mips64r2"></a>

  233. <p>Equivalent to <samp>-march=mips64r2</samp>.

  234. </p>

  235. </dd>

  236. <dt><code>-mips64r3</code></dt>

  237. <dd><a name="index-mips64r3"></a>

  238. <p>Equivalent to <samp>-march=mips64r3</samp>.

  239. </p>

  240. </dd>

  241. <dt><code>-mips64r5</code></dt>

  242. <dd><a name="index-mips64r5"></a>

  243. <p>Equivalent to <samp>-march=mips64r5</samp>.

  244. </p>

  245. </dd>

  246. <dt><code>-mips64r6</code></dt>

  247. <dd><a name="index-mips64r6"></a>

  248. <p>Equivalent to <samp>-march=mips64r6</samp>.

  249. </p>

  250. </dd>

  251. <dt><code>-mips16</code></dt>

  252. <dt><code>-mno-mips16</code></dt>

  253. <dd><a name="index-mips16"></a>

  254. <a name="index-mno_002dmips16"></a>

  255. <p>Generate (do not generate) MIPS16 code.  If GCC is targeting a

  256. MIPS32 or MIPS64 architecture, it makes use of the MIPS16e ASE.

  257. </p>

  258. <p>MIPS16 code generation can also be controlled on a per-function basis

  259. by means of <code>mips16</code> and <code>nomips16</code> attributes.

  260. See <a href="Function-Attributes.html#Function-Attributes">Function Attributes</a>, for more information.

  261. </p>

  262. </dd>

  263. <dt><code>-mflip-mips16</code></dt>

  264. <dd><a name="index-mflip_002dmips16"></a>

  265. <p>Generate MIPS16 code on alternating functions.  This option is provided

  266. for regression testing of mixed MIPS16/non-MIPS16 code generation, and is

  267. not intended for ordinary use in compiling user code.

  268. </p>

  269. </dd>

  270. <dt><code>-minterlink-compressed</code></dt>

  271. <dt><code>-mno-interlink-compressed</code></dt>

  272. <dd><a name="index-minterlink_002dcompressed"></a>

  273. <a name="index-mno_002dinterlink_002dcompressed"></a>

  274. <p>Require (do not require) that code using the standard (uncompressed) MIPS ISA

  275. be link-compatible with MIPS16 and microMIPS code, and vice versa.

  276. </p>

  277. <p>For example, code using the standard ISA encoding cannot jump directly

  278. to MIPS16 or microMIPS code; it must either use a call or an indirect jump.

  279. <samp>-minterlink-compressed</samp> therefore disables direct jumps unless GCC

  280. knows that the target of the jump is not compressed.

  281. </p>

  282. </dd>

  283. <dt><code>-minterlink-mips16</code></dt>

  284. <dt><code>-mno-interlink-mips16</code></dt>

  285. <dd><a name="index-minterlink_002dmips16"></a>

  286. <a name="index-mno_002dinterlink_002dmips16"></a>

  287. <p>Aliases of <samp>-minterlink-compressed</samp> and

  288. <samp>-mno-interlink-compressed</samp>.  These options predate the microMIPS ASE

  289. and are retained for backwards compatibility.

  290. </p>

  291. </dd>

  292. <dt><code>-mabi=32</code></dt>

  293. <dt><code>-mabi=o64</code></dt>

  294. <dt><code>-mabi=n32</code></dt>

  295. <dt><code>-mabi=64</code></dt>

  296. <dt><code>-mabi=eabi</code></dt>

  297. <dd><a name="index-mabi_003d32"></a>

  298. <a name="index-mabi_003do64"></a>

  299. <a name="index-mabi_003dn32"></a>

  300. <a name="index-mabi_003d64"></a>

  301. <a name="index-mabi_003deabi"></a>

  302. <p>Generate code for the given ABI.

  303. </p>

  304. <p>Note that the EABI has a 32-bit and a 64-bit variant.  GCC normally

  305. generates 64-bit code when you select a 64-bit architecture, but you

  306. can use <samp>-mgp32</samp> to get 32-bit code instead.

  307. </p>

  308. <p>For information about the O64 ABI, see

  309. <a href="http://gcc.gnu.org/projects/mipso64-abi.html">http://gcc.gnu.org/projects/mipso64-abi.html</a>.

  310. </p>

  311. <p>GCC supports a variant of the o32 ABI in which floating-point registers

  312. are 64 rather than 32 bits wide.  You can select this combination with

  313. <samp>-mabi=32</samp> <samp>-mfp64</samp>.  This ABI relies on the <code>mthc1</code>

  314. and <code>mfhc1</code> instructions and is therefore only supported for

  315. MIPS32R2, MIPS32R3 and MIPS32R5 processors.

  316. </p>

  317. <p>The register assignments for arguments and return values remain the

  318. same, but each scalar value is passed in a single 64-bit register

  319. rather than a pair of 32-bit registers.  For example, scalar

  320. floating-point values are returned in &lsquo;<samp>$f0</samp>&rsquo; only, not a

  321. &lsquo;<samp>$f0</samp>&rsquo;/&lsquo;<samp>$f1</samp>&rsquo; pair.  The set of call-saved registers also

  322. remains the same in that the even-numbered double-precision registers

  323. are saved.

  324. </p>

  325. <p>Two additional variants of the o32 ABI are supported to enable

  326. a transition from 32-bit to 64-bit registers.  These are FPXX

  327. (<samp>-mfpxx</samp>) and FP64A (<samp>-mfp64</samp> <samp>-mno-odd-spreg</samp>).

  328. The FPXX extension mandates that all code must execute correctly

  329. when run using 32-bit or 64-bit registers.  The code can be interlinked

  330. with either FP32 or FP64, but not both.

  331. The FP64A extension is similar to the FP64 extension but forbids the

  332. use of odd-numbered single-precision registers.  This can be used

  333. in conjunction with the <code>FRE</code> mode of FPUs in MIPS32R5

  334. processors and allows both FP32 and FP64A code to interlink and

  335. run in the same process without changing FPU modes.

  336. </p>

  337. </dd>

  338. <dt><code>-mabicalls</code></dt>

  339. <dt><code>-mno-abicalls</code></dt>

  340. <dd><a name="index-mabicalls"></a>

  341. <a name="index-mno_002dabicalls"></a>

  342. <p>Generate (do not generate) code that is suitable for SVR4-style

  343. dynamic objects.  <samp>-mabicalls</samp> is the default for SVR4-based

  344. systems.

  345. </p>

  346. </dd>

  347. <dt><code>-mshared</code></dt>

  348. <dt><code>-mno-shared</code></dt>

  349. <dd><p>Generate (do not generate) code that is fully position-independent,

  350. and that can therefore be linked into shared libraries.  This option

  351. only affects <samp>-mabicalls</samp>.

  352. </p>

  353. <p>All <samp>-mabicalls</samp> code has traditionally been position-independent,

  354. regardless of options like <samp>-fPIC</samp> and <samp>-fpic</samp>.  However,

  355. as an extension, the GNU toolchain allows executables to use absolute

  356. accesses for locally-binding symbols.  It can also use shorter GP

  357. initialization sequences and generate direct calls to locally-defined

  358. functions.  This mode is selected by <samp>-mno-shared</samp>.

  359. </p>

  360. <p><samp>-mno-shared</samp> depends on binutils 2.16 or higher and generates

  361. objects that can only be linked by the GNU linker.  However, the option

  362. does not affect the ABI of the final executable; it only affects the ABI

  363. of relocatable objects.  Using <samp>-mno-shared</samp> generally makes

  364. executables both smaller and quicker.

  365. </p>

  366. <p><samp>-mshared</samp> is the default.

  367. </p>

  368. </dd>

  369. <dt><code>-mplt</code></dt>

  370. <dt><code>-mno-plt</code></dt>

  371. <dd><a name="index-mplt"></a>

  372. <a name="index-mno_002dplt"></a>

  373. <p>Assume (do not assume) that the static and dynamic linkers

  374. support PLTs and copy relocations.  This option only affects

  375. <samp>-mno-shared -mabicalls</samp>.  For the n64 ABI, this option

  376. has no effect without <samp>-msym32</samp>.

  377. </p>

  378. <p>You can make <samp>-mplt</samp> the default by configuring

  379. GCC with <samp>--with-mips-plt</samp>.  The default is

  380. <samp>-mno-plt</samp> otherwise.

  381. </p>

  382. </dd>

  383. <dt><code>-mxgot</code></dt>

  384. <dt><code>-mno-xgot</code></dt>

  385. <dd><a name="index-mxgot-1"></a>

  386. <a name="index-mno_002dxgot-1"></a>

  387. <p>Lift (do not lift) the usual restrictions on the size of the global

  388. offset table.

  389. </p>

  390. <p>GCC normally uses a single instruction to load values from the GOT.

  391. While this is relatively efficient, it only works if the GOT

  392. is smaller than about 64k.  Anything larger causes the linker

  393. to report an error such as:

  394. </p>

  395. <a name="index-relocation-truncated-to-fit-_0028MIPS_0029"></a>

  396. <div class="smallexample">

  397. <pre class="smallexample">relocation truncated to fit: R_MIPS_GOT16 foobar

  398. </pre></div>

  399. 

  400. <p>If this happens, you should recompile your code with <samp>-mxgot</samp>.

  401. This works with very large GOTs, although the code is also

  402. less efficient, since it takes three instructions to fetch the

  403. value of a global symbol.

  404. </p>

  405. <p>Note that some linkers can create multiple GOTs.  If you have such a

  406. linker, you should only need to use <samp>-mxgot</samp> when a single object

  407. file accesses more than 64k&rsquo;s worth of GOT entries.  Very few do.

  408. </p>

  409. <p>These options have no effect unless GCC is generating position

  410. independent code.

  411. </p>

  412. </dd>

  413. <dt><code>-mgp32</code></dt>

  414. <dd><a name="index-mgp32"></a>

  415. <p>Assume that general-purpose registers are 32 bits wide.

  416. </p>

  417. </dd>

  418. <dt><code>-mgp64</code></dt>

  419. <dd><a name="index-mgp64"></a>

  420. <p>Assume that general-purpose registers are 64 bits wide.

  421. </p>

  422. </dd>

  423. <dt><code>-mfp32</code></dt>

  424. <dd><a name="index-mfp32"></a>

  425. <p>Assume that floating-point registers are 32 bits wide.

  426. </p>

  427. </dd>

  428. <dt><code>-mfp64</code></dt>

  429. <dd><a name="index-mfp64"></a>

  430. <p>Assume that floating-point registers are 64 bits wide.

  431. </p>

  432. </dd>

  433. <dt><code>-mfpxx</code></dt>

  434. <dd><a name="index-mfpxx"></a>

  435. <p>Do not assume the width of floating-point registers.

  436. </p>

  437. </dd>

  438. <dt><code>-mhard-float</code></dt>

  439. <dd><a name="index-mhard_002dfloat-4"></a>

  440. <p>Use floating-point coprocessor instructions.

  441. </p>

  442. </dd>

  443. <dt><code>-msoft-float</code></dt>

  444. <dd><a name="index-msoft_002dfloat-7"></a>

  445. <p>Do not use floating-point coprocessor instructions.  Implement

  446. floating-point calculations using library calls instead.

  447. </p>

  448. </dd>

  449. <dt><code>-mno-float</code></dt>

  450. <dd><a name="index-mno_002dfloat"></a>

  451. <p>Equivalent to <samp>-msoft-float</samp>, but additionally asserts that the

  452. program being compiled does not perform any floating-point operations.

  453. This option is presently supported only by some bare-metal MIPS

  454. configurations, where it may select a special set of libraries

  455. that lack all floating-point support (including, for example, the

  456. floating-point <code>printf</code> formats).  

  457. If code compiled with <samp>-mno-float</samp> accidentally contains

  458. floating-point operations, it is likely to suffer a link-time

  459. or run-time failure.

  460. </p>

  461. </dd>

  462. <dt><code>-msingle-float</code></dt>

  463. <dd><a name="index-msingle_002dfloat"></a>

  464. <p>Assume that the floating-point coprocessor only supports single-precision

  465. operations.

  466. </p>

  467. </dd>

  468. <dt><code>-mdouble-float</code></dt>

  469. <dd><a name="index-mdouble_002dfloat-1"></a>

  470. <p>Assume that the floating-point coprocessor supports double-precision

  471. operations.  This is the default.

  472. </p>

  473. </dd>

  474. <dt><code>-modd-spreg</code></dt>

  475. <dt><code>-mno-odd-spreg</code></dt>

  476. <dd><a name="index-modd_002dspreg"></a>

  477. <a name="index-mno_002dodd_002dspreg"></a>

  478. <p>Enable the use of odd-numbered single-precision floating-point registers

  479. for the o32 ABI.  This is the default for processors that are known to

  480. support these registers.  When using the o32 FPXX ABI, <samp>-mno-odd-spreg</samp>

  481. is set by default.

  482. </p>

  483. </dd>

  484. <dt><code>-mabs=2008</code></dt>

  485. <dt><code>-mabs=legacy</code></dt>

  486. <dd><a name="index-mabs_003d2008"></a>

  487. <a name="index-mabs_003dlegacy"></a>

  488. <p>These options control the treatment of the special not-a-number (NaN)

  489. IEEE 754 floating-point data with the <code>abs.<i>fmt</i></code> and

  490. <code>neg.<i>fmt</i></code> machine instructions.

  491. </p>

  492. <p>By default or when <samp>-mabs=legacy</samp> is used the legacy

  493. treatment is selected.  In this case these instructions are considered

  494. arithmetic and avoided where correct operation is required and the

  495. input operand might be a NaN.  A longer sequence of instructions that

  496. manipulate the sign bit of floating-point datum manually is used

  497. instead unless the <samp>-ffinite-math-only</samp> option has also been

  498. specified.

  499. </p>

  500. <p>The <samp>-mabs=2008</samp> option selects the IEEE 754-2008 treatment.  In

  501. this case these instructions are considered non-arithmetic and therefore

  502. operating correctly in all cases, including in particular where the

  503. input operand is a NaN.  These instructions are therefore always used

  504. for the respective operations.

  505. </p>

  506. </dd>

  507. <dt><code>-mnan=2008</code></dt>

  508. <dt><code>-mnan=legacy</code></dt>

  509. <dd><a name="index-mnan_003d2008"></a>

  510. <a name="index-mnan_003dlegacy"></a>

  511. <p>These options control the encoding of the special not-a-number (NaN)

  512. IEEE 754 floating-point data.

  513. </p>

  514. <p>The <samp>-mnan=legacy</samp> option selects the legacy encoding.  In this

  515. case quiet NaNs (qNaNs) are denoted by the first bit of their trailing

  516. significand field being 0, whereas signaling NaNs (sNaNs) are denoted

  517. by the first bit of their trailing significand field being 1.

  518. </p>

  519. <p>The <samp>-mnan=2008</samp> option selects the IEEE 754-2008 encoding.  In

  520. this case qNaNs are denoted by the first bit of their trailing

  521. significand field being 1, whereas sNaNs are denoted by the first bit of

  522. their trailing significand field being 0.

  523. </p>

  524. <p>The default is <samp>-mnan=legacy</samp> unless GCC has been configured with

  525. <samp>--with-nan=2008</samp>.

  526. </p>

  527. </dd>

  528. <dt><code>-mllsc</code></dt>

  529. <dt><code>-mno-llsc</code></dt>

  530. <dd><a name="index-mllsc"></a>

  531. <a name="index-mno_002dllsc"></a>

  532. <p>Use (do not use) &lsquo;<samp>ll</samp>&rsquo;, &lsquo;<samp>sc</samp>&rsquo;, and &lsquo;<samp>sync</samp>&rsquo; instructions to

  533. implement atomic memory built-in functions.  When neither option is

  534. specified, GCC uses the instructions if the target architecture

  535. supports them.

  536. </p>

  537. <p><samp>-mllsc</samp> is useful if the runtime environment can emulate the

  538. instructions and <samp>-mno-llsc</samp> can be useful when compiling for

  539. nonstandard ISAs.  You can make either option the default by

  540. configuring GCC with <samp>--with-llsc</samp> and <samp>--without-llsc</samp>

  541. respectively.  <samp>--with-llsc</samp> is the default for some

  542. configurations; see the installation documentation for details.

  543. </p>

  544. </dd>

  545. <dt><code>-mdsp</code></dt>

  546. <dt><code>-mno-dsp</code></dt>

  547. <dd><a name="index-mdsp-1"></a>

  548. <a name="index-mno_002ddsp"></a>

  549. <p>Use (do not use) revision 1 of the MIPS DSP ASE.

  550. See <a href="MIPS-DSP-Built_002din-Functions.html#MIPS-DSP-Built_002din-Functions">MIPS DSP Built-in Functions</a>.  This option defines the

  551. preprocessor macro <code>__mips_dsp</code>.  It also defines

  552. <code>__mips_dsp_rev</code> to 1.

  553. </p>

  554. </dd>

  555. <dt><code>-mdspr2</code></dt>

  556. <dt><code>-mno-dspr2</code></dt>

  557. <dd><a name="index-mdspr2"></a>

  558. <a name="index-mno_002ddspr2"></a>

  559. <p>Use (do not use) revision 2 of the MIPS DSP ASE.

  560. See <a href="MIPS-DSP-Built_002din-Functions.html#MIPS-DSP-Built_002din-Functions">MIPS DSP Built-in Functions</a>.  This option defines the

  561. preprocessor macros <code>__mips_dsp</code> and <code>__mips_dspr2</code>.

  562. It also defines <code>__mips_dsp_rev</code> to 2.

  563. </p>

  564. </dd>

  565. <dt><code>-msmartmips</code></dt>

  566. <dt><code>-mno-smartmips</code></dt>

  567. <dd><a name="index-msmartmips"></a>

  568. <a name="index-mno_002dsmartmips"></a>

  569. <p>Use (do not use) the MIPS SmartMIPS ASE.

  570. </p>

  571. </dd>

  572. <dt><code>-mpaired-single</code></dt>

  573. <dt><code>-mno-paired-single</code></dt>

  574. <dd><a name="index-mpaired_002dsingle"></a>

  575. <a name="index-mno_002dpaired_002dsingle"></a>

  576. <p>Use (do not use) paired-single floating-point instructions.

  577. See <a href="MIPS-Paired_002dSingle-Support.html#MIPS-Paired_002dSingle-Support">MIPS Paired-Single Support</a>.  This option requires

  578. hardware floating-point support to be enabled.

  579. </p>

  580. </dd>

  581. <dt><code>-mdmx</code></dt>

  582. <dt><code>-mno-mdmx</code></dt>

  583. <dd><a name="index-mdmx"></a>

  584. <a name="index-mno_002dmdmx"></a>

  585. <p>Use (do not use) MIPS Digital Media Extension instructions.

  586. This option can only be used when generating 64-bit code and requires

  587. hardware floating-point support to be enabled.

  588. </p>

  589. </dd>

  590. <dt><code>-mips3d</code></dt>

  591. <dt><code>-mno-mips3d</code></dt>

  592. <dd><a name="index-mips3d"></a>

  593. <a name="index-mno_002dmips3d"></a>

  594. <p>Use (do not use) the MIPS-3D ASE.  See <a href="MIPS_002d3D-Built_002din-Functions.html#MIPS_002d3D-Built_002din-Functions">MIPS-3D Built-in Functions</a>.

  595. The option <samp>-mips3d</samp> implies <samp>-mpaired-single</samp>.

  596. </p>

  597. </dd>

  598. <dt><code>-mmicromips</code></dt>

  599. <dt><code>-mno-micromips</code></dt>

  600. <dd><a name="index-mmicromips"></a>

  601. <a name="index-mno_002dmmicromips"></a>

  602. <p>Generate (do not generate) microMIPS code.

  603. </p>

  604. <p>MicroMIPS code generation can also be controlled on a per-function basis

  605. by means of <code>micromips</code> and <code>nomicromips</code> attributes.

  606. See <a href="Function-Attributes.html#Function-Attributes">Function Attributes</a>, for more information.

  607. </p>

  608. </dd>

  609. <dt><code>-mmt</code></dt>

  610. <dt><code>-mno-mt</code></dt>

  611. <dd><a name="index-mmt"></a>

  612. <a name="index-mno_002dmt"></a>

  613. <p>Use (do not use) MT Multithreading instructions.

  614. </p>

  615. </dd>

  616. <dt><code>-mmcu</code></dt>

  617. <dt><code>-mno-mcu</code></dt>

  618. <dd><a name="index-mmcu-1"></a>

  619. <a name="index-mno_002dmcu"></a>

  620. <p>Use (do not use) the MIPS MCU ASE instructions.

  621. </p>

  622. </dd>

  623. <dt><code>-meva</code></dt>

  624. <dt><code>-mno-eva</code></dt>

  625. <dd><a name="index-meva"></a>

  626. <a name="index-mno_002deva"></a>

  627. <p>Use (do not use) the MIPS Enhanced Virtual Addressing instructions.

  628. </p>

  629. </dd>

  630. <dt><code>-mvirt</code></dt>

  631. <dt><code>-mno-virt</code></dt>

  632. <dd><a name="index-mvirt"></a>

  633. <a name="index-mno_002dvirt"></a>

  634. <p>Use (do not use) the MIPS Virtualization (VZ) instructions.

  635. </p>

  636. </dd>

  637. <dt><code>-mxpa</code></dt>

  638. <dt><code>-mno-xpa</code></dt>

  639. <dd><a name="index-mxpa"></a>

  640. <a name="index-mno_002dxpa"></a>

  641. <p>Use (do not use) the MIPS eXtended Physical Address (XPA) instructions.

  642. </p>

  643. </dd>

  644. <dt><code>-mcrc</code></dt>

  645. <dt><code>-mno-crc</code></dt>

  646. <dd><a name="index-mcrc"></a>

  647. <a name="index-mno_002dcrc"></a>

  648. <p>Use (do not use) the MIPS Cyclic Redundancy Check (CRC) instructions.

  649. </p>

  650. </dd>

  651. <dt><code>-mginv</code></dt>

  652. <dt><code>-mno-ginv</code></dt>

  653. <dd><a name="index-mginv"></a>

  654. <a name="index-mno_002dginv"></a>

  655. <p>Use (do not use) the MIPS Global INValidate (GINV) instructions.

  656. </p>

  657. </dd>

  658. <dt><code>-mloongson-mmi</code></dt>

  659. <dt><code>-mno-loongson-mmi</code></dt>

  660. <dd><a name="index-mloongson_002dmmi"></a>

  661. <a name="index-mno_002dloongson_002dmmi"></a>

  662. <p>Use (do not use) the MIPS Loongson MultiMedia extensions Instructions (MMI).

  663. </p>

  664. </dd>

  665. <dt><code>-mloongson-ext</code></dt>

  666. <dt><code>-mno-loongson-ext</code></dt>

  667. <dd><a name="index-mloongson_002dext"></a>

  668. <a name="index-mno_002dloongson_002dext"></a>

  669. <p>Use (do not use) the MIPS Loongson EXTensions (EXT) instructions.

  670. </p>

  671. </dd>

  672. <dt><code>-mloongson-ext2</code></dt>

  673. <dt><code>-mno-loongson-ext2</code></dt>

  674. <dd><a name="index-mloongson_002dext2"></a>

  675. <a name="index-mno_002dloongson_002dext2"></a>

  676. <p>Use (do not use) the MIPS Loongson EXTensions r2 (EXT2) instructions.

  677. </p>

  678. </dd>

  679. <dt><code>-mlong64</code></dt>

  680. <dd><a name="index-mlong64"></a>

  681. <p>Force <code>long</code> types to be 64 bits wide.  See <samp>-mlong32</samp> for

  682. an explanation of the default and the way that the pointer size is

  683. determined.

  684. </p>

  685. </dd>

  686. <dt><code>-mlong32</code></dt>

  687. <dd><a name="index-mlong32"></a>

  688. <p>Force <code>long</code>, <code>int</code>, and pointer types to be 32 bits wide.

  689. </p>

  690. <p>The default size of <code>int</code>s, <code>long</code>s and pointers depends on

  691. the ABI.  All the supported ABIs use 32-bit <code>int</code>s.  The n64 ABI

  692. uses 64-bit <code>long</code>s, as does the 64-bit EABI; the others use

  693. 32-bit <code>long</code>s.  Pointers are the same size as <code>long</code>s,

  694. or the same size as integer registers, whichever is smaller.

  695. </p>

  696. </dd>

  697. <dt><code>-msym32</code></dt>

  698. <dt><code>-mno-sym32</code></dt>

  699. <dd><a name="index-msym32"></a>

  700. <a name="index-mno_002dsym32"></a>

  701. <p>Assume (do not assume) that all symbols have 32-bit values, regardless

  702. of the selected ABI.  This option is useful in combination with

  703. <samp>-mabi=64</samp> and <samp>-mno-abicalls</samp> because it allows GCC

  704. to generate shorter and faster references to symbolic addresses.

  705. </p>

  706. </dd>

  707. <dt><code>-G <var>num</var></code></dt>

  708. <dd><a name="index-G-2"></a>

  709. <p>Put definitions of externally-visible data in a small data section

  710. if that data is no bigger than <var>num</var> bytes.  GCC can then generate

  711. more efficient accesses to the data; see <samp>-mgpopt</samp> for details.

  712. </p>

  713. <p>The default <samp>-G</samp> option depends on the configuration.

  714. </p>

  715. </dd>

  716. <dt><code>-mlocal-sdata</code></dt>

  717. <dt><code>-mno-local-sdata</code></dt>

  718. <dd><a name="index-mlocal_002dsdata"></a>

  719. <a name="index-mno_002dlocal_002dsdata"></a>

  720. <p>Extend (do not extend) the <samp>-G</samp> behavior to local data too,

  721. such as to static variables in C.  <samp>-mlocal-sdata</samp> is the

  722. default for all configurations.

  723. </p>

  724. <p>If the linker complains that an application is using too much small data,

  725. you might want to try rebuilding the less performance-critical parts with

  726. <samp>-mno-local-sdata</samp>.  You might also want to build large

  727. libraries with <samp>-mno-local-sdata</samp>, so that the libraries leave

  728. more room for the main program.

  729. </p>

  730. </dd>

  731. <dt><code>-mextern-sdata</code></dt>

  732. <dt><code>-mno-extern-sdata</code></dt>

  733. <dd><a name="index-mextern_002dsdata"></a>

  734. <a name="index-mno_002dextern_002dsdata"></a>

  735. <p>Assume (do not assume) that externally-defined data is in

  736. a small data section if the size of that data is within the <samp>-G</samp> limit.

  737. <samp>-mextern-sdata</samp> is the default for all configurations.

  738. </p>

  739. <p>If you compile a module <var>Mod</var> with <samp>-mextern-sdata</samp> <samp>-G

  740. <var>num</var></samp> <samp>-mgpopt</samp>, and <var>Mod</var> references a variable <var>Var</var>

  741. that is no bigger than <var>num</var> bytes, you must make sure that <var>Var</var>

  742. is placed in a small data section.  If <var>Var</var> is defined by another

  743. module, you must either compile that module with a high-enough

  744. <samp>-G</samp> setting or attach a <code>section</code> attribute to <var>Var</var>&rsquo;s

  745. definition.  If <var>Var</var> is common, you must link the application

  746. with a high-enough <samp>-G</samp> setting.

  747. </p>

  748. <p>The easiest way of satisfying these restrictions is to compile

  749. and link every module with the same <samp>-G</samp> option.  However,

  750. you may wish to build a library that supports several different

  751. small data limits.  You can do this by compiling the library with

  752. the highest supported <samp>-G</samp> setting and additionally using

  753. <samp>-mno-extern-sdata</samp> to stop the library from making assumptions

  754. about externally-defined data.

  755. </p>

  756. </dd>

  757. <dt><code>-mgpopt</code></dt>

  758. <dt><code>-mno-gpopt</code></dt>

  759. <dd><a name="index-mgpopt"></a>

  760. <a name="index-mno_002dgpopt"></a>

  761. <p>Use (do not use) GP-relative accesses for symbols that are known to be

  762. in a small data section; see <samp>-G</samp>, <samp>-mlocal-sdata</samp> and

  763. <samp>-mextern-sdata</samp>.  <samp>-mgpopt</samp> is the default for all

  764. configurations.

  765. </p>

  766. <p><samp>-mno-gpopt</samp> is useful for cases where the <code>$gp</code> register

  767. might not hold the value of <code>_gp</code>.  For example, if the code is

  768. part of a library that might be used in a boot monitor, programs that

  769. call boot monitor routines pass an unknown value in <code>$gp</code>.

  770. (In such situations, the boot monitor itself is usually compiled

  771. with <samp>-G0</samp>.)

  772. </p>

  773. <p><samp>-mno-gpopt</samp> implies <samp>-mno-local-sdata</samp> and

  774. <samp>-mno-extern-sdata</samp>.

  775. </p>

  776. </dd>

  777. <dt><code>-membedded-data</code></dt>

  778. <dt><code>-mno-embedded-data</code></dt>

  779. <dd><a name="index-membedded_002ddata"></a>

  780. <a name="index-mno_002dembedded_002ddata"></a>

  781. <p>Allocate variables to the read-only data section first if possible, then

  782. next in the small data section if possible, otherwise in data.  This gives

  783. slightly slower code than the default, but reduces the amount of RAM required

  784. when executing, and thus may be preferred for some embedded systems.

  785. </p>

  786. </dd>

  787. <dt><code>-muninit-const-in-rodata</code></dt>

  788. <dt><code>-mno-uninit-const-in-rodata</code></dt>

  789. <dd><a name="index-muninit_002dconst_002din_002drodata"></a>

  790. <a name="index-mno_002duninit_002dconst_002din_002drodata"></a>

  791. <p>Put uninitialized <code>const</code> variables in the read-only data section.

  792. This option is only meaningful in conjunction with <samp>-membedded-data</samp>.

  793. </p>

  794. </dd>

  795. <dt><code>-mcode-readable=<var>setting</var></code></dt>

  796. <dd><a name="index-mcode_002dreadable"></a>

  797. <p>Specify whether GCC may generate code that reads from executable sections.

  798. There are three possible settings:

  799. </p>

  800. <dl compact="compact">

  801. <dt><code>-mcode-readable=yes</code></dt>

  802. <dd><p>Instructions may freely access executable sections.  This is the

  803. default setting.

  804. </p>

  805. </dd>

  806. <dt><code>-mcode-readable=pcrel</code></dt>

  807. <dd><p>MIPS16 PC-relative load instructions can access executable sections,

  808. but other instructions must not do so.  This option is useful on 4KSc

  809. and 4KSd processors when the code TLBs have the Read Inhibit bit set.

  810. It is also useful on processors that can be configured to have a dual

  811. instruction/data SRAM interface and that, like the M4K, automatically

  812. redirect PC-relative loads to the instruction RAM.

  813. </p>

  814. </dd>

  815. <dt><code>-mcode-readable=no</code></dt>

  816. <dd><p>Instructions must not access executable sections.  This option can be

  817. useful on targets that are configured to have a dual instruction/data

  818. SRAM interface but that (unlike the M4K) do not automatically redirect

  819. PC-relative loads to the instruction RAM.

  820. </p></dd>

  821. </dl>

  822. 

  823. </dd>

  824. <dt><code>-msplit-addresses</code></dt>

  825. <dt><code>-mno-split-addresses</code></dt>

  826. <dd><a name="index-msplit_002daddresses"></a>

  827. <a name="index-mno_002dsplit_002daddresses"></a>

  828. <p>Enable (disable) use of the <code>%hi()</code> and <code>%lo()</code> assembler

  829. relocation operators.  This option has been superseded by

  830. <samp>-mexplicit-relocs</samp> but is retained for backwards compatibility.

  831. </p>

  832. </dd>

  833. <dt><code>-mexplicit-relocs</code></dt>

  834. <dt><code>-mno-explicit-relocs</code></dt>

  835. <dd><a name="index-mexplicit_002drelocs-1"></a>

  836. <a name="index-mno_002dexplicit_002drelocs-1"></a>

  837. <p>Use (do not use) assembler relocation operators when dealing with symbolic

  838. addresses.  The alternative, selected by <samp>-mno-explicit-relocs</samp>,

  839. is to use assembler macros instead.

  840. </p>

  841. <p><samp>-mexplicit-relocs</samp> is the default if GCC was configured

  842. to use an assembler that supports relocation operators.

  843. </p>

  844. </dd>

  845. <dt><code>-mcheck-zero-division</code></dt>

  846. <dt><code>-mno-check-zero-division</code></dt>

  847. <dd><a name="index-mcheck_002dzero_002ddivision"></a>

  848. <a name="index-mno_002dcheck_002dzero_002ddivision"></a>

  849. <p>Trap (do not trap) on integer division by zero.

  850. </p>

  851. <p>The default is <samp>-mcheck-zero-division</samp>.

  852. </p>

  853. </dd>

  854. <dt><code>-mdivide-traps</code></dt>

  855. <dt><code>-mdivide-breaks</code></dt>

  856. <dd><a name="index-mdivide_002dtraps"></a>

  857. <a name="index-mdivide_002dbreaks"></a>

  858. <p>MIPS systems check for division by zero by generating either a

  859. conditional trap or a break instruction.  Using traps results in

  860. smaller code, but is only supported on MIPS II and later.  Also, some

  861. versions of the Linux kernel have a bug that prevents trap from

  862. generating the proper signal (<code>SIGFPE</code>).  Use <samp>-mdivide-traps</samp> to

  863. allow conditional traps on architectures that support them and

  864. <samp>-mdivide-breaks</samp> to force the use of breaks.

  865. </p>

  866. <p>The default is usually <samp>-mdivide-traps</samp>, but this can be

  867. overridden at configure time using <samp>--with-divide=breaks</samp>.

  868. Divide-by-zero checks can be completely disabled using

  869. <samp>-mno-check-zero-division</samp>.

  870. </p>

  871. </dd>

  872. <dt><code>-mload-store-pairs</code></dt>

  873. <dt><code>-mno-load-store-pairs</code></dt>

  874. <dd><a name="index-mload_002dstore_002dpairs"></a>

  875. <a name="index-mno_002dload_002dstore_002dpairs"></a>

  876. <p>Enable (disable) an optimization that pairs consecutive load or store

  877. instructions to enable load/store bonding.  This option is enabled by

  878. default but only takes effect when the selected architecture is known

  879. to support bonding.

  880. </p>

  881. </dd>

  882. <dt><code>-mmemcpy</code></dt>

  883. <dt><code>-mno-memcpy</code></dt>

  884. <dd><a name="index-mmemcpy-1"></a>

  885. <a name="index-mno_002dmemcpy"></a>

  886. <p>Force (do not force) the use of <code>memcpy</code> for non-trivial block

  887. moves.  The default is <samp>-mno-memcpy</samp>, which allows GCC to inline

  888. most constant-sized copies.

  889. </p>

  890. </dd>

  891. <dt><code>-mlong-calls</code></dt>

  892. <dt><code>-mno-long-calls</code></dt>

  893. <dd><a name="index-mlong_002dcalls-6"></a>

  894. <a name="index-mno_002dlong_002dcalls-3"></a>

  895. <p>Disable (do not disable) use of the <code>jal</code> instruction.  Calling

  896. functions using <code>jal</code> is more efficient but requires the caller

  897. and callee to be in the same 256 megabyte segment.

  898. </p>

  899. <p>This option has no effect on abicalls code.  The default is

  900. <samp>-mno-long-calls</samp>.

  901. </p>

  902. </dd>

  903. <dt><code>-mmad</code></dt>

  904. <dt><code>-mno-mad</code></dt>

  905. <dd><a name="index-mmad"></a>

  906. <a name="index-mno_002dmad"></a>

  907. <p>Enable (disable) use of the <code>mad</code>, <code>madu</code> and <code>mul</code>

  908. instructions, as provided by the R4650 ISA.

  909. </p>

  910. </dd>

  911. <dt><code>-mimadd</code></dt>

  912. <dt><code>-mno-imadd</code></dt>

  913. <dd><a name="index-mimadd"></a>

  914. <a name="index-mno_002dimadd"></a>

  915. <p>Enable (disable) use of the <code>madd</code> and <code>msub</code> integer

  916. instructions.  The default is <samp>-mimadd</samp> on architectures

  917. that support <code>madd</code> and <code>msub</code> except for the 74k 

  918. architecture where it was found to generate slower code.

  919. </p>

  920. </dd>

  921. <dt><code>-mfused-madd</code></dt>

  922. <dt><code>-mno-fused-madd</code></dt>

  923. <dd><a name="index-mfused_002dmadd-1"></a>

  924. <a name="index-mno_002dfused_002dmadd-1"></a>

  925. <p>Enable (disable) use of the floating-point multiply-accumulate

  926. instructions, when they are available.  The default is

  927. <samp>-mfused-madd</samp>.

  928. </p>

  929. <p>On the R8000 CPU when multiply-accumulate instructions are used,

  930. the intermediate product is calculated to infinite precision

  931. and is not subject to the FCSR Flush to Zero bit.  This may be

  932. undesirable in some circumstances.  On other processors the result

  933. is numerically identical to the equivalent computation using

  934. separate multiply, add, subtract and negate instructions.

  935. </p>

  936. </dd>

  937. <dt><code>-nocpp</code></dt>

  938. <dd><a name="index-nocpp"></a>

  939. <p>Tell the MIPS assembler to not run its preprocessor over user

  940. assembler files (with a &lsquo;<samp>.s</samp>&rsquo; suffix) when assembling them.

  941. </p>

  942. </dd>

  943. <dt><code>-mfix-24k</code></dt>

  944. <dt><code>-mno-fix-24k</code></dt>

  945. <dd><a name="index-mfix_002d24k"></a>

  946. <a name="index-mno_002dfix_002d24k"></a>

  947. <p>Work around the 24K E48 (lost data on stores during refill) errata.

  948. The workarounds are implemented by the assembler rather than by GCC.

  949. </p>

  950. </dd>

  951. <dt><code>-mfix-r4000</code></dt>

  952. <dt><code>-mno-fix-r4000</code></dt>

  953. <dd><a name="index-mfix_002dr4000"></a>

  954. <a name="index-mno_002dfix_002dr4000"></a>

  955. <p>Work around certain R4000 CPU errata:

  956. </p><ul class="no-bullet">

  957. <li>- A double-word or a variable shift may give an incorrect result if executed

  958. immediately after starting an integer division.

  959. </li><li>- A double-word or a variable shift may give an incorrect result if executed

  960. while an integer multiplication is in progress.

  961. </li><li>- An integer division may give an incorrect result if started in a delay slot

  962. of a taken branch or a jump.

  963. </li></ul>

  964. 

  965. </dd>

  966. <dt><code>-mfix-r4400</code></dt>

  967. <dt><code>-mno-fix-r4400</code></dt>

  968. <dd><a name="index-mfix_002dr4400"></a>

  969. <a name="index-mno_002dfix_002dr4400"></a>

  970. <p>Work around certain R4400 CPU errata:

  971. </p><ul class="no-bullet">

  972. <li>- A double-word or a variable shift may give an incorrect result if executed

  973. immediately after starting an integer division.

  974. </li></ul>

  975. 

  976. </dd>

  977. <dt><code>-mfix-r10000</code></dt>

  978. <dt><code>-mno-fix-r10000</code></dt>

  979. <dd><a name="index-mfix_002dr10000"></a>

  980. <a name="index-mno_002dfix_002dr10000"></a>

  981. <p>Work around certain R10000 errata:

  982. </p><ul class="no-bullet">

  983. <li>- <code>ll</code>/<code>sc</code> sequences may not behave atomically on revisions

  984. prior to 3.0.  They may deadlock on revisions 2.6 and earlier.

  985. </li></ul>

  986. 

  987. <p>This option can only be used if the target architecture supports

  988. branch-likely instructions.  <samp>-mfix-r10000</samp> is the default when

  989. <samp>-march=r10000</samp> is used; <samp>-mno-fix-r10000</samp> is the default

  990. otherwise.

  991. </p>

  992. </dd>

  993. <dt><code>-mfix-r5900</code></dt>

  994. <dt><code>-mno-fix-r5900</code></dt>

  995. <dd><a name="index-mfix_002dr5900"></a>

  996. <p>Do not attempt to schedule the preceding instruction into the delay slot

  997. of a branch instruction placed at the end of a short loop of six

  998. instructions or fewer and always schedule a <code>nop</code> instruction there

  999. instead.  The short loop bug under certain conditions causes loops to

  1000. execute only once or twice, due to a hardware bug in the R5900 chip.  The

  1001. workaround is implemented by the assembler rather than by GCC.

  1002. </p>

  1003. </dd>

  1004. <dt><code>-mfix-rm7000</code></dt>

  1005. <dt><code>-mno-fix-rm7000</code></dt>

  1006. <dd><a name="index-mfix_002drm7000"></a>

  1007. <p>Work around the RM7000 <code>dmult</code>/<code>dmultu</code> errata.  The

  1008. workarounds are implemented by the assembler rather than by GCC.

  1009. </p>

  1010. </dd>

  1011. <dt><code>-mfix-vr4120</code></dt>

  1012. <dt><code>-mno-fix-vr4120</code></dt>

  1013. <dd><a name="index-mfix_002dvr4120"></a>

  1014. <p>Work around certain VR4120 errata:

  1015. </p><ul class="no-bullet">

  1016. <li>- <code>dmultu</code> does not always produce the correct result.

  1017. </li><li>- <code>div</code> and <code>ddiv</code> do not always produce the correct result if one

  1018. of the operands is negative.

  1019. </li></ul>

  1020. <p>The workarounds for the division errata rely on special functions in

  1021. <samp>libgcc.a</samp>.  At present, these functions are only provided by

  1022. the <code>mips64vr*-elf</code> configurations.

  1023. </p>

  1024. <p>Other VR4120 errata require a NOP to be inserted between certain pairs of

  1025. instructions.  These errata are handled by the assembler, not by GCC itself.

  1026. </p>

  1027. </dd>

  1028. <dt><code>-mfix-vr4130</code></dt>

  1029. <dd><a name="index-mfix_002dvr4130"></a>

  1030. <p>Work around the VR4130 <code>mflo</code>/<code>mfhi</code> errata.  The

  1031. workarounds are implemented by the assembler rather than by GCC,

  1032. although GCC avoids using <code>mflo</code> and <code>mfhi</code> if the

  1033. VR4130 <code>macc</code>, <code>macchi</code>, <code>dmacc</code> and <code>dmacchi</code>

  1034. instructions are available instead.

  1035. </p>

  1036. </dd>

  1037. <dt><code>-mfix-sb1</code></dt>

  1038. <dt><code>-mno-fix-sb1</code></dt>

  1039. <dd><a name="index-mfix_002dsb1"></a>

  1040. <p>Work around certain SB-1 CPU core errata.

  1041. (This flag currently works around the SB-1 revision 2

  1042. &ldquo;F1&rdquo; and &ldquo;F2&rdquo; floating-point errata.)

  1043. </p>

  1044. </dd>

  1045. <dt><code>-mr10k-cache-barrier=<var>setting</var></code></dt>

  1046. <dd><a name="index-mr10k_002dcache_002dbarrier"></a>

  1047. <p>Specify whether GCC should insert cache barriers to avoid the

  1048. side effects of speculation on R10K processors.

  1049. </p>

  1050. <p>In common with many processors, the R10K tries to predict the outcome

  1051. of a conditional branch and speculatively executes instructions from

  1052. the &ldquo;taken&rdquo; branch.  It later aborts these instructions if the

  1053. predicted outcome is wrong.  However, on the R10K, even aborted

  1054. instructions can have side effects.

  1055. </p>

  1056. <p>This problem only affects kernel stores and, depending on the system,

  1057. kernel loads.  As an example, a speculatively-executed store may load

  1058. the target memory into cache and mark the cache line as dirty, even if

  1059. the store itself is later aborted.  If a DMA operation writes to the

  1060. same area of memory before the &ldquo;dirty&rdquo; line is flushed, the cached

  1061. data overwrites the DMA-ed data.  See the R10K processor manual

  1062. for a full description, including other potential problems.

  1063. </p>

  1064. <p>One workaround is to insert cache barrier instructions before every memory

  1065. access that might be speculatively executed and that might have side

  1066. effects even if aborted.  <samp>-mr10k-cache-barrier=<var>setting</var></samp>

  1067. controls GCC&rsquo;s implementation of this workaround.  It assumes that

  1068. aborted accesses to any byte in the following regions does not have

  1069. side effects:

  1070. </p>

  1071. <ol>

  1072. <li> the memory occupied by the current function&rsquo;s stack frame;

  1073. 

  1074. </li><li> the memory occupied by an incoming stack argument;

  1075. 

  1076. </li><li> the memory occupied by an object with a link-time-constant address.

  1077. </li></ol>

  1078. 

  1079. <p>It is the kernel&rsquo;s responsibility to ensure that speculative

  1080. accesses to these regions are indeed safe.

  1081. </p>

  1082. <p>If the input program contains a function declaration such as:

  1083. </p>

  1084. <div class="smallexample">

  1085. <pre class="smallexample">void foo (void);

  1086. </pre></div>

  1087. 

  1088. <p>then the implementation of <code>foo</code> must allow <code>j foo</code> and

  1089. <code>jal foo</code> to be executed speculatively.  GCC honors this

  1090. restriction for functions it compiles itself.  It expects non-GCC

  1091. functions (such as hand-written assembly code) to do the same.

  1092. </p>

  1093. <p>The option has three forms:

  1094. </p>

  1095. <dl compact="compact">

  1096. <dt><code>-mr10k-cache-barrier=load-store</code></dt>

  1097. <dd><p>Insert a cache barrier before a load or store that might be

  1098. speculatively executed and that might have side effects even

  1099. if aborted.

  1100. </p>

  1101. </dd>

  1102. <dt><code>-mr10k-cache-barrier=store</code></dt>

  1103. <dd><p>Insert a cache barrier before a store that might be speculatively

  1104. executed and that might have side effects even if aborted.

  1105. </p>

  1106. </dd>

  1107. <dt><code>-mr10k-cache-barrier=none</code></dt>

  1108. <dd><p>Disable the insertion of cache barriers.  This is the default setting.

  1109. </p></dd>

  1110. </dl>

  1111. 

  1112. </dd>

  1113. <dt><code>-mflush-func=<var>func</var></code></dt>

  1114. <dt><code>-mno-flush-func</code></dt>

  1115. <dd><a name="index-mflush_002dfunc"></a>

  1116. <p>Specifies the function to call to flush the I and D caches, or to not

  1117. call any such function.  If called, the function must take the same

  1118. arguments as the common <code>_flush_func</code>, that is, the address of the

  1119. memory range for which the cache is being flushed, the size of the

  1120. memory range, and the number 3 (to flush both caches).  The default

  1121. depends on the target GCC was configured for, but commonly is either

  1122. <code>_flush_func</code> or <code>__cpu_flush</code>.

  1123. </p>

  1124. </dd>

  1125. <dt><code>mbranch-cost=<var>num</var></code></dt>

  1126. <dd><a name="index-mbranch_002dcost-2"></a>

  1127. <p>Set the cost of branches to roughly <var>num</var> &ldquo;simple&rdquo; instructions.

  1128. This cost is only a heuristic and is not guaranteed to produce

  1129. consistent results across releases.  A zero cost redundantly selects

  1130. the default, which is based on the <samp>-mtune</samp> setting.

  1131. </p>

  1132. </dd>

  1133. <dt><code>-mbranch-likely</code></dt>

  1134. <dt><code>-mno-branch-likely</code></dt>

  1135. <dd><a name="index-mbranch_002dlikely"></a>

  1136. <a name="index-mno_002dbranch_002dlikely"></a>

  1137. <p>Enable or disable use of Branch Likely instructions, regardless of the

  1138. default for the selected architecture.  By default, Branch Likely

  1139. instructions may be generated if they are supported by the selected

  1140. architecture.  An exception is for the MIPS32 and MIPS64 architectures

  1141. and processors that implement those architectures; for those, Branch

  1142. Likely instructions are not be generated by default because the MIPS32

  1143. and MIPS64 architectures specifically deprecate their use.

  1144. </p>

  1145. </dd>

  1146. <dt><code>-mcompact-branches=never</code></dt>

  1147. <dt><code>-mcompact-branches=optimal</code></dt>

  1148. <dt><code>-mcompact-branches=always</code></dt>

  1149. <dd><a name="index-mcompact_002dbranches_003dnever"></a>

  1150. <a name="index-mcompact_002dbranches_003doptimal"></a>

  1151. <a name="index-mcompact_002dbranches_003dalways"></a>

  1152. <p>These options control which form of branches will be generated.  The

  1153. default is <samp>-mcompact-branches=optimal</samp>.

  1154. </p>

  1155. <p>The <samp>-mcompact-branches=never</samp> option ensures that compact branch

  1156. instructions will never be generated.

  1157. </p>

  1158. <p>The <samp>-mcompact-branches=always</samp> option ensures that a compact

  1159. branch instruction will be generated if available.  If a compact branch

  1160. instruction is not available, a delay slot form of the branch will be

  1161. used instead.

  1162. </p>

  1163. <p>This option is supported from MIPS Release 6 onwards.

  1164. </p>

  1165. <p>The <samp>-mcompact-branches=optimal</samp> option will cause a delay slot

  1166. branch to be used if one is available in the current ISA and the delay

  1167. slot is successfully filled.  If the delay slot is not filled, a compact

  1168. branch will be chosen if one is available.

  1169. </p>

  1170. </dd>

  1171. <dt><code>-mfp-exceptions</code></dt>

  1172. <dt><code>-mno-fp-exceptions</code></dt>

  1173. <dd><a name="index-mfp_002dexceptions"></a>

  1174. <p>Specifies whether FP exceptions are enabled.  This affects how

  1175. FP instructions are scheduled for some processors.

  1176. The default is that FP exceptions are

  1177. enabled.

  1178. </p>

  1179. <p>For instance, on the SB-1, if FP exceptions are disabled, and we are emitting

  1180. 64-bit code, then we can use both FP pipes.  Otherwise, we can only use one

  1181. FP pipe.

  1182. </p>

  1183. </dd>

  1184. <dt><code>-mvr4130-align</code></dt>

  1185. <dt><code>-mno-vr4130-align</code></dt>

  1186. <dd><a name="index-mvr4130_002dalign"></a>

  1187. <p>The VR4130 pipeline is two-way superscalar, but can only issue two

  1188. instructions together if the first one is 8-byte aligned.  When this

  1189. option is enabled, GCC aligns pairs of instructions that it

  1190. thinks should execute in parallel.

  1191. </p>

  1192. <p>This option only has an effect when optimizing for the VR4130.

  1193. It normally makes code faster, but at the expense of making it bigger.

  1194. It is enabled by default at optimization level <samp>-O3</samp>.

  1195. </p>

  1196. </dd>

  1197. <dt><code>-msynci</code></dt>

  1198. <dt><code>-mno-synci</code></dt>

  1199. <dd><a name="index-msynci"></a>

  1200. <p>Enable (disable) generation of <code>synci</code> instructions on

  1201. architectures that support it.  The <code>synci</code> instructions (if

  1202. enabled) are generated when <code>__builtin___clear_cache</code> is

  1203. compiled.

  1204. </p>

  1205. <p>This option defaults to <samp>-mno-synci</samp>, but the default can be

  1206. overridden by configuring GCC with <samp>--with-synci</samp>.

  1207. </p>

  1208. <p>When compiling code for single processor systems, it is generally safe

  1209. to use <code>synci</code>.  However, on many multi-core (SMP) systems, it

  1210. does not invalidate the instruction caches on all cores and may lead

  1211. to undefined behavior.

  1212. </p>

  1213. </dd>

  1214. <dt><code>-mrelax-pic-calls</code></dt>

  1215. <dt><code>-mno-relax-pic-calls</code></dt>

  1216. <dd><a name="index-mrelax_002dpic_002dcalls"></a>

  1217. <p>Try to turn PIC calls that are normally dispatched via register

  1218. <code>$25</code> into direct calls.  This is only possible if the linker can

  1219. resolve the destination at link time and if the destination is within

  1220. range for a direct call.

  1221. </p>

  1222. <p><samp>-mrelax-pic-calls</samp> is the default if GCC was configured to use

  1223. an assembler and a linker that support the <code>.reloc</code> assembly

  1224. directive and <samp>-mexplicit-relocs</samp> is in effect.  With

  1225. <samp>-mno-explicit-relocs</samp>, this optimization can be performed by the

  1226. assembler and the linker alone without help from the compiler.

  1227. </p>

  1228. </dd>

  1229. <dt><code>-mmcount-ra-address</code></dt>

  1230. <dt><code>-mno-mcount-ra-address</code></dt>

  1231. <dd><a name="index-mmcount_002dra_002daddress"></a>

  1232. <a name="index-mno_002dmcount_002dra_002daddress"></a>

  1233. <p>Emit (do not emit) code that allows <code>_mcount</code> to modify the

  1234. calling function&rsquo;s return address.  When enabled, this option extends

  1235. the usual <code>_mcount</code> interface with a new <var>ra-address</var>

  1236. parameter, which has type <code>intptr_t *</code> and is passed in register

  1237. <code>$12</code>.  <code>_mcount</code> can then modify the return address by

  1238. doing both of the following:

  1239. </p><ul>

  1240. <li> Returning the new address in register <code>$31</code>.

  1241. </li><li> Storing the new address in <code>*<var>ra-address</var></code>,

  1242. if <var>ra-address</var> is nonnull.

  1243. </li></ul>

  1244. 

  1245. <p>The default is <samp>-mno-mcount-ra-address</samp>.

  1246. </p>

  1247. </dd>

  1248. <dt><code>-mframe-header-opt</code></dt>

  1249. <dt><code>-mno-frame-header-opt</code></dt>

  1250. <dd><a name="index-mframe_002dheader_002dopt"></a>

  1251. <p>Enable (disable) frame header optimization in the o32 ABI.  When using the

  1252. o32 ABI, calling functions will allocate 16 bytes on the stack for the called

  1253. function to write out register arguments.  When enabled, this optimization

  1254. will suppress the allocation of the frame header if it can be determined that

  1255. it is unused.

  1256. </p>

  1257. <p>This optimization is off by default at all optimization levels.

  1258. </p>

  1259. </dd>

  1260. <dt><code>-mlxc1-sxc1</code></dt>

  1261. <dt><code>-mno-lxc1-sxc1</code></dt>

  1262. <dd><a name="index-mlxc1_002dsxc1"></a>

  1263. <p>When applicable, enable (disable) the generation of <code>lwxc1</code>,

  1264. <code>swxc1</code>, <code>ldxc1</code>, <code>sdxc1</code> instructions.  Enabled by default.

  1265. </p>

  1266. </dd>

  1267. <dt><code>-mmadd4</code></dt>

  1268. <dt><code>-mno-madd4</code></dt>

  1269. <dd><a name="index-mmadd4"></a>

  1270. <p>When applicable, enable (disable) the generation of 4-operand <code>madd.s</code>,

  1271. <code>madd.d</code> and related instructions.  Enabled by default.

  1272. </p>

  1273. </dd>

  1274. </dl>

  1275. 

  1276. <hr>

  1277. <div class="header">

  1278. <p>

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  1280. </div>

  1281. 

  1282. 

  1283. 

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