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toolchain-gcc-arm-embedded/share/doc/gcc-arm-none-eabi/html/gccint/MIPS-Coprocessors.html

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  25. <title>MIPS Coprocessors (GNU Compiler Collection (GCC) Internals)</title>

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  70. <a name="MIPS-Coprocessors"></a>

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  74. </div>

  75. <hr>

  76. <a name="Defining-coprocessor-specifics-for-MIPS-targets_002e"></a>

  77. <h3 class="section">18.26 Defining coprocessor specifics for MIPS targets.</h3>

  78. <a name="index-MIPS-coprocessor_002ddefinition-macros"></a>

  79. 

  80. <p>The MIPS specification allows MIPS implementations to have as many as 4

  81. coprocessors, each with as many as 32 private registers.  GCC supports

  82. accessing these registers and transferring values between the registers

  83. and memory using asm-ized variables.  For example:

  84. </p>

  85. <div class="smallexample">

  86. <pre class="smallexample">  register unsigned int cp0count asm (&quot;c0r1&quot;);

  87.   unsigned int d;

  88. 

  89.   d = cp0count + 3;

  90. </pre></div>

  91. 

  92. <p>(&ldquo;c0r1&rdquo; is the default name of register 1 in coprocessor 0; alternate

  93. names may be added as described below, or the default names may be

  94. overridden entirely in <code>SUBTARGET_CONDITIONAL_REGISTER_USAGE</code>.)

  95. </p>

  96. <p>Coprocessor registers are assumed to be epilogue-used; sets to them will

  97. be preserved even if it does not appear that the register is used again

  98. later in the function.

  99. </p>

  100. <p>Another note: according to the MIPS spec, coprocessor 1 (if present) is

  101. the FPU.  One accesses COP1 registers through standard mips

  102. floating-point support; they are not included in this mechanism.

  103. </p>

  104. 

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