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  35. <link href="Constraints.html#Constraints" rel="up" title="Constraints">

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  70. <a name="Machine-Constraints"></a>

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  72. <p>

  73. Next: <a href="Disable-Insn-Alternatives.html#Disable-Insn-Alternatives" accesskey="n" rel="next">Disable Insn Alternatives</a>, Previous: <a href="Modifiers.html#Modifiers" accesskey="p" rel="prev">Modifiers</a>, Up: <a href="Constraints.html#Constraints" accesskey="u" rel="up">Constraints</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>

  74. </div>

  75. <hr>

  76. <a name="Constraints-for-Particular-Machines"></a>

  77. <h4 class="subsection">17.8.5 Constraints for Particular Machines</h4>

  78. <a name="index-machine-specific-constraints"></a>

  79. <a name="index-constraints_002c-machine-specific"></a>

  80. 

  81. <p>Whenever possible, you should use the general-purpose constraint letters

  82. in <code>asm</code> arguments, since they will convey meaning more readily to

  83. people reading your code.  Failing that, use the constraint letters

  84. that usually have very similar meanings across architectures.  The most

  85. commonly used constraints are &lsquo;<samp>m</samp>&rsquo; and &lsquo;<samp>r</samp>&rsquo; (for memory and

  86. general-purpose registers respectively; see <a href="Simple-Constraints.html#Simple-Constraints">Simple Constraints</a>), and

  87. &lsquo;<samp>I</samp>&rsquo;, usually the letter indicating the most common

  88. immediate-constant format.

  89. </p>

  90. <p>Each architecture defines additional constraints.  These constraints

  91. are used by the compiler itself for instruction generation, as well as

  92. for <code>asm</code> statements; therefore, some of the constraints are not

  93. particularly useful for <code>asm</code>.  Here is a summary of some of the

  94. machine-dependent constraints available on some particular machines;

  95. it includes both constraints that are useful for <code>asm</code> and

  96. constraints that aren&rsquo;t.  The compiler source file mentioned in the

  97. table heading for each architecture is the definitive reference for

  98. the meanings of that architecture&rsquo;s constraints.

  99. </p>

  100. <dl compact="compact">

  101. <dt><em>AArch64 family&mdash;<samp>config/aarch64/constraints.md</samp></em></dt>

  102. <dd><dl compact="compact">

  103. <dt><code>k</code></dt>

  104. <dd><p>The stack pointer register (<code>SP</code>)

  105. </p>

  106. </dd>

  107. <dt><code>w</code></dt>

  108. <dd><p>Floating point register, Advanced SIMD vector register or SVE vector register

  109. </p>

  110. </dd>

  111. <dt><code>x</code></dt>

  112. <dd><p>Like <code>w</code>, but restricted to registers 0 to 15 inclusive.

  113. </p>

  114. </dd>

  115. <dt><code>y</code></dt>

  116. <dd><p>Like <code>w</code>, but restricted to registers 0 to 7 inclusive.

  117. </p>

  118. </dd>

  119. <dt><code>Upl</code></dt>

  120. <dd><p>One of the low eight SVE predicate registers (<code>P0</code> to <code>P7</code>)

  121. </p>

  122. </dd>

  123. <dt><code>Upa</code></dt>

  124. <dd><p>Any of the SVE predicate registers (<code>P0</code> to <code>P15</code>)

  125. </p>

  126. </dd>

  127. <dt><code>I</code></dt>

  128. <dd><p>Integer constant that is valid as an immediate operand in an <code>ADD</code>

  129. instruction

  130. </p>

  131. </dd>

  132. <dt><code>J</code></dt>

  133. <dd><p>Integer constant that is valid as an immediate operand in a <code>SUB</code>

  134. instruction (once negated)

  135. </p>

  136. </dd>

  137. <dt><code>K</code></dt>

  138. <dd><p>Integer constant that can be used with a 32-bit logical instruction

  139. </p>

  140. </dd>

  141. <dt><code>L</code></dt>

  142. <dd><p>Integer constant that can be used with a 64-bit logical instruction

  143. </p>

  144. </dd>

  145. <dt><code>M</code></dt>

  146. <dd><p>Integer constant that is valid as an immediate operand in a 32-bit <code>MOV</code>

  147. pseudo instruction. The <code>MOV</code> may be assembled to one of several different

  148. machine instructions depending on the value

  149. </p>

  150. </dd>

  151. <dt><code>N</code></dt>

  152. <dd><p>Integer constant that is valid as an immediate operand in a 64-bit <code>MOV</code>

  153. pseudo instruction

  154. </p>

  155. </dd>

  156. <dt><code>S</code></dt>

  157. <dd><p>An absolute symbolic address or a label reference

  158. </p>

  159. </dd>

  160. <dt><code>Y</code></dt>

  161. <dd><p>Floating point constant zero

  162. </p>

  163. </dd>

  164. <dt><code>Z</code></dt>

  165. <dd><p>Integer constant zero

  166. </p>

  167. </dd>

  168. <dt><code>Ush</code></dt>

  169. <dd><p>The high part (bits 12 and upwards) of the pc-relative address of a symbol

  170. within 4GB of the instruction

  171. </p>

  172. </dd>

  173. <dt><code>Q</code></dt>

  174. <dd><p>A memory address which uses a single base register with no offset

  175. </p>

  176. </dd>

  177. <dt><code>Ump</code></dt>

  178. <dd><p>A memory address suitable for a load/store pair instruction in SI, DI, SF and

  179. DF modes

  180. </p>

  181. </dd>

  182. </dl>

  183. 

  184. 

  185. </dd>

  186. <dt><em>AMD GCN &mdash;<samp>config/gcn/constraints.md</samp></em></dt>

  187. <dd><dl compact="compact">

  188. <dt><code>I</code></dt>

  189. <dd><p>Immediate integer in the range -16 to 64

  190. </p>

  191. </dd>

  192. <dt><code>J</code></dt>

  193. <dd><p>Immediate 16-bit signed integer

  194. </p>

  195. </dd>

  196. <dt><code>Kf</code></dt>

  197. <dd><p>Immediate constant -1

  198. </p>

  199. </dd>

  200. <dt><code>L</code></dt>

  201. <dd><p>Immediate 15-bit unsigned integer

  202. </p>

  203. </dd>

  204. <dt><code>A</code></dt>

  205. <dd><p>Immediate constant that can be inlined in an instruction encoding: integer

  206. -16..64, or float 0.0, +/-0.5, +/-1.0, +/-2.0,

  207. +/-4.0, 1.0/(2.0*PI)

  208. </p>

  209. </dd>

  210. <dt><code>B</code></dt>

  211. <dd><p>Immediate 32-bit signed integer that can be attached to an instruction encoding

  212. </p>

  213. </dd>

  214. <dt><code>C</code></dt>

  215. <dd><p>Immediate 32-bit integer in range -16..4294967295 (i.e. 32-bit unsigned

  216. integer or &lsquo;<samp>A</samp>&rsquo; constraint)

  217. </p>

  218. </dd>

  219. <dt><code>DA</code></dt>

  220. <dd><p>Immediate 64-bit constant that can be split into two &lsquo;<samp>A</samp>&rsquo; constants

  221. </p>

  222. </dd>

  223. <dt><code>DB</code></dt>

  224. <dd><p>Immediate 64-bit constant that can be split into two &lsquo;<samp>B</samp>&rsquo; constants

  225. </p>

  226. </dd>

  227. <dt><code>U</code></dt>

  228. <dd><p>Any <code>unspec</code>

  229. </p>

  230. </dd>

  231. <dt><code>Y</code></dt>

  232. <dd><p>Any <code>symbol_ref</code> or <code>label_ref</code>

  233. </p>

  234. </dd>

  235. <dt><code>v</code></dt>

  236. <dd><p>VGPR register

  237. </p>

  238. </dd>

  239. <dt><code>Sg</code></dt>

  240. <dd><p>SGPR register

  241. </p>

  242. </dd>

  243. <dt><code>SD</code></dt>

  244. <dd><p>SGPR registers valid for instruction destinations, including VCC, M0 and EXEC

  245. </p>

  246. </dd>

  247. <dt><code>SS</code></dt>

  248. <dd><p>SGPR registers valid for instruction sources, including VCC, M0, EXEC and SCC

  249. </p>

  250. </dd>

  251. <dt><code>Sm</code></dt>

  252. <dd><p>SGPR registers valid as a source for scalar memory instructions (excludes M0

  253. and EXEC)

  254. </p>

  255. </dd>

  256. <dt><code>Sv</code></dt>

  257. <dd><p>SGPR registers valid as a source or destination for vector instructions

  258. (excludes EXEC)

  259. </p>

  260. </dd>

  261. <dt><code>ca</code></dt>

  262. <dd><p>All condition registers: SCC, VCCZ, EXECZ

  263. </p>

  264. </dd>

  265. <dt><code>cs</code></dt>

  266. <dd><p>Scalar condition register: SCC

  267. </p>

  268. </dd>

  269. <dt><code>cV</code></dt>

  270. <dd><p>Vector condition register: VCC, VCC_LO, VCC_HI

  271. </p>

  272. </dd>

  273. <dt><code>e</code></dt>

  274. <dd><p>EXEC register (EXEC_LO and EXEC_HI)

  275. </p>

  276. </dd>

  277. <dt><code>RB</code></dt>

  278. <dd><p>Memory operand with address space suitable for <code>buffer_*</code> instructions

  279. </p>

  280. </dd>

  281. <dt><code>RF</code></dt>

  282. <dd><p>Memory operand with address space suitable for <code>flat_*</code> instructions

  283. </p>

  284. </dd>

  285. <dt><code>RS</code></dt>

  286. <dd><p>Memory operand with address space suitable for <code>s_*</code> instructions

  287. </p>

  288. </dd>

  289. <dt><code>RL</code></dt>

  290. <dd><p>Memory operand with address space suitable for <code>ds_*</code> LDS instructions

  291. </p>

  292. </dd>

  293. <dt><code>RG</code></dt>

  294. <dd><p>Memory operand with address space suitable for <code>ds_*</code> GDS instructions

  295. </p>

  296. </dd>

  297. <dt><code>RD</code></dt>

  298. <dd><p>Memory operand with address space suitable for any <code>ds_*</code> instructions

  299. </p>

  300. </dd>

  301. <dt><code>RM</code></dt>

  302. <dd><p>Memory operand with address space suitable for <code>global_*</code> instructions

  303. </p>

  304. </dd>

  305. </dl>

  306. 

  307. 

  308. </dd>

  309. <dt><em>ARC &mdash;<samp>config/arc/constraints.md</samp></em></dt>

  310. <dd><dl compact="compact">

  311. <dt><code>q</code></dt>

  312. <dd><p>Registers usable in ARCompact 16-bit instructions: <code>r0</code>-<code>r3</code>,

  313. <code>r12</code>-<code>r15</code>.  This constraint can only match when the <samp>-mq</samp>

  314. option is in effect.

  315. </p>

  316. </dd>

  317. <dt><code>e</code></dt>

  318. <dd><p>Registers usable as base-regs of memory addresses in ARCompact 16-bit memory

  319. instructions: <code>r0</code>-<code>r3</code>, <code>r12</code>-<code>r15</code>, <code>sp</code>.

  320. This constraint can only match when the <samp>-mq</samp>

  321. option is in effect.

  322. </p></dd>

  323. <dt><code>D</code></dt>

  324. <dd><p>ARC FPX (dpfp) 64-bit registers. <code>D0</code>, <code>D1</code>.

  325. </p>

  326. </dd>

  327. <dt><code>I</code></dt>

  328. <dd><p>A signed 12-bit integer constant.

  329. </p>

  330. </dd>

  331. <dt><code>Cal</code></dt>

  332. <dd><p>constant for arithmetic/logical operations.  This might be any constant

  333. that can be put into a long immediate by the assmbler or linker without

  334. involving a PIC relocation.

  335. </p>

  336. </dd>

  337. <dt><code>K</code></dt>

  338. <dd><p>A 3-bit unsigned integer constant.

  339. </p>

  340. </dd>

  341. <dt><code>L</code></dt>

  342. <dd><p>A 6-bit unsigned integer constant.

  343. </p>

  344. </dd>

  345. <dt><code>CnL</code></dt>

  346. <dd><p>One&rsquo;s complement of a 6-bit unsigned integer constant.

  347. </p>

  348. </dd>

  349. <dt><code>CmL</code></dt>

  350. <dd><p>Two&rsquo;s complement of a 6-bit unsigned integer constant.

  351. </p>

  352. </dd>

  353. <dt><code>M</code></dt>

  354. <dd><p>A 5-bit unsigned integer constant.

  355. </p>

  356. </dd>

  357. <dt><code>O</code></dt>

  358. <dd><p>A 7-bit unsigned integer constant.

  359. </p>

  360. </dd>

  361. <dt><code>P</code></dt>

  362. <dd><p>A 8-bit unsigned integer constant.

  363. </p>

  364. </dd>

  365. <dt><code>H</code></dt>

  366. <dd><p>Any const_double value.

  367. </p></dd>

  368. </dl>

  369. 

  370. </dd>

  371. <dt><em>ARM family&mdash;<samp>config/arm/constraints.md</samp></em></dt>

  372. <dd><dl compact="compact">

  373. <dt><code>h</code></dt>

  374. <dd><p>In Thumb state, the core registers <code>r8</code>-<code>r15</code>.

  375. </p>

  376. </dd>

  377. <dt><code>k</code></dt>

  378. <dd><p>The stack pointer register.

  379. </p>

  380. </dd>

  381. <dt><code>l</code></dt>

  382. <dd><p>In Thumb State the core registers <code>r0</code>-<code>r7</code>.  In ARM state this

  383. is an alias for the <code>r</code> constraint.

  384. </p>

  385. </dd>

  386. <dt><code>t</code></dt>

  387. <dd><p>VFP floating-point registers <code>s0</code>-<code>s31</code>.  Used for 32 bit values.

  388. </p>

  389. </dd>

  390. <dt><code>w</code></dt>

  391. <dd><p>VFP floating-point registers <code>d0</code>-<code>d31</code> and the appropriate

  392. subset <code>d0</code>-<code>d15</code> based on command line options.

  393. Used for 64 bit values only.  Not valid for Thumb1.

  394. </p>

  395. </dd>

  396. <dt><code>y</code></dt>

  397. <dd><p>The iWMMX co-processor registers.

  398. </p>

  399. </dd>

  400. <dt><code>z</code></dt>

  401. <dd><p>The iWMMX GR registers.

  402. </p>

  403. </dd>

  404. <dt><code>G</code></dt>

  405. <dd><p>The floating-point constant 0.0

  406. </p>

  407. </dd>

  408. <dt><code>I</code></dt>

  409. <dd><p>Integer that is valid as an immediate operand in a data processing

  410. instruction.  That is, an integer in the range 0 to 255 rotated by a

  411. multiple of 2

  412. </p>

  413. </dd>

  414. <dt><code>J</code></dt>

  415. <dd><p>Integer in the range -4095 to 4095

  416. </p>

  417. </dd>

  418. <dt><code>K</code></dt>

  419. <dd><p>Integer that satisfies constraint &lsquo;<samp>I</samp>&rsquo; when inverted (ones complement)

  420. </p>

  421. </dd>

  422. <dt><code>L</code></dt>

  423. <dd><p>Integer that satisfies constraint &lsquo;<samp>I</samp>&rsquo; when negated (twos complement)

  424. </p>

  425. </dd>

  426. <dt><code>M</code></dt>

  427. <dd><p>Integer in the range 0 to 32

  428. </p>

  429. </dd>

  430. <dt><code>Q</code></dt>

  431. <dd><p>A memory reference where the exact address is in a single register

  432. (&lsquo;&lsquo;<samp>m</samp>&rsquo;&rsquo; is preferable for <code>asm</code> statements)

  433. </p>

  434. </dd>

  435. <dt><code>R</code></dt>

  436. <dd><p>An item in the constant pool

  437. </p>

  438. </dd>

  439. <dt><code>S</code></dt>

  440. <dd><p>A symbol in the text segment of the current file

  441. </p>

  442. </dd>

  443. <dt><code>Uv</code></dt>

  444. <dd><p>A memory reference suitable for VFP load/store insns (reg+constant offset)

  445. </p>

  446. </dd>

  447. <dt><code>Uy</code></dt>

  448. <dd><p>A memory reference suitable for iWMMXt load/store instructions.

  449. </p>

  450. </dd>

  451. <dt><code>Uq</code></dt>

  452. <dd><p>A memory reference suitable for the ARMv4 ldrsb instruction.

  453. </p></dd>

  454. </dl>

  455. 

  456. </dd>

  457. <dt><em>AVR family&mdash;<samp>config/avr/constraints.md</samp></em></dt>

  458. <dd><dl compact="compact">

  459. <dt><code>l</code></dt>

  460. <dd><p>Registers from r0 to r15

  461. </p>

  462. </dd>

  463. <dt><code>a</code></dt>

  464. <dd><p>Registers from r16 to r23

  465. </p>

  466. </dd>

  467. <dt><code>d</code></dt>

  468. <dd><p>Registers from r16 to r31

  469. </p>

  470. </dd>

  471. <dt><code>w</code></dt>

  472. <dd><p>Registers from r24 to r31.  These registers can be used in &lsquo;<samp>adiw</samp>&rsquo; command

  473. </p>

  474. </dd>

  475. <dt><code>e</code></dt>

  476. <dd><p>Pointer register (r26&ndash;r31)

  477. </p>

  478. </dd>

  479. <dt><code>b</code></dt>

  480. <dd><p>Base pointer register (r28&ndash;r31)

  481. </p>

  482. </dd>

  483. <dt><code>q</code></dt>

  484. <dd><p>Stack pointer register (SPH:SPL)

  485. </p>

  486. </dd>

  487. <dt><code>t</code></dt>

  488. <dd><p>Temporary register r0

  489. </p>

  490. </dd>

  491. <dt><code>x</code></dt>

  492. <dd><p>Register pair X (r27:r26)

  493. </p>

  494. </dd>

  495. <dt><code>y</code></dt>

  496. <dd><p>Register pair Y (r29:r28)

  497. </p>

  498. </dd>

  499. <dt><code>z</code></dt>

  500. <dd><p>Register pair Z (r31:r30)

  501. </p>

  502. </dd>

  503. <dt><code>I</code></dt>

  504. <dd><p>Constant greater than -1, less than 64

  505. </p>

  506. </dd>

  507. <dt><code>J</code></dt>

  508. <dd><p>Constant greater than -64, less than 1

  509. </p>

  510. </dd>

  511. <dt><code>K</code></dt>

  512. <dd><p>Constant integer 2

  513. </p>

  514. </dd>

  515. <dt><code>L</code></dt>

  516. <dd><p>Constant integer 0

  517. </p>

  518. </dd>

  519. <dt><code>M</code></dt>

  520. <dd><p>Constant that fits in 8 bits

  521. </p>

  522. </dd>

  523. <dt><code>N</code></dt>

  524. <dd><p>Constant integer -1

  525. </p>

  526. </dd>

  527. <dt><code>O</code></dt>

  528. <dd><p>Constant integer 8, 16, or 24

  529. </p>

  530. </dd>

  531. <dt><code>P</code></dt>

  532. <dd><p>Constant integer 1

  533. </p>

  534. </dd>

  535. <dt><code>G</code></dt>

  536. <dd><p>A floating point constant 0.0

  537. </p>

  538. </dd>

  539. <dt><code>Q</code></dt>

  540. <dd><p>A memory address based on Y or Z pointer with displacement.

  541. </p></dd>

  542. </dl>

  543. 

  544. </dd>

  545. <dt><em>Blackfin family&mdash;<samp>config/bfin/constraints.md</samp></em></dt>

  546. <dd><dl compact="compact">

  547. <dt><code>a</code></dt>

  548. <dd><p>P register

  549. </p>

  550. </dd>

  551. <dt><code>d</code></dt>

  552. <dd><p>D register

  553. </p>

  554. </dd>

  555. <dt><code>z</code></dt>

  556. <dd><p>A call clobbered P register.

  557. </p>

  558. </dd>

  559. <dt><code>q<var>n</var></code></dt>

  560. <dd><p>A single register.  If <var>n</var> is in the range 0 to 7, the corresponding D

  561. register.  If it is <code>A</code>, then the register P0.

  562. </p>

  563. </dd>

  564. <dt><code>D</code></dt>

  565. <dd><p>Even-numbered D register

  566. </p>

  567. </dd>

  568. <dt><code>W</code></dt>

  569. <dd><p>Odd-numbered D register

  570. </p>

  571. </dd>

  572. <dt><code>e</code></dt>

  573. <dd><p>Accumulator register.

  574. </p>

  575. </dd>

  576. <dt><code>A</code></dt>

  577. <dd><p>Even-numbered accumulator register.

  578. </p>

  579. </dd>

  580. <dt><code>B</code></dt>

  581. <dd><p>Odd-numbered accumulator register.

  582. </p>

  583. </dd>

  584. <dt><code>b</code></dt>

  585. <dd><p>I register

  586. </p>

  587. </dd>

  588. <dt><code>v</code></dt>

  589. <dd><p>B register

  590. </p>

  591. </dd>

  592. <dt><code>f</code></dt>

  593. <dd><p>M register

  594. </p>

  595. </dd>

  596. <dt><code>c</code></dt>

  597. <dd><p>Registers used for circular buffering, i.e. I, B, or L registers.

  598. </p>

  599. </dd>

  600. <dt><code>C</code></dt>

  601. <dd><p>The CC register.

  602. </p>

  603. </dd>

  604. <dt><code>t</code></dt>

  605. <dd><p>LT0 or LT1.

  606. </p>

  607. </dd>

  608. <dt><code>k</code></dt>

  609. <dd><p>LC0 or LC1.

  610. </p>

  611. </dd>

  612. <dt><code>u</code></dt>

  613. <dd><p>LB0 or LB1.

  614. </p>

  615. </dd>

  616. <dt><code>x</code></dt>

  617. <dd><p>Any D, P, B, M, I or L register.

  618. </p>

  619. </dd>

  620. <dt><code>y</code></dt>

  621. <dd><p>Additional registers typically used only in prologues and epilogues: RETS,

  622. RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.

  623. </p>

  624. </dd>

  625. <dt><code>w</code></dt>

  626. <dd><p>Any register except accumulators or CC.

  627. </p>

  628. </dd>

  629. <dt><code>Ksh</code></dt>

  630. <dd><p>Signed 16 bit integer (in the range -32768 to 32767)

  631. </p>

  632. </dd>

  633. <dt><code>Kuh</code></dt>

  634. <dd><p>Unsigned 16 bit integer (in the range 0 to 65535)

  635. </p>

  636. </dd>

  637. <dt><code>Ks7</code></dt>

  638. <dd><p>Signed 7 bit integer (in the range -64 to 63)

  639. </p>

  640. </dd>

  641. <dt><code>Ku7</code></dt>

  642. <dd><p>Unsigned 7 bit integer (in the range 0 to 127)

  643. </p>

  644. </dd>

  645. <dt><code>Ku5</code></dt>

  646. <dd><p>Unsigned 5 bit integer (in the range 0 to 31)

  647. </p>

  648. </dd>

  649. <dt><code>Ks4</code></dt>

  650. <dd><p>Signed 4 bit integer (in the range -8 to 7)

  651. </p>

  652. </dd>

  653. <dt><code>Ks3</code></dt>

  654. <dd><p>Signed 3 bit integer (in the range -3 to 4)

  655. </p>

  656. </dd>

  657. <dt><code>Ku3</code></dt>

  658. <dd><p>Unsigned 3 bit integer (in the range 0 to 7)

  659. </p>

  660. </dd>

  661. <dt><code>P<var>n</var></code></dt>

  662. <dd><p>Constant <var>n</var>, where <var>n</var> is a single-digit constant in the range 0 to 4.

  663. </p>

  664. </dd>

  665. <dt><code>PA</code></dt>

  666. <dd><p>An integer equal to one of the MACFLAG_XXX constants that is suitable for

  667. use with either accumulator.

  668. </p>

  669. </dd>

  670. <dt><code>PB</code></dt>

  671. <dd><p>An integer equal to one of the MACFLAG_XXX constants that is suitable for

  672. use only with accumulator A1.

  673. </p>

  674. </dd>

  675. <dt><code>M1</code></dt>

  676. <dd><p>Constant 255.

  677. </p>

  678. </dd>

  679. <dt><code>M2</code></dt>

  680. <dd><p>Constant 65535.

  681. </p>

  682. </dd>

  683. <dt><code>J</code></dt>

  684. <dd><p>An integer constant with exactly a single bit set.

  685. </p>

  686. </dd>

  687. <dt><code>L</code></dt>

  688. <dd><p>An integer constant with all bits set except exactly one.

  689. </p>

  690. </dd>

  691. <dt><code>H</code></dt>

  692. <dt><code>Q</code></dt>

  693. <dd><p>Any SYMBOL_REF.

  694. </p></dd>

  695. </dl>

  696. 

  697. </dd>

  698. <dt><em>CR16 Architecture&mdash;<samp>config/cr16/cr16.h</samp></em></dt>

  699. <dd><dl compact="compact">

  700. <dt><code>b</code></dt>

  701. <dd><p>Registers from r0 to r14 (registers without stack pointer)

  702. </p>

  703. </dd>

  704. <dt><code>t</code></dt>

  705. <dd><p>Register from r0 to r11 (all 16-bit registers)

  706. </p>

  707. </dd>

  708. <dt><code>p</code></dt>

  709. <dd><p>Register from r12 to r15 (all 32-bit registers)

  710. </p>

  711. </dd>

  712. <dt><code>I</code></dt>

  713. <dd><p>Signed constant that fits in 4 bits

  714. </p>

  715. </dd>

  716. <dt><code>J</code></dt>

  717. <dd><p>Signed constant that fits in 5 bits

  718. </p>

  719. </dd>

  720. <dt><code>K</code></dt>

  721. <dd><p>Signed constant that fits in 6 bits

  722. </p>

  723. </dd>

  724. <dt><code>L</code></dt>

  725. <dd><p>Unsigned constant that fits in 4 bits

  726. </p>

  727. </dd>

  728. <dt><code>M</code></dt>

  729. <dd><p>Signed constant that fits in 32 bits

  730. </p>

  731. </dd>

  732. <dt><code>N</code></dt>

  733. <dd><p>Check for 64 bits wide constants for add/sub instructions

  734. </p>

  735. </dd>

  736. <dt><code>G</code></dt>

  737. <dd><p>Floating point constant that is legal for store immediate

  738. </p></dd>

  739. </dl>

  740. 

  741. </dd>

  742. <dt><em>C-SKY&mdash;<samp>config/csky/constraints.md</samp></em></dt>

  743. <dd><dl compact="compact">

  744. <dt><code>a</code></dt>

  745. <dd><p>The mini registers r0 - r7.

  746. </p>

  747. </dd>

  748. <dt><code>b</code></dt>

  749. <dd><p>The low registers r0 - r15.

  750. </p>

  751. </dd>

  752. <dt><code>c</code></dt>

  753. <dd><p>C register.

  754. </p>

  755. </dd>

  756. <dt><code>y</code></dt>

  757. <dd><p>HI and LO registers.

  758. </p>

  759. </dd>

  760. <dt><code>l</code></dt>

  761. <dd><p>LO register.

  762. </p>

  763. </dd>

  764. <dt><code>h</code></dt>

  765. <dd><p>HI register.

  766. </p>

  767. </dd>

  768. <dt><code>v</code></dt>

  769. <dd><p>Vector registers.

  770. </p>

  771. </dd>

  772. <dt><code>z</code></dt>

  773. <dd><p>Stack pointer register (SP).

  774. </p></dd>

  775. </dl>

  776. 

  777. <p>The C-SKY back end supports a large set of additional constraints

  778. that are only useful for instruction selection or splitting rather

  779. than inline asm, such as constraints representing constant integer

  780. ranges accepted by particular instruction encodings.

  781. Refer to the source code for details.

  782. </p>

  783. </dd>

  784. <dt><em>Epiphany&mdash;<samp>config/epiphany/constraints.md</samp></em></dt>

  785. <dd><dl compact="compact">

  786. <dt><code>U16</code></dt>

  787. <dd><p>An unsigned 16-bit constant.

  788. </p>

  789. </dd>

  790. <dt><code>K</code></dt>

  791. <dd><p>An unsigned 5-bit constant.

  792. </p>

  793. </dd>

  794. <dt><code>L</code></dt>

  795. <dd><p>A signed 11-bit constant.

  796. </p>

  797. </dd>

  798. <dt><code>Cm1</code></dt>

  799. <dd><p>A signed 11-bit constant added to -1.

  800. Can only match when the <samp>-m1reg-<var>reg</var></samp> option is active.

  801. </p>

  802. </dd>

  803. <dt><code>Cl1</code></dt>

  804. <dd><p>Left-shift of -1, i.e., a bit mask with a block of leading ones, the rest

  805. being a block of trailing zeroes.

  806. Can only match when the <samp>-m1reg-<var>reg</var></samp> option is active.

  807. </p>

  808. </dd>

  809. <dt><code>Cr1</code></dt>

  810. <dd><p>Right-shift of -1, i.e., a bit mask with a trailing block of ones, the

  811. rest being zeroes.  Or to put it another way, one less than a power of two.

  812. Can only match when the <samp>-m1reg-<var>reg</var></samp> option is active.

  813. </p>

  814. </dd>

  815. <dt><code>Cal</code></dt>

  816. <dd><p>Constant for arithmetic/logical operations.

  817. This is like <code>i</code>, except that for position independent code,

  818. no symbols / expressions needing relocations are allowed.

  819. </p>

  820. </dd>

  821. <dt><code>Csy</code></dt>

  822. <dd><p>Symbolic constant for call/jump instruction.

  823. </p>

  824. </dd>

  825. <dt><code>Rcs</code></dt>

  826. <dd><p>The register class usable in short insns.  This is a register class

  827. constraint, and can thus drive register allocation.

  828. This constraint won&rsquo;t match unless <samp>-mprefer-short-insn-regs</samp> is

  829. in effect.

  830. </p>

  831. </dd>

  832. <dt><code>Rsc</code></dt>

  833. <dd><p>The the register class of registers that can be used to hold a

  834. sibcall call address.  I.e., a caller-saved register.

  835. </p>

  836. </dd>

  837. <dt><code>Rct</code></dt>

  838. <dd><p>Core control register class.

  839. </p>

  840. </dd>

  841. <dt><code>Rgs</code></dt>

  842. <dd><p>The register group usable in short insns.

  843. This constraint does not use a register class, so that it only

  844. passively matches suitable registers, and doesn&rsquo;t drive register allocation.

  845. </p>

  846. </dd>

  847. <dt><code>Car</code></dt>

  848. <dd><p>Constant suitable for the addsi3_r pattern.  This is a valid offset

  849. For byte, halfword, or word addressing.

  850. </p>

  851. </dd>

  852. <dt><code>Rra</code></dt>

  853. <dd><p>Matches the return address if it can be replaced with the link register.

  854. </p>

  855. </dd>

  856. <dt><code>Rcc</code></dt>

  857. <dd><p>Matches the integer condition code register.

  858. </p>

  859. </dd>

  860. <dt><code>Sra</code></dt>

  861. <dd><p>Matches the return address if it is in a stack slot.

  862. </p>

  863. </dd>

  864. <dt><code>Cfm</code></dt>

  865. <dd><p>Matches control register values to switch fp mode, which are encapsulated in

  866. <code>UNSPEC_FP_MODE</code>.

  867. </p></dd>

  868. </dl>

  869. 

  870. </dd>

  871. <dt><em>FRV&mdash;<samp>config/frv/frv.h</samp></em></dt>

  872. <dd><dl compact="compact">

  873. <dt><code>a</code></dt>

  874. <dd><p>Register in the class <code>ACC_REGS</code> (<code>acc0</code> to <code>acc7</code>).

  875. </p>

  876. </dd>

  877. <dt><code>b</code></dt>

  878. <dd><p>Register in the class <code>EVEN_ACC_REGS</code> (<code>acc0</code> to <code>acc7</code>).

  879. </p>

  880. </dd>

  881. <dt><code>c</code></dt>

  882. <dd><p>Register in the class <code>CC_REGS</code> (<code>fcc0</code> to <code>fcc3</code> and

  883. <code>icc0</code> to <code>icc3</code>).

  884. </p>

  885. </dd>

  886. <dt><code>d</code></dt>

  887. <dd><p>Register in the class <code>GPR_REGS</code> (<code>gr0</code> to <code>gr63</code>).

  888. </p>

  889. </dd>

  890. <dt><code>e</code></dt>

  891. <dd><p>Register in the class <code>EVEN_REGS</code> (<code>gr0</code> to <code>gr63</code>).

  892. Odd registers are excluded not in the class but through the use of a machine

  893. mode larger than 4 bytes.

  894. </p>

  895. </dd>

  896. <dt><code>f</code></dt>

  897. <dd><p>Register in the class <code>FPR_REGS</code> (<code>fr0</code> to <code>fr63</code>).

  898. </p>

  899. </dd>

  900. <dt><code>h</code></dt>

  901. <dd><p>Register in the class <code>FEVEN_REGS</code> (<code>fr0</code> to <code>fr63</code>).

  902. Odd registers are excluded not in the class but through the use of a machine

  903. mode larger than 4 bytes.

  904. </p>

  905. </dd>

  906. <dt><code>l</code></dt>

  907. <dd><p>Register in the class <code>LR_REG</code> (the <code>lr</code> register).

  908. </p>

  909. </dd>

  910. <dt><code>q</code></dt>

  911. <dd><p>Register in the class <code>QUAD_REGS</code> (<code>gr2</code> to <code>gr63</code>).

  912. Register numbers not divisible by 4 are excluded not in the class but through

  913. the use of a machine mode larger than 8 bytes.

  914. </p>

  915. </dd>

  916. <dt><code>t</code></dt>

  917. <dd><p>Register in the class <code>ICC_REGS</code> (<code>icc0</code> to <code>icc3</code>).

  918. </p>

  919. </dd>

  920. <dt><code>u</code></dt>

  921. <dd><p>Register in the class <code>FCC_REGS</code> (<code>fcc0</code> to <code>fcc3</code>).

  922. </p>

  923. </dd>

  924. <dt><code>v</code></dt>

  925. <dd><p>Register in the class <code>ICR_REGS</code> (<code>cc4</code> to <code>cc7</code>).

  926. </p>

  927. </dd>

  928. <dt><code>w</code></dt>

  929. <dd><p>Register in the class <code>FCR_REGS</code> (<code>cc0</code> to <code>cc3</code>).

  930. </p>

  931. </dd>

  932. <dt><code>x</code></dt>

  933. <dd><p>Register in the class <code>QUAD_FPR_REGS</code> (<code>fr0</code> to <code>fr63</code>).

  934. Register numbers not divisible by 4 are excluded not in the class but through

  935. the use of a machine mode larger than 8 bytes.

  936. </p>

  937. </dd>

  938. <dt><code>z</code></dt>

  939. <dd><p>Register in the class <code>SPR_REGS</code> (<code>lcr</code> and <code>lr</code>).

  940. </p>

  941. </dd>

  942. <dt><code>A</code></dt>

  943. <dd><p>Register in the class <code>QUAD_ACC_REGS</code> (<code>acc0</code> to <code>acc7</code>).

  944. </p>

  945. </dd>

  946. <dt><code>B</code></dt>

  947. <dd><p>Register in the class <code>ACCG_REGS</code> (<code>accg0</code> to <code>accg7</code>).

  948. </p>

  949. </dd>

  950. <dt><code>C</code></dt>

  951. <dd><p>Register in the class <code>CR_REGS</code> (<code>cc0</code> to <code>cc7</code>).

  952. </p>

  953. </dd>

  954. <dt><code>G</code></dt>

  955. <dd><p>Floating point constant zero

  956. </p>

  957. </dd>

  958. <dt><code>I</code></dt>

  959. <dd><p>6-bit signed integer constant

  960. </p>

  961. </dd>

  962. <dt><code>J</code></dt>

  963. <dd><p>10-bit signed integer constant

  964. </p>

  965. </dd>

  966. <dt><code>L</code></dt>

  967. <dd><p>16-bit signed integer constant

  968. </p>

  969. </dd>

  970. <dt><code>M</code></dt>

  971. <dd><p>16-bit unsigned integer constant

  972. </p>

  973. </dd>

  974. <dt><code>N</code></dt>

  975. <dd><p>12-bit signed integer constant that is negative&mdash;i.e. in the

  976. range of -2048 to -1

  977. </p>

  978. </dd>

  979. <dt><code>O</code></dt>

  980. <dd><p>Constant zero

  981. </p>

  982. </dd>

  983. <dt><code>P</code></dt>

  984. <dd><p>12-bit signed integer constant that is greater than zero&mdash;i.e. in the

  985. range of 1 to 2047.

  986. </p>

  987. </dd>

  988. </dl>

  989. 

  990. </dd>

  991. <dt><em>FT32&mdash;<samp>config/ft32/constraints.md</samp></em></dt>

  992. <dd><dl compact="compact">

  993. <dt><code>A</code></dt>

  994. <dd><p>An absolute address

  995. </p>

  996. </dd>

  997. <dt><code>B</code></dt>

  998. <dd><p>An offset address

  999. </p>

  1000. </dd>

  1001. <dt><code>W</code></dt>

  1002. <dd><p>A register indirect memory operand

  1003. </p>

  1004. </dd>

  1005. <dt><code>e</code></dt>

  1006. <dd><p>An offset address.

  1007. </p>

  1008. </dd>

  1009. <dt><code>f</code></dt>

  1010. <dd><p>An offset address.

  1011. </p>

  1012. </dd>

  1013. <dt><code>O</code></dt>

  1014. <dd><p>The constant zero or one

  1015. </p>

  1016. </dd>

  1017. <dt><code>I</code></dt>

  1018. <dd><p>A 16-bit signed constant (-32768 &hellip; 32767)

  1019. </p>

  1020. </dd>

  1021. <dt><code>w</code></dt>

  1022. <dd><p>A bitfield mask suitable for bext or bins

  1023. </p>

  1024. </dd>

  1025. <dt><code>x</code></dt>

  1026. <dd><p>An inverted bitfield mask suitable for bext or bins

  1027. </p>

  1028. </dd>

  1029. <dt><code>L</code></dt>

  1030. <dd><p>A 16-bit unsigned constant, multiple of 4 (0 &hellip; 65532)

  1031. </p>

  1032. </dd>

  1033. <dt><code>S</code></dt>

  1034. <dd><p>A 20-bit signed constant (-524288 &hellip; 524287)

  1035. </p>

  1036. </dd>

  1037. <dt><code>b</code></dt>

  1038. <dd><p>A constant for a bitfield width (1 &hellip; 16)

  1039. </p>

  1040. </dd>

  1041. <dt><code>KA</code></dt>

  1042. <dd><p>A 10-bit signed constant (-512 &hellip; 511)

  1043. </p>

  1044. </dd>

  1045. </dl>

  1046. 

  1047. </dd>

  1048. <dt><em>Hewlett-Packard PA-RISC&mdash;<samp>config/pa/pa.h</samp></em></dt>

  1049. <dd><dl compact="compact">

  1050. <dt><code>a</code></dt>

  1051. <dd><p>General register 1

  1052. </p>

  1053. </dd>

  1054. <dt><code>f</code></dt>

  1055. <dd><p>Floating point register

  1056. </p>

  1057. </dd>

  1058. <dt><code>q</code></dt>

  1059. <dd><p>Shift amount register

  1060. </p>

  1061. </dd>

  1062. <dt><code>x</code></dt>

  1063. <dd><p>Floating point register (deprecated)

  1064. </p>

  1065. </dd>

  1066. <dt><code>y</code></dt>

  1067. <dd><p>Upper floating point register (32-bit), floating point register (64-bit)

  1068. </p>

  1069. </dd>

  1070. <dt><code>Z</code></dt>

  1071. <dd><p>Any register

  1072. </p>

  1073. </dd>

  1074. <dt><code>I</code></dt>

  1075. <dd><p>Signed 11-bit integer constant

  1076. </p>

  1077. </dd>

  1078. <dt><code>J</code></dt>

  1079. <dd><p>Signed 14-bit integer constant

  1080. </p>

  1081. </dd>

  1082. <dt><code>K</code></dt>

  1083. <dd><p>Integer constant that can be deposited with a <code>zdepi</code> instruction

  1084. </p>

  1085. </dd>

  1086. <dt><code>L</code></dt>

  1087. <dd><p>Signed 5-bit integer constant

  1088. </p>

  1089. </dd>

  1090. <dt><code>M</code></dt>

  1091. <dd><p>Integer constant 0

  1092. </p>

  1093. </dd>

  1094. <dt><code>N</code></dt>

  1095. <dd><p>Integer constant that can be loaded with a <code>ldil</code> instruction

  1096. </p>

  1097. </dd>

  1098. <dt><code>O</code></dt>

  1099. <dd><p>Integer constant whose value plus one is a power of 2

  1100. </p>

  1101. </dd>

  1102. <dt><code>P</code></dt>

  1103. <dd><p>Integer constant that can be used for <code>and</code> operations in <code>depi</code>

  1104. and <code>extru</code> instructions

  1105. </p>

  1106. </dd>

  1107. <dt><code>S</code></dt>

  1108. <dd><p>Integer constant 31

  1109. </p>

  1110. </dd>

  1111. <dt><code>U</code></dt>

  1112. <dd><p>Integer constant 63

  1113. </p>

  1114. </dd>

  1115. <dt><code>G</code></dt>

  1116. <dd><p>Floating-point constant 0.0

  1117. </p>

  1118. </dd>

  1119. <dt><code>A</code></dt>

  1120. <dd><p>A <code>lo_sum</code> data-linkage-table memory operand

  1121. </p>

  1122. </dd>

  1123. <dt><code>Q</code></dt>

  1124. <dd><p>A memory operand that can be used as the destination operand of an

  1125. integer store instruction

  1126. </p>

  1127. </dd>

  1128. <dt><code>R</code></dt>

  1129. <dd><p>A scaled or unscaled indexed memory operand

  1130. </p>

  1131. </dd>

  1132. <dt><code>T</code></dt>

  1133. <dd><p>A memory operand for floating-point loads and stores

  1134. </p>

  1135. </dd>

  1136. <dt><code>W</code></dt>

  1137. <dd><p>A register indirect memory operand

  1138. </p></dd>

  1139. </dl>

  1140. 

  1141. </dd>

  1142. <dt><em>Intel IA-64&mdash;<samp>config/ia64/ia64.h</samp></em></dt>

  1143. <dd><dl compact="compact">

  1144. <dt><code>a</code></dt>

  1145. <dd><p>General register <code>r0</code> to <code>r3</code> for <code>addl</code> instruction

  1146. </p>

  1147. </dd>

  1148. <dt><code>b</code></dt>

  1149. <dd><p>Branch register

  1150. </p>

  1151. </dd>

  1152. <dt><code>c</code></dt>

  1153. <dd><p>Predicate register (&lsquo;<samp>c</samp>&rsquo; as in &ldquo;conditional&rdquo;)

  1154. </p>

  1155. </dd>

  1156. <dt><code>d</code></dt>

  1157. <dd><p>Application register residing in M-unit

  1158. </p>

  1159. </dd>

  1160. <dt><code>e</code></dt>

  1161. <dd><p>Application register residing in I-unit

  1162. </p>

  1163. </dd>

  1164. <dt><code>f</code></dt>

  1165. <dd><p>Floating-point register

  1166. </p>

  1167. </dd>

  1168. <dt><code>m</code></dt>

  1169. <dd><p>Memory operand.  If used together with &lsquo;<samp>&lt;</samp>&rsquo; or &lsquo;<samp>&gt;</samp>&rsquo;,

  1170. the operand can have postincrement and postdecrement which

  1171. require printing with &lsquo;<samp>%Pn</samp>&rsquo; on IA-64.

  1172. </p>

  1173. </dd>

  1174. <dt><code>G</code></dt>

  1175. <dd><p>Floating-point constant 0.0 or 1.0

  1176. </p>

  1177. </dd>

  1178. <dt><code>I</code></dt>

  1179. <dd><p>14-bit signed integer constant

  1180. </p>

  1181. </dd>

  1182. <dt><code>J</code></dt>

  1183. <dd><p>22-bit signed integer constant

  1184. </p>

  1185. </dd>

  1186. <dt><code>K</code></dt>

  1187. <dd><p>8-bit signed integer constant for logical instructions

  1188. </p>

  1189. </dd>

  1190. <dt><code>L</code></dt>

  1191. <dd><p>8-bit adjusted signed integer constant for compare pseudo-ops

  1192. </p>

  1193. </dd>

  1194. <dt><code>M</code></dt>

  1195. <dd><p>6-bit unsigned integer constant for shift counts

  1196. </p>

  1197. </dd>

  1198. <dt><code>N</code></dt>

  1199. <dd><p>9-bit signed integer constant for load and store postincrements

  1200. </p>

  1201. </dd>

  1202. <dt><code>O</code></dt>

  1203. <dd><p>The constant zero

  1204. </p>

  1205. </dd>

  1206. <dt><code>P</code></dt>

  1207. <dd><p>0 or -1 for <code>dep</code> instruction

  1208. </p>

  1209. </dd>

  1210. <dt><code>Q</code></dt>

  1211. <dd><p>Non-volatile memory for floating-point loads and stores

  1212. </p>

  1213. </dd>

  1214. <dt><code>R</code></dt>

  1215. <dd><p>Integer constant in the range 1 to 4 for <code>shladd</code> instruction

  1216. </p>

  1217. </dd>

  1218. <dt><code>S</code></dt>

  1219. <dd><p>Memory operand except postincrement and postdecrement.  This is

  1220. now roughly the same as &lsquo;<samp>m</samp>&rsquo; when not used together with &lsquo;<samp>&lt;</samp>&rsquo;

  1221. or &lsquo;<samp>&gt;</samp>&rsquo;.

  1222. </p></dd>

  1223. </dl>

  1224. 

  1225. </dd>

  1226. <dt><em>M32C&mdash;<samp>config/m32c/m32c.c</samp></em></dt>

  1227. <dd><dl compact="compact">

  1228. <dt><code>Rsp</code></dt>

  1229. <dt><code>Rfb</code></dt>

  1230. <dt><code>Rsb</code></dt>

  1231. <dd><p>&lsquo;<samp>$sp</samp>&rsquo;, &lsquo;<samp>$fb</samp>&rsquo;, &lsquo;<samp>$sb</samp>&rsquo;.

  1232. </p>

  1233. </dd>

  1234. <dt><code>Rcr</code></dt>

  1235. <dd><p>Any control register, when they&rsquo;re 16 bits wide (nothing if control

  1236. registers are 24 bits wide)

  1237. </p>

  1238. </dd>

  1239. <dt><code>Rcl</code></dt>

  1240. <dd><p>Any control register, when they&rsquo;re 24 bits wide.

  1241. </p>

  1242. </dd>

  1243. <dt><code>R0w</code></dt>

  1244. <dt><code>R1w</code></dt>

  1245. <dt><code>R2w</code></dt>

  1246. <dt><code>R3w</code></dt>

  1247. <dd><p>$r0, $r1, $r2, $r3.

  1248. </p>

  1249. </dd>

  1250. <dt><code>R02</code></dt>

  1251. <dd><p>$r0 or $r2, or $r2r0 for 32 bit values.

  1252. </p>

  1253. </dd>

  1254. <dt><code>R13</code></dt>

  1255. <dd><p>$r1 or $r3, or $r3r1 for 32 bit values.

  1256. </p>

  1257. </dd>

  1258. <dt><code>Rdi</code></dt>

  1259. <dd><p>A register that can hold a 64 bit value.

  1260. </p>

  1261. </dd>

  1262. <dt><code>Rhl</code></dt>

  1263. <dd><p>$r0 or $r1 (registers with addressable high/low bytes)

  1264. </p>

  1265. </dd>

  1266. <dt><code>R23</code></dt>

  1267. <dd><p>$r2 or $r3

  1268. </p>

  1269. </dd>

  1270. <dt><code>Raa</code></dt>

  1271. <dd><p>Address registers

  1272. </p>

  1273. </dd>

  1274. <dt><code>Raw</code></dt>

  1275. <dd><p>Address registers when they&rsquo;re 16 bits wide.

  1276. </p>

  1277. </dd>

  1278. <dt><code>Ral</code></dt>

  1279. <dd><p>Address registers when they&rsquo;re 24 bits wide.

  1280. </p>

  1281. </dd>

  1282. <dt><code>Rqi</code></dt>

  1283. <dd><p>Registers that can hold QI values.

  1284. </p>

  1285. </dd>

  1286. <dt><code>Rad</code></dt>

  1287. <dd><p>Registers that can be used with displacements ($a0, $a1, $sb).

  1288. </p>

  1289. </dd>

  1290. <dt><code>Rsi</code></dt>

  1291. <dd><p>Registers that can hold 32 bit values.

  1292. </p>

  1293. </dd>

  1294. <dt><code>Rhi</code></dt>

  1295. <dd><p>Registers that can hold 16 bit values.

  1296. </p>

  1297. </dd>

  1298. <dt><code>Rhc</code></dt>

  1299. <dd><p>Registers chat can hold 16 bit values, including all control

  1300. registers.

  1301. </p>

  1302. </dd>

  1303. <dt><code>Rra</code></dt>

  1304. <dd><p>$r0 through R1, plus $a0 and $a1.

  1305. </p>

  1306. </dd>

  1307. <dt><code>Rfl</code></dt>

  1308. <dd><p>The flags register.

  1309. </p>

  1310. </dd>

  1311. <dt><code>Rmm</code></dt>

  1312. <dd><p>The memory-based pseudo-registers $mem0 through $mem15.

  1313. </p>

  1314. </dd>

  1315. <dt><code>Rpi</code></dt>

  1316. <dd><p>Registers that can hold pointers (16 bit registers for r8c, m16c; 24

  1317. bit registers for m32cm, m32c).

  1318. </p>

  1319. </dd>

  1320. <dt><code>Rpa</code></dt>

  1321. <dd><p>Matches multiple registers in a PARALLEL to form a larger register.

  1322. Used to match function return values.

  1323. </p>

  1324. </dd>

  1325. <dt><code>Is3</code></dt>

  1326. <dd><p>-8 &hellip; 7

  1327. </p>

  1328. </dd>

  1329. <dt><code>IS1</code></dt>

  1330. <dd><p>-128 &hellip; 127

  1331. </p>

  1332. </dd>

  1333. <dt><code>IS2</code></dt>

  1334. <dd><p>-32768 &hellip; 32767

  1335. </p>

  1336. </dd>

  1337. <dt><code>IU2</code></dt>

  1338. <dd><p>0 &hellip; 65535

  1339. </p>

  1340. </dd>

  1341. <dt><code>In4</code></dt>

  1342. <dd><p>-8 &hellip; -1 or 1 &hellip; 8

  1343. </p>

  1344. </dd>

  1345. <dt><code>In5</code></dt>

  1346. <dd><p>-16 &hellip; -1 or 1 &hellip; 16

  1347. </p>

  1348. </dd>

  1349. <dt><code>In6</code></dt>

  1350. <dd><p>-32 &hellip; -1 or 1 &hellip; 32

  1351. </p>

  1352. </dd>

  1353. <dt><code>IM2</code></dt>

  1354. <dd><p>-65536 &hellip; -1

  1355. </p>

  1356. </dd>

  1357. <dt><code>Ilb</code></dt>

  1358. <dd><p>An 8 bit value with exactly one bit set.

  1359. </p>

  1360. </dd>

  1361. <dt><code>Ilw</code></dt>

  1362. <dd><p>A 16 bit value with exactly one bit set.

  1363. </p>

  1364. </dd>

  1365. <dt><code>Sd</code></dt>

  1366. <dd><p>The common src/dest memory addressing modes.

  1367. </p>

  1368. </dd>

  1369. <dt><code>Sa</code></dt>

  1370. <dd><p>Memory addressed using $a0 or $a1.

  1371. </p>

  1372. </dd>

  1373. <dt><code>Si</code></dt>

  1374. <dd><p>Memory addressed with immediate addresses.

  1375. </p>

  1376. </dd>

  1377. <dt><code>Ss</code></dt>

  1378. <dd><p>Memory addressed using the stack pointer ($sp).

  1379. </p>

  1380. </dd>

  1381. <dt><code>Sf</code></dt>

  1382. <dd><p>Memory addressed using the frame base register ($fb).

  1383. </p>

  1384. </dd>

  1385. <dt><code>Ss</code></dt>

  1386. <dd><p>Memory addressed using the small base register ($sb).

  1387. </p>

  1388. </dd>

  1389. <dt><code>S1</code></dt>

  1390. <dd><p>$r1h

  1391. </p></dd>

  1392. </dl>

  1393. 

  1394. </dd>

  1395. <dt><em>MicroBlaze&mdash;<samp>config/microblaze/constraints.md</samp></em></dt>

  1396. <dd><dl compact="compact">

  1397. <dt><code>d</code></dt>

  1398. <dd><p>A general register (<code>r0</code> to <code>r31</code>).

  1399. </p>

  1400. </dd>

  1401. <dt><code>z</code></dt>

  1402. <dd><p>A status register (<code>rmsr</code>, <code>$fcc1</code> to <code>$fcc7</code>).

  1403. </p>

  1404. </dd>

  1405. </dl>

  1406. 

  1407. </dd>

  1408. <dt><em>MIPS&mdash;<samp>config/mips/constraints.md</samp></em></dt>

  1409. <dd><dl compact="compact">

  1410. <dt><code>d</code></dt>

  1411. <dd><p>A general-purpose register.  This is equivalent to <code>r</code> unless

  1412. generating MIPS16 code, in which case the MIPS16 register set is used.

  1413. </p>

  1414. </dd>

  1415. <dt><code>f</code></dt>

  1416. <dd><p>A floating-point register (if available).

  1417. </p>

  1418. </dd>

  1419. <dt><code>h</code></dt>

  1420. <dd><p>Formerly the <code>hi</code> register.  This constraint is no longer supported.

  1421. </p>

  1422. </dd>

  1423. <dt><code>l</code></dt>

  1424. <dd><p>The <code>lo</code> register.  Use this register to store values that are

  1425. no bigger than a word.

  1426. </p>

  1427. </dd>

  1428. <dt><code>x</code></dt>

  1429. <dd><p>The concatenated <code>hi</code> and <code>lo</code> registers.  Use this register

  1430. to store doubleword values.

  1431. </p>

  1432. </dd>

  1433. <dt><code>c</code></dt>

  1434. <dd><p>A register suitable for use in an indirect jump.  This will always be

  1435. <code>$25</code> for <samp>-mabicalls</samp>.

  1436. </p>

  1437. </dd>

  1438. <dt><code>v</code></dt>

  1439. <dd><p>Register <code>$3</code>.  Do not use this constraint in new code;

  1440. it is retained only for compatibility with glibc.

  1441. </p>

  1442. </dd>

  1443. <dt><code>y</code></dt>

  1444. <dd><p>Equivalent to <code>r</code>; retained for backwards compatibility.

  1445. </p>

  1446. </dd>

  1447. <dt><code>z</code></dt>

  1448. <dd><p>A floating-point condition code register.

  1449. </p>

  1450. </dd>

  1451. <dt><code>I</code></dt>

  1452. <dd><p>A signed 16-bit constant (for arithmetic instructions).

  1453. </p>

  1454. </dd>

  1455. <dt><code>J</code></dt>

  1456. <dd><p>Integer zero.

  1457. </p>

  1458. </dd>

  1459. <dt><code>K</code></dt>

  1460. <dd><p>An unsigned 16-bit constant (for logic instructions).

  1461. </p>

  1462. </dd>

  1463. <dt><code>L</code></dt>

  1464. <dd><p>A signed 32-bit constant in which the lower 16 bits are zero.

  1465. Such constants can be loaded using <code>lui</code>.

  1466. </p>

  1467. </dd>

  1468. <dt><code>M</code></dt>

  1469. <dd><p>A constant that cannot be loaded using <code>lui</code>, <code>addiu</code>

  1470. or <code>ori</code>.

  1471. </p>

  1472. </dd>

  1473. <dt><code>N</code></dt>

  1474. <dd><p>A constant in the range -65535 to -1 (inclusive).

  1475. </p>

  1476. </dd>

  1477. <dt><code>O</code></dt>

  1478. <dd><p>A signed 15-bit constant.

  1479. </p>

  1480. </dd>

  1481. <dt><code>P</code></dt>

  1482. <dd><p>A constant in the range 1 to 65535 (inclusive).

  1483. </p>

  1484. </dd>

  1485. <dt><code>G</code></dt>

  1486. <dd><p>Floating-point zero.

  1487. </p>

  1488. </dd>

  1489. <dt><code>R</code></dt>

  1490. <dd><p>An address that can be used in a non-macro load or store.

  1491. </p>

  1492. </dd>

  1493. <dt><code>ZC</code></dt>

  1494. <dd><p>A memory operand whose address is formed by a base register and offset

  1495. that is suitable for use in instructions with the same addressing mode

  1496. as <code>ll</code> and <code>sc</code>.

  1497. </p>

  1498. </dd>

  1499. <dt><code>ZD</code></dt>

  1500. <dd><p>An address suitable for a <code>prefetch</code> instruction, or for any other

  1501. instruction with the same addressing mode as <code>prefetch</code>.

  1502. </p></dd>

  1503. </dl>

  1504. 

  1505. </dd>

  1506. <dt><em>Motorola 680x0&mdash;<samp>config/m68k/constraints.md</samp></em></dt>

  1507. <dd><dl compact="compact">

  1508. <dt><code>a</code></dt>

  1509. <dd><p>Address register

  1510. </p>

  1511. </dd>

  1512. <dt><code>d</code></dt>

  1513. <dd><p>Data register

  1514. </p>

  1515. </dd>

  1516. <dt><code>f</code></dt>

  1517. <dd><p>68881 floating-point register, if available

  1518. </p>

  1519. </dd>

  1520. <dt><code>I</code></dt>

  1521. <dd><p>Integer in the range 1 to 8

  1522. </p>

  1523. </dd>

  1524. <dt><code>J</code></dt>

  1525. <dd><p>16-bit signed number

  1526. </p>

  1527. </dd>

  1528. <dt><code>K</code></dt>

  1529. <dd><p>Signed number whose magnitude is greater than 0x80

  1530. </p>

  1531. </dd>

  1532. <dt><code>L</code></dt>

  1533. <dd><p>Integer in the range -8 to -1

  1534. </p>

  1535. </dd>

  1536. <dt><code>M</code></dt>

  1537. <dd><p>Signed number whose magnitude is greater than 0x100

  1538. </p>

  1539. </dd>

  1540. <dt><code>N</code></dt>

  1541. <dd><p>Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate

  1542. </p>

  1543. </dd>

  1544. <dt><code>O</code></dt>

  1545. <dd><p>16 (for rotate using swap)

  1546. </p>

  1547. </dd>

  1548. <dt><code>P</code></dt>

  1549. <dd><p>Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate

  1550. </p>

  1551. </dd>

  1552. <dt><code>R</code></dt>

  1553. <dd><p>Numbers that mov3q can handle

  1554. </p>

  1555. </dd>

  1556. <dt><code>G</code></dt>

  1557. <dd><p>Floating point constant that is not a 68881 constant

  1558. </p>

  1559. </dd>

  1560. <dt><code>S</code></dt>

  1561. <dd><p>Operands that satisfy &rsquo;m&rsquo; when -mpcrel is in effect

  1562. </p>

  1563. </dd>

  1564. <dt><code>T</code></dt>

  1565. <dd><p>Operands that satisfy &rsquo;s&rsquo; when -mpcrel is not in effect

  1566. </p>

  1567. </dd>

  1568. <dt><code>Q</code></dt>

  1569. <dd><p>Address register indirect addressing mode

  1570. </p>

  1571. </dd>

  1572. <dt><code>U</code></dt>

  1573. <dd><p>Register offset addressing

  1574. </p>

  1575. </dd>

  1576. <dt><code>W</code></dt>

  1577. <dd><p>const_call_operand

  1578. </p>

  1579. </dd>

  1580. <dt><code>Cs</code></dt>

  1581. <dd><p>symbol_ref or const

  1582. </p>

  1583. </dd>

  1584. <dt><code>Ci</code></dt>

  1585. <dd><p>const_int

  1586. </p>

  1587. </dd>

  1588. <dt><code>C0</code></dt>

  1589. <dd><p>const_int 0

  1590. </p>

  1591. </dd>

  1592. <dt><code>Cj</code></dt>

  1593. <dd><p>Range of signed numbers that don&rsquo;t fit in 16 bits

  1594. </p>

  1595. </dd>

  1596. <dt><code>Cmvq</code></dt>

  1597. <dd><p>Integers valid for mvq

  1598. </p>

  1599. </dd>

  1600. <dt><code>Capsw</code></dt>

  1601. <dd><p>Integers valid for a moveq followed by a swap

  1602. </p>

  1603. </dd>

  1604. <dt><code>Cmvz</code></dt>

  1605. <dd><p>Integers valid for mvz

  1606. </p>

  1607. </dd>

  1608. <dt><code>Cmvs</code></dt>

  1609. <dd><p>Integers valid for mvs

  1610. </p>

  1611. </dd>

  1612. <dt><code>Ap</code></dt>

  1613. <dd><p>push_operand

  1614. </p>

  1615. </dd>

  1616. <dt><code>Ac</code></dt>

  1617. <dd><p>Non-register operands allowed in clr

  1618. </p>

  1619. </dd>

  1620. </dl>

  1621. 

  1622. </dd>

  1623. <dt><em>Moxie&mdash;<samp>config/moxie/constraints.md</samp></em></dt>

  1624. <dd><dl compact="compact">

  1625. <dt><code>A</code></dt>

  1626. <dd><p>An absolute address

  1627. </p>

  1628. </dd>

  1629. <dt><code>B</code></dt>

  1630. <dd><p>An offset address

  1631. </p>

  1632. </dd>

  1633. <dt><code>W</code></dt>

  1634. <dd><p>A register indirect memory operand

  1635. </p>

  1636. </dd>

  1637. <dt><code>I</code></dt>

  1638. <dd><p>A constant in the range of 0 to 255.

  1639. </p>

  1640. </dd>

  1641. <dt><code>N</code></dt>

  1642. <dd><p>A constant in the range of 0 to -255.

  1643. </p>

  1644. </dd>

  1645. </dl>

  1646. 

  1647. </dd>

  1648. <dt><em>MSP430&ndash;<samp>config/msp430/constraints.md</samp></em></dt>

  1649. <dd><dl compact="compact">

  1650. <dt><code>R12</code></dt>

  1651. <dd><p>Register R12.

  1652. </p>

  1653. </dd>

  1654. <dt><code>R13</code></dt>

  1655. <dd><p>Register R13.

  1656. </p>

  1657. </dd>

  1658. <dt><code>K</code></dt>

  1659. <dd><p>Integer constant 1.

  1660. </p>

  1661. </dd>

  1662. <dt><code>L</code></dt>

  1663. <dd><p>Integer constant -1^20..1^19.

  1664. </p>

  1665. </dd>

  1666. <dt><code>M</code></dt>

  1667. <dd><p>Integer constant 1-4.

  1668. </p>

  1669. </dd>

  1670. <dt><code>Ya</code></dt>

  1671. <dd><p>Memory references which do not require an extended MOVX instruction.

  1672. </p>

  1673. </dd>

  1674. <dt><code>Yl</code></dt>

  1675. <dd><p>Memory reference, labels only.

  1676. </p>

  1677. </dd>

  1678. <dt><code>Ys</code></dt>

  1679. <dd><p>Memory reference, stack only.

  1680. </p>

  1681. </dd>

  1682. </dl>

  1683. 

  1684. </dd>

  1685. <dt><em>NDS32&mdash;<samp>config/nds32/constraints.md</samp></em></dt>

  1686. <dd><dl compact="compact">

  1687. <dt><code>w</code></dt>

  1688. <dd><p>LOW register class $r0 to $r7 constraint for V3/V3M ISA.

  1689. </p></dd>

  1690. <dt><code>l</code></dt>

  1691. <dd><p>LOW register class $r0 to $r7.

  1692. </p></dd>

  1693. <dt><code>d</code></dt>

  1694. <dd><p>MIDDLE register class $r0 to $r11, $r16 to $r19.

  1695. </p></dd>

  1696. <dt><code>h</code></dt>

  1697. <dd><p>HIGH register class $r12 to $r14, $r20 to $r31.

  1698. </p></dd>

  1699. <dt><code>t</code></dt>

  1700. <dd><p>Temporary assist register $ta (i.e. $r15).

  1701. </p></dd>

  1702. <dt><code>k</code></dt>

  1703. <dd><p>Stack register $sp.

  1704. </p></dd>

  1705. <dt><code>Iu03</code></dt>

  1706. <dd><p>Unsigned immediate 3-bit value.

  1707. </p></dd>

  1708. <dt><code>In03</code></dt>

  1709. <dd><p>Negative immediate 3-bit value in the range of -7&ndash;0.

  1710. </p></dd>

  1711. <dt><code>Iu04</code></dt>

  1712. <dd><p>Unsigned immediate 4-bit value.

  1713. </p></dd>

  1714. <dt><code>Is05</code></dt>

  1715. <dd><p>Signed immediate 5-bit value.

  1716. </p></dd>

  1717. <dt><code>Iu05</code></dt>

  1718. <dd><p>Unsigned immediate 5-bit value.

  1719. </p></dd>

  1720. <dt><code>In05</code></dt>

  1721. <dd><p>Negative immediate 5-bit value in the range of -31&ndash;0.

  1722. </p></dd>

  1723. <dt><code>Ip05</code></dt>

  1724. <dd><p>Unsigned immediate 5-bit value for movpi45 instruction with range 16&ndash;47.

  1725. </p></dd>

  1726. <dt><code>Iu06</code></dt>

  1727. <dd><p>Unsigned immediate 6-bit value constraint for addri36.sp instruction.

  1728. </p></dd>

  1729. <dt><code>Iu08</code></dt>

  1730. <dd><p>Unsigned immediate 8-bit value.

  1731. </p></dd>

  1732. <dt><code>Iu09</code></dt>

  1733. <dd><p>Unsigned immediate 9-bit value.

  1734. </p></dd>

  1735. <dt><code>Is10</code></dt>

  1736. <dd><p>Signed immediate 10-bit value.

  1737. </p></dd>

  1738. <dt><code>Is11</code></dt>

  1739. <dd><p>Signed immediate 11-bit value.

  1740. </p></dd>

  1741. <dt><code>Is15</code></dt>

  1742. <dd><p>Signed immediate 15-bit value.

  1743. </p></dd>

  1744. <dt><code>Iu15</code></dt>

  1745. <dd><p>Unsigned immediate 15-bit value.

  1746. </p></dd>

  1747. <dt><code>Ic15</code></dt>

  1748. <dd><p>A constant which is not in the range of imm15u but ok for bclr instruction.

  1749. </p></dd>

  1750. <dt><code>Ie15</code></dt>

  1751. <dd><p>A constant which is not in the range of imm15u but ok for bset instruction.

  1752. </p></dd>

  1753. <dt><code>It15</code></dt>

  1754. <dd><p>A constant which is not in the range of imm15u but ok for btgl instruction.

  1755. </p></dd>

  1756. <dt><code>Ii15</code></dt>

  1757. <dd><p>A constant whose compliment value is in the range of imm15u

  1758. and ok for bitci instruction.

  1759. </p></dd>

  1760. <dt><code>Is16</code></dt>

  1761. <dd><p>Signed immediate 16-bit value.

  1762. </p></dd>

  1763. <dt><code>Is17</code></dt>

  1764. <dd><p>Signed immediate 17-bit value.

  1765. </p></dd>

  1766. <dt><code>Is19</code></dt>

  1767. <dd><p>Signed immediate 19-bit value.

  1768. </p></dd>

  1769. <dt><code>Is20</code></dt>

  1770. <dd><p>Signed immediate 20-bit value.

  1771. </p></dd>

  1772. <dt><code>Ihig</code></dt>

  1773. <dd><p>The immediate value that can be simply set high 20-bit.

  1774. </p></dd>

  1775. <dt><code>Izeb</code></dt>

  1776. <dd><p>The immediate value 0xff.

  1777. </p></dd>

  1778. <dt><code>Izeh</code></dt>

  1779. <dd><p>The immediate value 0xffff.

  1780. </p></dd>

  1781. <dt><code>Ixls</code></dt>

  1782. <dd><p>The immediate value 0x01.

  1783. </p></dd>

  1784. <dt><code>Ix11</code></dt>

  1785. <dd><p>The immediate value 0x7ff.

  1786. </p></dd>

  1787. <dt><code>Ibms</code></dt>

  1788. <dd><p>The immediate value with power of 2.

  1789. </p></dd>

  1790. <dt><code>Ifex</code></dt>

  1791. <dd><p>The immediate value with power of 2 minus 1.

  1792. </p></dd>

  1793. <dt><code>U33</code></dt>

  1794. <dd><p>Memory constraint for 333 format.

  1795. </p></dd>

  1796. <dt><code>U45</code></dt>

  1797. <dd><p>Memory constraint for 45 format.

  1798. </p></dd>

  1799. <dt><code>U37</code></dt>

  1800. <dd><p>Memory constraint for 37 format.

  1801. </p></dd>

  1802. </dl>

  1803. 

  1804. </dd>

  1805. <dt><em>Nios II family&mdash;<samp>config/nios2/constraints.md</samp></em></dt>

  1806. <dd><dl compact="compact">

  1807. <dt><code>I</code></dt>

  1808. <dd><p>Integer that is valid as an immediate operand in an

  1809. instruction taking a signed 16-bit number. Range

  1810. -32768 to 32767.

  1811. </p>

  1812. </dd>

  1813. <dt><code>J</code></dt>

  1814. <dd><p>Integer that is valid as an immediate operand in an

  1815. instruction taking an unsigned 16-bit number. Range

  1816. 0 to 65535.

  1817. </p>

  1818. </dd>

  1819. <dt><code>K</code></dt>

  1820. <dd><p>Integer that is valid as an immediate operand in an

  1821. instruction taking only the upper 16-bits of a

  1822. 32-bit number. Range 32-bit numbers with the lower

  1823. 16-bits being 0.

  1824. </p>

  1825. </dd>

  1826. <dt><code>L</code></dt>

  1827. <dd><p>Integer that is valid as an immediate operand for a 

  1828. shift instruction. Range 0 to 31.

  1829. </p>

  1830. </dd>

  1831. <dt><code>M</code></dt>

  1832. <dd><p>Integer that is valid as an immediate operand for

  1833. only the value 0. Can be used in conjunction with

  1834. the format modifier <code>z</code> to use <code>r0</code>

  1835. instead of <code>0</code> in the assembly output.

  1836. </p>

  1837. </dd>

  1838. <dt><code>N</code></dt>

  1839. <dd><p>Integer that is valid as an immediate operand for

  1840. a custom instruction opcode. Range 0 to 255.

  1841. </p>

  1842. </dd>

  1843. <dt><code>P</code></dt>

  1844. <dd><p>An immediate operand for R2 andchi/andci instructions. 

  1845. </p>

  1846. </dd>

  1847. <dt><code>S</code></dt>

  1848. <dd><p>Matches immediates which are addresses in the small

  1849. data section and therefore can be added to <code>gp</code>

  1850. as a 16-bit immediate to re-create their 32-bit value.

  1851. </p>

  1852. </dd>

  1853. <dt><code>U</code></dt>

  1854. <dd><p>Matches constants suitable as an operand for the rdprs and

  1855. cache instructions.

  1856. </p>

  1857. </dd>

  1858. <dt><code>v</code></dt>

  1859. <dd><p>A memory operand suitable for Nios II R2 load/store

  1860. exclusive instructions.

  1861. </p>

  1862. </dd>

  1863. <dt><code>w</code></dt>

  1864. <dd><p>A memory operand suitable for load/store IO and cache

  1865. instructions.

  1866. </p>

  1867. </dd>

  1868. <dt><code>T</code></dt>

  1869. <dd><p>A <code>const</code> wrapped <code>UNSPEC</code> expression,

  1870. representing a supported PIC or TLS relocation.

  1871. </p>

  1872. </dd>

  1873. </dl>

  1874. 

  1875. </dd>

  1876. <dt><em>OpenRISC&mdash;<samp>config/or1k/constraints.md</samp></em></dt>

  1877. <dd><dl compact="compact">

  1878. <dt><code>I</code></dt>

  1879. <dd><p>Integer that is valid as an immediate operand in an

  1880. instruction taking a signed 16-bit number. Range

  1881. -32768 to 32767.

  1882. </p>

  1883. </dd>

  1884. <dt><code>K</code></dt>

  1885. <dd><p>Integer that is valid as an immediate operand in an

  1886. instruction taking an unsigned 16-bit number. Range

  1887. 0 to 65535.

  1888. </p>

  1889. </dd>

  1890. <dt><code>M</code></dt>

  1891. <dd><p>Signed 16-bit constant shifted left 16 bits. (Used with <code>l.movhi</code>)

  1892. </p>

  1893. </dd>

  1894. <dt><code>O</code></dt>

  1895. <dd><p>Zero

  1896. </p>

  1897. </dd>

  1898. <dt><code>c</code></dt>

  1899. <dd><p>Register usable for sibcalls.

  1900. </p>

  1901. </dd>

  1902. </dl>

  1903. 

  1904. </dd>

  1905. <dt><em>PDP-11&mdash;<samp>config/pdp11/constraints.md</samp></em></dt>

  1906. <dd><dl compact="compact">

  1907. <dt><code>a</code></dt>

  1908. <dd><p>Floating point registers AC0 through AC3.  These can be loaded from/to

  1909. memory with a single instruction.

  1910. </p>

  1911. </dd>

  1912. <dt><code>d</code></dt>

  1913. <dd><p>Odd numbered general registers (R1, R3, R5).  These are used for

  1914. 16-bit multiply operations.

  1915. </p>

  1916. </dd>

  1917. <dt><code>D</code></dt>

  1918. <dd><p>A memory reference that is encoded within the opcode, but not

  1919. auto-increment or auto-decrement.

  1920. </p>

  1921. </dd>

  1922. <dt><code>f</code></dt>

  1923. <dd><p>Any of the floating point registers (AC0 through AC5).

  1924. </p>

  1925. </dd>

  1926. <dt><code>G</code></dt>

  1927. <dd><p>Floating point constant 0.

  1928. </p>

  1929. </dd>

  1930. <dt><code>h</code></dt>

  1931. <dd><p>Floating point registers AC4 and AC5.  These cannot be loaded from/to

  1932. memory with a single instruction.

  1933. </p>

  1934. </dd>

  1935. <dt><code>I</code></dt>

  1936. <dd><p>An integer constant that fits in 16 bits.

  1937. </p>

  1938. </dd>

  1939. <dt><code>J</code></dt>

  1940. <dd><p>An integer constant whose low order 16 bits are zero.

  1941. </p>

  1942. </dd>

  1943. <dt><code>K</code></dt>

  1944. <dd><p>An integer constant that does not meet the constraints for codes

  1945. &lsquo;<samp>I</samp>&rsquo; or &lsquo;<samp>J</samp>&rsquo;.

  1946. </p>

  1947. </dd>

  1948. <dt><code>L</code></dt>

  1949. <dd><p>The integer constant 1.

  1950. </p>

  1951. </dd>

  1952. <dt><code>M</code></dt>

  1953. <dd><p>The integer constant -1.

  1954. </p>

  1955. </dd>

  1956. <dt><code>N</code></dt>

  1957. <dd><p>The integer constant 0.

  1958. </p>

  1959. </dd>

  1960. <dt><code>O</code></dt>

  1961. <dd><p>Integer constants 0 through 3; shifts by these

  1962. amounts are handled as multiple single-bit shifts rather than a single

  1963. variable-length shift.

  1964. </p>

  1965. </dd>

  1966. <dt><code>Q</code></dt>

  1967. <dd><p>A memory reference which requires an additional word (address or

  1968. offset) after the opcode.

  1969. </p>

  1970. </dd>

  1971. <dt><code>R</code></dt>

  1972. <dd><p>A memory reference that is encoded within the opcode.

  1973. </p>

  1974. </dd>

  1975. </dl>

  1976. 

  1977. </dd>

  1978. <dt><em>PowerPC and IBM RS6000&mdash;<samp>config/rs6000/constraints.md</samp></em></dt>

  1979. <dd><dl compact="compact">

  1980. <dt><code>r</code></dt>

  1981. <dd><p>A general purpose register (GPR), <code>r0</code>&hellip;<code>r31</code>.

  1982. </p>

  1983. </dd>

  1984. <dt><code>b</code></dt>

  1985. <dd><p>A base register.  Like <code>r</code>, but <code>r0</code> is not allowed, so

  1986. <code>r1</code>&hellip;<code>r31</code>.

  1987. </p>

  1988. </dd>

  1989. <dt><code>f</code></dt>

  1990. <dd><p>A floating point register (FPR), <code>f0</code>&hellip;<code>f31</code>.

  1991. </p>

  1992. </dd>

  1993. <dt><code>d</code></dt>

  1994. <dd><p>A floating point register.  This is the same as <code>f</code> nowadays;

  1995. historically <code>f</code> was for single-precision and <code>d</code> was for

  1996. double-precision floating point.

  1997. </p>

  1998. </dd>

  1999. <dt><code>v</code></dt>

  2000. <dd><p>An Altivec vector register (VR), <code>v0</code>&hellip;<code>v31</code>.

  2001. </p>

  2002. </dd>

  2003. <dt><code>wa</code></dt>

  2004. <dd><p>A VSX register (VSR), <code>vs0</code>&hellip;<code>vs63</code>.  This is either an

  2005. FPR (<code>vs0</code>&hellip;<code>vs31</code> are <code>f0</code>&hellip;<code>f31</code>) or a VR

  2006. (<code>vs32</code>&hellip;<code>vs63</code> are <code>v0</code>&hellip;<code>v31</code>).

  2007. </p>

  2008. <p>When using <code>wa</code>, you should use the <code>%x</code> output modifier, so that

  2009. the correct register number is printed.  For example:

  2010. </p>

  2011. <div class="smallexample">

  2012. <pre class="smallexample">asm (&quot;xvadddp %x0,%x1,%x2&quot;

  2013.      : &quot;=wa&quot; (v1)

  2014.      : &quot;wa&quot; (v2), &quot;wa&quot; (v3));

  2015. </pre></div>

  2016. 

  2017. <p>You should not use <code>%x</code> for <code>v</code> operands:

  2018. </p>

  2019. <div class="smallexample">

  2020. <pre class="smallexample">asm (&quot;xsaddqp %0,%1,%2&quot;

  2021.      : &quot;=v&quot; (v1)

  2022.      : &quot;v&quot; (v2), &quot;v&quot; (v3));

  2023. </pre></div>

  2024. 

  2025. </dd>

  2026. <dt><code>h</code></dt>

  2027. <dd><p>A special register (<code>vrsave</code>, <code>ctr</code>, or <code>lr</code>).

  2028. </p>

  2029. </dd>

  2030. <dt><code>c</code></dt>

  2031. <dd><p>The count register, <code>ctr</code>.

  2032. </p>

  2033. </dd>

  2034. <dt><code>l</code></dt>

  2035. <dd><p>The link register, <code>lr</code>.

  2036. </p>

  2037. </dd>

  2038. <dt><code>x</code></dt>

  2039. <dd><p>Condition register field 0, <code>cr0</code>.

  2040. </p>

  2041. </dd>

  2042. <dt><code>y</code></dt>

  2043. <dd><p>Any condition register field, <code>cr0</code>&hellip;<code>cr7</code>.

  2044. </p>

  2045. </dd>

  2046. <dt><code>z</code></dt>

  2047. <dd><p>The carry bit, <code>XER[CA]</code>.

  2048. </p>

  2049. </dd>

  2050. <dt><code>we</code></dt>

  2051. <dd><p>Like <code>wa</code>, if <samp>-mpower9-vector</samp> and <samp>-m64</samp> are used;

  2052. otherwise, <code>NO_REGS</code>.

  2053. </p>

  2054. </dd>

  2055. <dt><code>wn</code></dt>

  2056. <dd><p>No register (<code>NO_REGS</code>).

  2057. </p>

  2058. </dd>

  2059. <dt><code>wr</code></dt>

  2060. <dd><p>Like <code>r</code>, if <samp>-mpowerpc64</samp> is used; otherwise, <code>NO_REGS</code>.

  2061. </p>

  2062. </dd>

  2063. <dt><code>wx</code></dt>

  2064. <dd><p>Like <code>d</code>, if <samp>-mpowerpc-gfxopt</samp> is used; otherwise, <code>NO_REGS</code>.

  2065. </p>

  2066. </dd>

  2067. <dt><code>wA</code></dt>

  2068. <dd><p>Like <code>b</code>, if <samp>-mpowerpc64</samp> is used; otherwise, <code>NO_REGS</code>.

  2069. </p>

  2070. </dd>

  2071. <dt><code>wB</code></dt>

  2072. <dd><p>Signed 5-bit constant integer that can be loaded into an Altivec register.

  2073. </p>

  2074. </dd>

  2075. <dt><code>wD</code></dt>

  2076. <dd><p>Int constant that is the element number of the 64-bit scalar in a vector.

  2077. </p>

  2078. </dd>

  2079. <dt><code>wE</code></dt>

  2080. <dd><p>Vector constant that can be loaded with the XXSPLTIB instruction.

  2081. </p>

  2082. </dd>

  2083. <dt><code>wF</code></dt>

  2084. <dd><p>Memory operand suitable for power8 GPR load fusion.

  2085. </p>

  2086. </dd>

  2087. <dt><code>wL</code></dt>

  2088. <dd><p>Int constant that is the element number mfvsrld accesses in a vector.

  2089. </p>

  2090. </dd>

  2091. <dt><code>wM</code></dt>

  2092. <dd><p>Match vector constant with all 1&rsquo;s if the XXLORC instruction is available.

  2093. </p>

  2094. </dd>

  2095. <dt><code>wO</code></dt>

  2096. <dd><p>Memory operand suitable for the ISA 3.0 vector d-form instructions.

  2097. </p>

  2098. </dd>

  2099. <dt><code>wQ</code></dt>

  2100. <dd><p>Memory operand suitable for the load/store quad instructions.

  2101. </p>

  2102. </dd>

  2103. <dt><code>wS</code></dt>

  2104. <dd><p>Vector constant that can be loaded with XXSPLTIB &amp; sign extension.

  2105. </p>

  2106. </dd>

  2107. <dt><code>wY</code></dt>

  2108. <dd><p>A memory operand for a DS-form instruction.

  2109. </p>

  2110. </dd>

  2111. <dt><code>wZ</code></dt>

  2112. <dd><p>An indexed or indirect memory operand, ignoring the bottom 4 bits.

  2113. </p>

  2114. </dd>

  2115. <dt><code>I</code></dt>

  2116. <dd><p>A signed 16-bit constant.

  2117. </p>

  2118. </dd>

  2119. <dt><code>J</code></dt>

  2120. <dd><p>An unsigned 16-bit constant shifted left 16 bits (use <code>L</code> instead

  2121. for <code>SImode</code> constants).

  2122. </p>

  2123. </dd>

  2124. <dt><code>K</code></dt>

  2125. <dd><p>An unsigned 16-bit constant.

  2126. </p>

  2127. </dd>

  2128. <dt><code>L</code></dt>

  2129. <dd><p>A signed 16-bit constant shifted left 16 bits.

  2130. </p>

  2131. </dd>

  2132. <dt><code>M</code></dt>

  2133. <dd><p>An integer constant greater than 31.

  2134. </p>

  2135. </dd>

  2136. <dt><code>N</code></dt>

  2137. <dd><p>An exact power of 2.

  2138. </p>

  2139. </dd>

  2140. <dt><code>O</code></dt>

  2141. <dd><p>The integer constant zero.

  2142. </p>

  2143. </dd>

  2144. <dt><code>P</code></dt>

  2145. <dd><p>A constant whose negation is a signed 16-bit constant.

  2146. </p>

  2147. </dd>

  2148. <dt><code>eI</code></dt>

  2149. <dd><p>A signed 34-bit integer constant if prefixed instructions are supported.

  2150. </p>

  2151. </dd>

  2152. <dt><code>G</code></dt>

  2153. <dd><p>A floating point constant that can be loaded into a register with one

  2154. instruction per word.

  2155. </p>

  2156. </dd>

  2157. <dt><code>H</code></dt>

  2158. <dd><p>A floating point constant that can be loaded into a register using

  2159. three instructions.

  2160. </p>

  2161. </dd>

  2162. <dt><code>m</code></dt>

  2163. <dd><p>A memory operand.

  2164. Normally, <code>m</code> does not allow addresses that update the base register.

  2165. If the <code>&lt;</code> or <code>&gt;</code> constraint is also used, they are allowed and

  2166. therefore on PowerPC targets in that case it is only safe

  2167. to use <code>m&lt;&gt;</code> in an <code>asm</code> statement if that <code>asm</code> statement

  2168. accesses the operand exactly once.  The <code>asm</code> statement must also

  2169. use <code>%U<var>&lt;opno&gt;</var></code> as a placeholder for the &ldquo;update&rdquo; flag in the

  2170. corresponding load or store instruction.  For example:

  2171. </p>

  2172. <div class="smallexample">

  2173. <pre class="smallexample">asm (&quot;st%U0 %1,%0&quot; : &quot;=m&lt;&gt;&quot; (mem) : &quot;r&quot; (val));

  2174. </pre></div>

  2175. 

  2176. <p>is correct but:

  2177. </p>

  2178. <div class="smallexample">

  2179. <pre class="smallexample">asm (&quot;st %1,%0&quot; : &quot;=m&lt;&gt;&quot; (mem) : &quot;r&quot; (val));

  2180. </pre></div>

  2181. 

  2182. <p>is not.

  2183. </p>

  2184. </dd>

  2185. <dt><code>es</code></dt>

  2186. <dd><p>A &ldquo;stable&rdquo; memory operand; that is, one which does not include any

  2187. automodification of the base register.  This used to be useful when

  2188. <code>m</code> allowed automodification of the base register, but as those

  2189. are now only allowed when <code>&lt;</code> or <code>&gt;</code> is used, <code>es</code> is

  2190. basically the same as <code>m</code> without <code>&lt;</code> and <code>&gt;</code>.

  2191. </p>

  2192. </dd>

  2193. <dt><code>Q</code></dt>

  2194. <dd><p>A memory operand addressed by just a base register.

  2195. </p>

  2196. </dd>

  2197. <dt><code>Y</code></dt>

  2198. <dd><p>A memory operand for a DQ-form instruction.

  2199. </p>

  2200. </dd>

  2201. <dt><code>Z</code></dt>

  2202. <dd><p>A memory operand accessed with indexed or indirect addressing.

  2203. </p>

  2204. </dd>

  2205. <dt><code>R</code></dt>

  2206. <dd><p>An AIX TOC entry.

  2207. </p>

  2208. </dd>

  2209. <dt><code>a</code></dt>

  2210. <dd><p>An indexed or indirect address.

  2211. </p>

  2212. </dd>

  2213. <dt><code>U</code></dt>

  2214. <dd><p>A V.4 small data reference.

  2215. </p>

  2216. </dd>

  2217. <dt><code>W</code></dt>

  2218. <dd><p>A vector constant that does not require memory.

  2219. </p>

  2220. </dd>

  2221. <dt><code>j</code></dt>

  2222. <dd><p>The zero vector constant.

  2223. </p>

  2224. </dd>

  2225. </dl>

  2226. 

  2227. </dd>

  2228. <dt><em>PRU&mdash;<samp>config/pru/constraints.md</samp></em></dt>

  2229. <dd><dl compact="compact">

  2230. <dt><code>I</code></dt>

  2231. <dd><p>An unsigned 8-bit integer constant.

  2232. </p>

  2233. </dd>

  2234. <dt><code>J</code></dt>

  2235. <dd><p>An unsigned 16-bit integer constant.

  2236. </p>

  2237. </dd>

  2238. <dt><code>L</code></dt>

  2239. <dd><p>An unsigned 5-bit integer constant (for shift counts).

  2240. </p>

  2241. </dd>

  2242. <dt><code>T</code></dt>

  2243. <dd><p>A text segment (program memory) constant label.

  2244. </p>

  2245. </dd>

  2246. <dt><code>Z</code></dt>

  2247. <dd><p>Integer constant zero.

  2248. </p>

  2249. </dd>

  2250. </dl>

  2251. 

  2252. </dd>

  2253. <dt><em>RL78&mdash;<samp>config/rl78/constraints.md</samp></em></dt>

  2254. <dd><dl compact="compact">

  2255. <dt><code>Int3</code></dt>

  2256. <dd><p>An integer constant in the range 1 &hellip; 7.

  2257. </p></dd>

  2258. <dt><code>Int8</code></dt>

  2259. <dd><p>An integer constant in the range 0 &hellip; 255.

  2260. </p></dd>

  2261. <dt><code>J</code></dt>

  2262. <dd><p>An integer constant in the range -255 &hellip; 0

  2263. </p></dd>

  2264. <dt><code>K</code></dt>

  2265. <dd><p>The integer constant 1.

  2266. </p></dd>

  2267. <dt><code>L</code></dt>

  2268. <dd><p>The integer constant -1.

  2269. </p></dd>

  2270. <dt><code>M</code></dt>

  2271. <dd><p>The integer constant 0.

  2272. </p></dd>

  2273. <dt><code>N</code></dt>

  2274. <dd><p>The integer constant 2.

  2275. </p></dd>

  2276. <dt><code>O</code></dt>

  2277. <dd><p>The integer constant -2.

  2278. </p></dd>

  2279. <dt><code>P</code></dt>

  2280. <dd><p>An integer constant in the range 1 &hellip; 15.

  2281. </p></dd>

  2282. <dt><code>Qbi</code></dt>

  2283. <dd><p>The built-in compare types&ndash;eq, ne, gtu, ltu, geu, and leu.

  2284. </p></dd>

  2285. <dt><code>Qsc</code></dt>

  2286. <dd><p>The synthetic compare types&ndash;gt, lt, ge, and le.

  2287. </p></dd>

  2288. <dt><code>Wab</code></dt>

  2289. <dd><p>A memory reference with an absolute address.

  2290. </p></dd>

  2291. <dt><code>Wbc</code></dt>

  2292. <dd><p>A memory reference using <code>BC</code> as a base register, with an optional offset.

  2293. </p></dd>

  2294. <dt><code>Wca</code></dt>

  2295. <dd><p>A memory reference using <code>AX</code>, <code>BC</code>, <code>DE</code>, or <code>HL</code> for the address, for calls.

  2296. </p></dd>

  2297. <dt><code>Wcv</code></dt>

  2298. <dd><p>A memory reference using any 16-bit register pair for the address, for calls.

  2299. </p></dd>

  2300. <dt><code>Wd2</code></dt>

  2301. <dd><p>A memory reference using <code>DE</code> as a base register, with an optional offset.

  2302. </p></dd>

  2303. <dt><code>Wde</code></dt>

  2304. <dd><p>A memory reference using <code>DE</code> as a base register, without any offset.

  2305. </p></dd>

  2306. <dt><code>Wfr</code></dt>

  2307. <dd><p>Any memory reference to an address in the far address space.

  2308. </p></dd>

  2309. <dt><code>Wh1</code></dt>

  2310. <dd><p>A memory reference using <code>HL</code> as a base register, with an optional one-byte offset.

  2311. </p></dd>

  2312. <dt><code>Whb</code></dt>

  2313. <dd><p>A memory reference using <code>HL</code> as a base register, with <code>B</code> or <code>C</code> as the index register.

  2314. </p></dd>

  2315. <dt><code>Whl</code></dt>

  2316. <dd><p>A memory reference using <code>HL</code> as a base register, without any offset.

  2317. </p></dd>

  2318. <dt><code>Ws1</code></dt>

  2319. <dd><p>A memory reference using <code>SP</code> as a base register, with an optional one-byte offset.

  2320. </p></dd>

  2321. <dt><code>Y</code></dt>

  2322. <dd><p>Any memory reference to an address in the near address space.

  2323. </p></dd>

  2324. <dt><code>A</code></dt>

  2325. <dd><p>The <code>AX</code> register.

  2326. </p></dd>

  2327. <dt><code>B</code></dt>

  2328. <dd><p>The <code>BC</code> register.

  2329. </p></dd>

  2330. <dt><code>D</code></dt>

  2331. <dd><p>The <code>DE</code> register.

  2332. </p></dd>

  2333. <dt><code>R</code></dt>

  2334. <dd><p><code>A</code> through <code>L</code> registers.

  2335. </p></dd>

  2336. <dt><code>S</code></dt>

  2337. <dd><p>The <code>SP</code> register.

  2338. </p></dd>

  2339. <dt><code>T</code></dt>

  2340. <dd><p>The <code>HL</code> register.

  2341. </p></dd>

  2342. <dt><code>Z08W</code></dt>

  2343. <dd><p>The 16-bit <code>R8</code> register.

  2344. </p></dd>

  2345. <dt><code>Z10W</code></dt>

  2346. <dd><p>The 16-bit <code>R10</code> register.

  2347. </p></dd>

  2348. <dt><code>Zint</code></dt>

  2349. <dd><p>The registers reserved for interrupts (<code>R24</code> to <code>R31</code>).

  2350. </p></dd>

  2351. <dt><code>a</code></dt>

  2352. <dd><p>The <code>A</code> register.

  2353. </p></dd>

  2354. <dt><code>b</code></dt>

  2355. <dd><p>The <code>B</code> register.

  2356. </p></dd>

  2357. <dt><code>c</code></dt>

  2358. <dd><p>The <code>C</code> register.

  2359. </p></dd>

  2360. <dt><code>d</code></dt>

  2361. <dd><p>The <code>D</code> register.

  2362. </p></dd>

  2363. <dt><code>e</code></dt>

  2364. <dd><p>The <code>E</code> register.

  2365. </p></dd>

  2366. <dt><code>h</code></dt>

  2367. <dd><p>The <code>H</code> register.

  2368. </p></dd>

  2369. <dt><code>l</code></dt>

  2370. <dd><p>The <code>L</code> register.

  2371. </p></dd>

  2372. <dt><code>v</code></dt>

  2373. <dd><p>The virtual registers.

  2374. </p></dd>

  2375. <dt><code>w</code></dt>

  2376. <dd><p>The <code>PSW</code> register.

  2377. </p></dd>

  2378. <dt><code>x</code></dt>

  2379. <dd><p>The <code>X</code> register.

  2380. </p>

  2381. </dd>

  2382. </dl>

  2383. 

  2384. </dd>

  2385. <dt><em>RISC-V&mdash;<samp>config/riscv/constraints.md</samp></em></dt>

  2386. <dd><dl compact="compact">

  2387. <dt><code>f</code></dt>

  2388. <dd><p>A floating-point register (if available).

  2389. </p>

  2390. </dd>

  2391. <dt><code>I</code></dt>

  2392. <dd><p>An I-type 12-bit signed immediate.

  2393. </p>

  2394. </dd>

  2395. <dt><code>J</code></dt>

  2396. <dd><p>Integer zero.

  2397. </p>

  2398. </dd>

  2399. <dt><code>K</code></dt>

  2400. <dd><p>A 5-bit unsigned immediate for CSR access instructions.

  2401. </p>

  2402. </dd>

  2403. <dt><code>A</code></dt>

  2404. <dd><p>An address that is held in a general-purpose register.

  2405. </p>

  2406. </dd>

  2407. </dl>

  2408. 

  2409. </dd>

  2410. <dt><em>RX&mdash;<samp>config/rx/constraints.md</samp></em></dt>

  2411. <dd><dl compact="compact">

  2412. <dt><code>Q</code></dt>

  2413. <dd><p>An address which does not involve register indirect addressing or

  2414. pre/post increment/decrement addressing.

  2415. </p>

  2416. </dd>

  2417. <dt><code>Symbol</code></dt>

  2418. <dd><p>A symbol reference.

  2419. </p>

  2420. </dd>

  2421. <dt><code>Int08</code></dt>

  2422. <dd><p>A constant in the range -256 to 255, inclusive.

  2423. </p>

  2424. </dd>

  2425. <dt><code>Sint08</code></dt>

  2426. <dd><p>A constant in the range -128 to 127, inclusive.

  2427. </p>

  2428. </dd>

  2429. <dt><code>Sint16</code></dt>

  2430. <dd><p>A constant in the range -32768 to 32767, inclusive.

  2431. </p>

  2432. </dd>

  2433. <dt><code>Sint24</code></dt>

  2434. <dd><p>A constant in the range -8388608 to 8388607, inclusive.

  2435. </p>

  2436. </dd>

  2437. <dt><code>Uint04</code></dt>

  2438. <dd><p>A constant in the range 0 to 15, inclusive.

  2439. </p>

  2440. </dd>

  2441. </dl>

  2442. 

  2443. </dd>

  2444. <dt><em>S/390 and zSeries&mdash;<samp>config/s390/s390.h</samp></em></dt>

  2445. <dd><dl compact="compact">

  2446. <dt><code>a</code></dt>

  2447. <dd><p>Address register (general purpose register except r0)

  2448. </p>

  2449. </dd>

  2450. <dt><code>c</code></dt>

  2451. <dd><p>Condition code register

  2452. </p>

  2453. </dd>

  2454. <dt><code>d</code></dt>

  2455. <dd><p>Data register (arbitrary general purpose register)

  2456. </p>

  2457. </dd>

  2458. <dt><code>f</code></dt>

  2459. <dd><p>Floating-point register

  2460. </p>

  2461. </dd>

  2462. <dt><code>I</code></dt>

  2463. <dd><p>Unsigned 8-bit constant (0&ndash;255)

  2464. </p>

  2465. </dd>

  2466. <dt><code>J</code></dt>

  2467. <dd><p>Unsigned 12-bit constant (0&ndash;4095)

  2468. </p>

  2469. </dd>

  2470. <dt><code>K</code></dt>

  2471. <dd><p>Signed 16-bit constant (-32768&ndash;32767)

  2472. </p>

  2473. </dd>

  2474. <dt><code>L</code></dt>

  2475. <dd><p>Value appropriate as displacement.

  2476. </p><dl compact="compact">

  2477. <dt><code>(0..4095)</code></dt>

  2478. <dd><p>for short displacement

  2479. </p></dd>

  2480. <dt><code>(-524288..524287)</code></dt>

  2481. <dd><p>for long displacement

  2482. </p></dd>

  2483. </dl>

  2484. 

  2485. </dd>

  2486. <dt><code>M</code></dt>

  2487. <dd><p>Constant integer with a value of 0x7fffffff.

  2488. </p>

  2489. </dd>

  2490. <dt><code>N</code></dt>

  2491. <dd><p>Multiple letter constraint followed by 4 parameter letters.

  2492. </p><dl compact="compact">

  2493. <dt><code>0..9:</code></dt>

  2494. <dd><p>number of the part counting from most to least significant

  2495. </p></dd>

  2496. <dt><code>H,Q:</code></dt>

  2497. <dd><p>mode of the part

  2498. </p></dd>

  2499. <dt><code>D,S,H:</code></dt>

  2500. <dd><p>mode of the containing operand

  2501. </p></dd>

  2502. <dt><code>0,F:</code></dt>

  2503. <dd><p>value of the other parts (F&mdash;all bits set)

  2504. </p></dd>

  2505. </dl>

  2506. <p>The constraint matches if the specified part of a constant

  2507. has a value different from its other parts.

  2508. </p>

  2509. </dd>

  2510. <dt><code>Q</code></dt>

  2511. <dd><p>Memory reference without index register and with short displacement.

  2512. </p>

  2513. </dd>

  2514. <dt><code>R</code></dt>

  2515. <dd><p>Memory reference with index register and short displacement.

  2516. </p>

  2517. </dd>

  2518. <dt><code>S</code></dt>

  2519. <dd><p>Memory reference without index register but with long displacement.

  2520. </p>

  2521. </dd>

  2522. <dt><code>T</code></dt>

  2523. <dd><p>Memory reference with index register and long displacement.

  2524. </p>

  2525. </dd>

  2526. <dt><code>U</code></dt>

  2527. <dd><p>Pointer with short displacement.

  2528. </p>

  2529. </dd>

  2530. <dt><code>W</code></dt>

  2531. <dd><p>Pointer with long displacement.

  2532. </p>

  2533. </dd>

  2534. <dt><code>Y</code></dt>

  2535. <dd><p>Shift count operand.

  2536. </p>

  2537. </dd>

  2538. </dl>

  2539. 

  2540. </dd>

  2541. <dt><em>SPARC&mdash;<samp>config/sparc/sparc.h</samp></em></dt>

  2542. <dd><dl compact="compact">

  2543. <dt><code>f</code></dt>

  2544. <dd><p>Floating-point register on the SPARC-V8 architecture and

  2545. lower floating-point register on the SPARC-V9 architecture.

  2546. </p>

  2547. </dd>

  2548. <dt><code>e</code></dt>

  2549. <dd><p>Floating-point register.  It is equivalent to &lsquo;<samp>f</samp>&rsquo; on the

  2550. SPARC-V8 architecture and contains both lower and upper

  2551. floating-point registers on the SPARC-V9 architecture.

  2552. </p>

  2553. </dd>

  2554. <dt><code>c</code></dt>

  2555. <dd><p>Floating-point condition code register.

  2556. </p>

  2557. </dd>

  2558. <dt><code>d</code></dt>

  2559. <dd><p>Lower floating-point register.  It is only valid on the SPARC-V9

  2560. architecture when the Visual Instruction Set is available.

  2561. </p>

  2562. </dd>

  2563. <dt><code>b</code></dt>

  2564. <dd><p>Floating-point register.  It is only valid on the SPARC-V9 architecture

  2565. when the Visual Instruction Set is available.

  2566. </p>

  2567. </dd>

  2568. <dt><code>h</code></dt>

  2569. <dd><p>64-bit global or out register for the SPARC-V8+ architecture.

  2570. </p>

  2571. </dd>

  2572. <dt><code>C</code></dt>

  2573. <dd><p>The constant all-ones, for floating-point.

  2574. </p>

  2575. </dd>

  2576. <dt><code>A</code></dt>

  2577. <dd><p>Signed 5-bit constant

  2578. </p>

  2579. </dd>

  2580. <dt><code>D</code></dt>

  2581. <dd><p>A vector constant

  2582. </p>

  2583. </dd>

  2584. <dt><code>I</code></dt>

  2585. <dd><p>Signed 13-bit constant

  2586. </p>

  2587. </dd>

  2588. <dt><code>J</code></dt>

  2589. <dd><p>Zero

  2590. </p>

  2591. </dd>

  2592. <dt><code>K</code></dt>

  2593. <dd><p>32-bit constant with the low 12 bits clear (a constant that can be

  2594. loaded with the <code>sethi</code> instruction)

  2595. </p>

  2596. </dd>

  2597. <dt><code>L</code></dt>

  2598. <dd><p>A constant in the range supported by <code>movcc</code> instructions (11-bit

  2599. signed immediate)

  2600. </p>

  2601. </dd>

  2602. <dt><code>M</code></dt>

  2603. <dd><p>A constant in the range supported by <code>movrcc</code> instructions (10-bit

  2604. signed immediate)

  2605. </p>

  2606. </dd>

  2607. <dt><code>N</code></dt>

  2608. <dd><p>Same as &lsquo;<samp>K</samp>&rsquo;, except that it verifies that bits that are not in the

  2609. lower 32-bit range are all zero.  Must be used instead of &lsquo;<samp>K</samp>&rsquo; for

  2610. modes wider than <code>SImode</code>

  2611. </p>

  2612. </dd>

  2613. <dt><code>O</code></dt>

  2614. <dd><p>The constant 4096

  2615. </p>

  2616. </dd>

  2617. <dt><code>G</code></dt>

  2618. <dd><p>Floating-point zero

  2619. </p>

  2620. </dd>

  2621. <dt><code>H</code></dt>

  2622. <dd><p>Signed 13-bit constant, sign-extended to 32 or 64 bits

  2623. </p>

  2624. </dd>

  2625. <dt><code>P</code></dt>

  2626. <dd><p>The constant -1

  2627. </p>

  2628. </dd>

  2629. <dt><code>Q</code></dt>

  2630. <dd><p>Floating-point constant whose integral representation can

  2631. be moved into an integer register using a single sethi

  2632. instruction

  2633. </p>

  2634. </dd>

  2635. <dt><code>R</code></dt>

  2636. <dd><p>Floating-point constant whose integral representation can

  2637. be moved into an integer register using a single mov

  2638. instruction

  2639. </p>

  2640. </dd>

  2641. <dt><code>S</code></dt>

  2642. <dd><p>Floating-point constant whose integral representation can

  2643. be moved into an integer register using a high/lo_sum

  2644. instruction sequence

  2645. </p>

  2646. </dd>

  2647. <dt><code>T</code></dt>

  2648. <dd><p>Memory address aligned to an 8-byte boundary

  2649. </p>

  2650. </dd>

  2651. <dt><code>U</code></dt>

  2652. <dd><p>Even register

  2653. </p>

  2654. </dd>

  2655. <dt><code>W</code></dt>

  2656. <dd><p>Memory address for &lsquo;<samp>e</samp>&rsquo; constraint registers

  2657. </p>

  2658. </dd>

  2659. <dt><code>w</code></dt>

  2660. <dd><p>Memory address with only a base register

  2661. </p>

  2662. </dd>

  2663. <dt><code>Y</code></dt>

  2664. <dd><p>Vector zero

  2665. </p>

  2666. </dd>

  2667. </dl>

  2668. 

  2669. </dd>

  2670. <dt><em>TI C6X family&mdash;<samp>config/c6x/constraints.md</samp></em></dt>

  2671. <dd><dl compact="compact">

  2672. <dt><code>a</code></dt>

  2673. <dd><p>Register file A (A0&ndash;A31).

  2674. </p>

  2675. </dd>

  2676. <dt><code>b</code></dt>

  2677. <dd><p>Register file B (B0&ndash;B31).

  2678. </p>

  2679. </dd>

  2680. <dt><code>A</code></dt>

  2681. <dd><p>Predicate registers in register file A (A0&ndash;A2 on C64X and

  2682. higher, A1 and A2 otherwise).

  2683. </p>

  2684. </dd>

  2685. <dt><code>B</code></dt>

  2686. <dd><p>Predicate registers in register file B (B0&ndash;B2).

  2687. </p>

  2688. </dd>

  2689. <dt><code>C</code></dt>

  2690. <dd><p>A call-used register in register file B (B0&ndash;B9, B16&ndash;B31).

  2691. </p>

  2692. </dd>

  2693. <dt><code>Da</code></dt>

  2694. <dd><p>Register file A, excluding predicate registers (A3&ndash;A31,

  2695. plus A0 if not C64X or higher).

  2696. </p>

  2697. </dd>

  2698. <dt><code>Db</code></dt>

  2699. <dd><p>Register file B, excluding predicate registers (B3&ndash;B31).

  2700. </p>

  2701. </dd>

  2702. <dt><code>Iu4</code></dt>

  2703. <dd><p>Integer constant in the range 0 &hellip; 15.

  2704. </p>

  2705. </dd>

  2706. <dt><code>Iu5</code></dt>

  2707. <dd><p>Integer constant in the range 0 &hellip; 31.

  2708. </p>

  2709. </dd>

  2710. <dt><code>In5</code></dt>

  2711. <dd><p>Integer constant in the range -31 &hellip; 0.

  2712. </p>

  2713. </dd>

  2714. <dt><code>Is5</code></dt>

  2715. <dd><p>Integer constant in the range -16 &hellip; 15.

  2716. </p>

  2717. </dd>

  2718. <dt><code>I5x</code></dt>

  2719. <dd><p>Integer constant that can be the operand of an ADDA or a SUBA insn.

  2720. </p>

  2721. </dd>

  2722. <dt><code>IuB</code></dt>

  2723. <dd><p>Integer constant in the range 0 &hellip; 65535.

  2724. </p>

  2725. </dd>

  2726. <dt><code>IsB</code></dt>

  2727. <dd><p>Integer constant in the range -32768 &hellip; 32767.

  2728. </p>

  2729. </dd>

  2730. <dt><code>IsC</code></dt>

  2731. <dd><p>Integer constant in the range <em>-2^{20}</em> &hellip; <em>2^{20} - 1</em>.

  2732. </p>

  2733. </dd>

  2734. <dt><code>Jc</code></dt>

  2735. <dd><p>Integer constant that is a valid mask for the clr instruction.

  2736. </p>

  2737. </dd>

  2738. <dt><code>Js</code></dt>

  2739. <dd><p>Integer constant that is a valid mask for the set instruction.

  2740. </p>

  2741. </dd>

  2742. <dt><code>Q</code></dt>

  2743. <dd><p>Memory location with A base register.

  2744. </p>

  2745. </dd>

  2746. <dt><code>R</code></dt>

  2747. <dd><p>Memory location with B base register.

  2748. </p>

  2749. </dd>

  2750. <dt><code>S0</code></dt>

  2751. <dd><p>On C64x+ targets, a GP-relative small data reference.

  2752. </p>

  2753. </dd>

  2754. <dt><code>S1</code></dt>

  2755. <dd><p>Any kind of <code>SYMBOL_REF</code>, for use in a call address.

  2756. </p>

  2757. </dd>

  2758. <dt><code>Si</code></dt>

  2759. <dd><p>Any kind of immediate operand, unless it matches the S0 constraint.

  2760. </p>

  2761. </dd>

  2762. <dt><code>T</code></dt>

  2763. <dd><p>Memory location with B base register, but not using a long offset.

  2764. </p>

  2765. </dd>

  2766. <dt><code>W</code></dt>

  2767. <dd><p>A memory operand with an address that cannot be used in an unaligned access.

  2768. </p>

  2769. </dd>

  2770. <dt><code>Z</code></dt>

  2771. <dd><p>Register B14 (aka DP).

  2772. </p>

  2773. </dd>

  2774. </dl>

  2775. 

  2776. </dd>

  2777. <dt><em>TILE-Gx&mdash;<samp>config/tilegx/constraints.md</samp></em></dt>

  2778. <dd><dl compact="compact">

  2779. <dt><code>R00</code></dt>

  2780. <dt><code>R01</code></dt>

  2781. <dt><code>R02</code></dt>

  2782. <dt><code>R03</code></dt>

  2783. <dt><code>R04</code></dt>

  2784. <dt><code>R05</code></dt>

  2785. <dt><code>R06</code></dt>

  2786. <dt><code>R07</code></dt>

  2787. <dt><code>R08</code></dt>

  2788. <dt><code>R09</code></dt>

  2789. <dt><code>R10</code></dt>

  2790. <dd><p>Each of these represents a register constraint for an individual

  2791. register, from r0 to r10.

  2792. </p>

  2793. </dd>

  2794. <dt><code>I</code></dt>

  2795. <dd><p>Signed 8-bit integer constant.

  2796. </p>

  2797. </dd>

  2798. <dt><code>J</code></dt>

  2799. <dd><p>Signed 16-bit integer constant.

  2800. </p>

  2801. </dd>

  2802. <dt><code>K</code></dt>

  2803. <dd><p>Unsigned 16-bit integer constant.

  2804. </p>

  2805. </dd>

  2806. <dt><code>L</code></dt>

  2807. <dd><p>Integer constant that fits in one signed byte when incremented by one

  2808. (-129 &hellip; 126).

  2809. </p>

  2810. </dd>

  2811. <dt><code>m</code></dt>

  2812. <dd><p>Memory operand.  If used together with &lsquo;<samp>&lt;</samp>&rsquo; or &lsquo;<samp>&gt;</samp>&rsquo;, the

  2813. operand can have postincrement which requires printing with &lsquo;<samp>%In</samp>&rsquo;

  2814. and &lsquo;<samp>%in</samp>&rsquo; on TILE-Gx.  For example:

  2815. </p>

  2816. <div class="smallexample">

  2817. <pre class="smallexample">asm (&quot;st_add %I0,%1,%i0&quot; : &quot;=m&lt;&gt;&quot; (*mem) : &quot;r&quot; (val));

  2818. </pre></div>

  2819. 

  2820. </dd>

  2821. <dt><code>M</code></dt>

  2822. <dd><p>A bit mask suitable for the BFINS instruction.

  2823. </p>

  2824. </dd>

  2825. <dt><code>N</code></dt>

  2826. <dd><p>Integer constant that is a byte tiled out eight times.

  2827. </p>

  2828. </dd>

  2829. <dt><code>O</code></dt>

  2830. <dd><p>The integer zero constant.

  2831. </p>

  2832. </dd>

  2833. <dt><code>P</code></dt>

  2834. <dd><p>Integer constant that is a sign-extended byte tiled out as four shorts.

  2835. </p>

  2836. </dd>

  2837. <dt><code>Q</code></dt>

  2838. <dd><p>Integer constant that fits in one signed byte when incremented

  2839. (-129 &hellip; 126), but excluding -1.

  2840. </p>

  2841. </dd>

  2842. <dt><code>S</code></dt>

  2843. <dd><p>Integer constant that has all 1 bits consecutive and starting at bit 0.

  2844. </p>

  2845. </dd>

  2846. <dt><code>T</code></dt>

  2847. <dd><p>A 16-bit fragment of a got, tls, or pc-relative reference.

  2848. </p>

  2849. </dd>

  2850. <dt><code>U</code></dt>

  2851. <dd><p>Memory operand except postincrement.  This is roughly the same as

  2852. &lsquo;<samp>m</samp>&rsquo; when not used together with &lsquo;<samp>&lt;</samp>&rsquo; or &lsquo;<samp>&gt;</samp>&rsquo;.

  2853. </p>

  2854. </dd>

  2855. <dt><code>W</code></dt>

  2856. <dd><p>An 8-element vector constant with identical elements.

  2857. </p>

  2858. </dd>

  2859. <dt><code>Y</code></dt>

  2860. <dd><p>A 4-element vector constant with identical elements.

  2861. </p>

  2862. </dd>

  2863. <dt><code>Z0</code></dt>

  2864. <dd><p>The integer constant 0xffffffff.

  2865. </p>

  2866. </dd>

  2867. <dt><code>Z1</code></dt>

  2868. <dd><p>The integer constant 0xffffffff00000000.

  2869. </p>

  2870. </dd>

  2871. </dl>

  2872. 

  2873. </dd>

  2874. <dt><em>TILEPro&mdash;<samp>config/tilepro/constraints.md</samp></em></dt>

  2875. <dd><dl compact="compact">

  2876. <dt><code>R00</code></dt>

  2877. <dt><code>R01</code></dt>

  2878. <dt><code>R02</code></dt>

  2879. <dt><code>R03</code></dt>

  2880. <dt><code>R04</code></dt>

  2881. <dt><code>R05</code></dt>

  2882. <dt><code>R06</code></dt>

  2883. <dt><code>R07</code></dt>

  2884. <dt><code>R08</code></dt>

  2885. <dt><code>R09</code></dt>

  2886. <dt><code>R10</code></dt>

  2887. <dd><p>Each of these represents a register constraint for an individual

  2888. register, from r0 to r10.

  2889. </p>

  2890. </dd>

  2891. <dt><code>I</code></dt>

  2892. <dd><p>Signed 8-bit integer constant.

  2893. </p>

  2894. </dd>

  2895. <dt><code>J</code></dt>

  2896. <dd><p>Signed 16-bit integer constant.

  2897. </p>

  2898. </dd>

  2899. <dt><code>K</code></dt>

  2900. <dd><p>Nonzero integer constant with low 16 bits zero.

  2901. </p>

  2902. </dd>

  2903. <dt><code>L</code></dt>

  2904. <dd><p>Integer constant that fits in one signed byte when incremented by one

  2905. (-129 &hellip; 126).

  2906. </p>

  2907. </dd>

  2908. <dt><code>m</code></dt>

  2909. <dd><p>Memory operand.  If used together with &lsquo;<samp>&lt;</samp>&rsquo; or &lsquo;<samp>&gt;</samp>&rsquo;, the

  2910. operand can have postincrement which requires printing with &lsquo;<samp>%In</samp>&rsquo;

  2911. and &lsquo;<samp>%in</samp>&rsquo; on TILEPro.  For example:

  2912. </p>

  2913. <div class="smallexample">

  2914. <pre class="smallexample">asm (&quot;swadd %I0,%1,%i0&quot; : &quot;=m&lt;&gt;&quot; (mem) : &quot;r&quot; (val));

  2915. </pre></div>

  2916. 

  2917. </dd>

  2918. <dt><code>M</code></dt>

  2919. <dd><p>A bit mask suitable for the MM instruction.

  2920. </p>

  2921. </dd>

  2922. <dt><code>N</code></dt>

  2923. <dd><p>Integer constant that is a byte tiled out four times.

  2924. </p>

  2925. </dd>

  2926. <dt><code>O</code></dt>

  2927. <dd><p>The integer zero constant.

  2928. </p>

  2929. </dd>

  2930. <dt><code>P</code></dt>

  2931. <dd><p>Integer constant that is a sign-extended byte tiled out as two shorts.

  2932. </p>

  2933. </dd>

  2934. <dt><code>Q</code></dt>

  2935. <dd><p>Integer constant that fits in one signed byte when incremented

  2936. (-129 &hellip; 126), but excluding -1.

  2937. </p>

  2938. </dd>

  2939. <dt><code>T</code></dt>

  2940. <dd><p>A symbolic operand, or a 16-bit fragment of a got, tls, or pc-relative

  2941. reference.

  2942. </p>

  2943. </dd>

  2944. <dt><code>U</code></dt>

  2945. <dd><p>Memory operand except postincrement.  This is roughly the same as

  2946. &lsquo;<samp>m</samp>&rsquo; when not used together with &lsquo;<samp>&lt;</samp>&rsquo; or &lsquo;<samp>&gt;</samp>&rsquo;.

  2947. </p>

  2948. </dd>

  2949. <dt><code>W</code></dt>

  2950. <dd><p>A 4-element vector constant with identical elements.

  2951. </p>

  2952. </dd>

  2953. <dt><code>Y</code></dt>

  2954. <dd><p>A 2-element vector constant with identical elements.

  2955. </p>

  2956. </dd>

  2957. </dl>

  2958. 

  2959. </dd>

  2960. <dt><em>Visium&mdash;<samp>config/visium/constraints.md</samp></em></dt>

  2961. <dd><dl compact="compact">

  2962. <dt><code>b</code></dt>

  2963. <dd><p>EAM register <code>mdb</code>

  2964. </p>

  2965. </dd>

  2966. <dt><code>c</code></dt>

  2967. <dd><p>EAM register <code>mdc</code>

  2968. </p>

  2969. </dd>

  2970. <dt><code>f</code></dt>

  2971. <dd><p>Floating point register

  2972. </p>

  2973. </dd>

  2974. <dt><code>k</code></dt>

  2975. <dd><p>Register for sibcall optimization

  2976. </p>

  2977. </dd>

  2978. <dt><code>l</code></dt>

  2979. <dd><p>General register, but not <code>r29</code>, <code>r30</code> and <code>r31</code>

  2980. </p>

  2981. </dd>

  2982. <dt><code>t</code></dt>

  2983. <dd><p>Register <code>r1</code>

  2984. </p>

  2985. </dd>

  2986. <dt><code>u</code></dt>

  2987. <dd><p>Register <code>r2</code>

  2988. </p>

  2989. </dd>

  2990. <dt><code>v</code></dt>

  2991. <dd><p>Register <code>r3</code>

  2992. </p>

  2993. </dd>

  2994. <dt><code>G</code></dt>

  2995. <dd><p>Floating-point constant 0.0

  2996. </p>

  2997. </dd>

  2998. <dt><code>J</code></dt>

  2999. <dd><p>Integer constant in the range 0 .. 65535 (16-bit immediate)

  3000. </p>

  3001. </dd>

  3002. <dt><code>K</code></dt>

  3003. <dd><p>Integer constant in the range 1 .. 31 (5-bit immediate)

  3004. </p>

  3005. </dd>

  3006. <dt><code>L</code></dt>

  3007. <dd><p>Integer constant in the range -65535 .. -1 (16-bit negative immediate)

  3008. </p>

  3009. </dd>

  3010. <dt><code>M</code></dt>

  3011. <dd><p>Integer constant -1

  3012. </p>

  3013. </dd>

  3014. <dt><code>O</code></dt>

  3015. <dd><p>Integer constant 0

  3016. </p>

  3017. </dd>

  3018. <dt><code>P</code></dt>

  3019. <dd><p>Integer constant 32

  3020. </p></dd>

  3021. </dl>

  3022. 

  3023. </dd>

  3024. <dt><em>x86 family&mdash;<samp>config/i386/constraints.md</samp></em></dt>

  3025. <dd><dl compact="compact">

  3026. <dt><code>R</code></dt>

  3027. <dd><p>Legacy register&mdash;the eight integer registers available on all

  3028. i386 processors (<code>a</code>, <code>b</code>, <code>c</code>, <code>d</code>,

  3029. <code>si</code>, <code>di</code>, <code>bp</code>, <code>sp</code>).

  3030. </p>

  3031. </dd>

  3032. <dt><code>q</code></dt>

  3033. <dd><p>Any register accessible as <code><var>r</var>l</code>.  In 32-bit mode, <code>a</code>,

  3034. <code>b</code>, <code>c</code>, and <code>d</code>; in 64-bit mode, any integer register.

  3035. </p>

  3036. </dd>

  3037. <dt><code>Q</code></dt>

  3038. <dd><p>Any register accessible as <code><var>r</var>h</code>: <code>a</code>, <code>b</code>,

  3039. <code>c</code>, and <code>d</code>.

  3040. </p>

  3041. </dd>

  3042. <dt><code>l</code></dt>

  3043. <dd><p>Any register that can be used as the index in a base+index memory

  3044. access: that is, any general register except the stack pointer.

  3045. </p>

  3046. </dd>

  3047. <dt><code>a</code></dt>

  3048. <dd><p>The <code>a</code> register.

  3049. </p>

  3050. </dd>

  3051. <dt><code>b</code></dt>

  3052. <dd><p>The <code>b</code> register.

  3053. </p>

  3054. </dd>

  3055. <dt><code>c</code></dt>

  3056. <dd><p>The <code>c</code> register.

  3057. </p>

  3058. </dd>

  3059. <dt><code>d</code></dt>

  3060. <dd><p>The <code>d</code> register.

  3061. </p>

  3062. </dd>

  3063. <dt><code>S</code></dt>

  3064. <dd><p>The <code>si</code> register.

  3065. </p>

  3066. </dd>

  3067. <dt><code>D</code></dt>

  3068. <dd><p>The <code>di</code> register.

  3069. </p>

  3070. </dd>

  3071. <dt><code>A</code></dt>

  3072. <dd><p>The <code>a</code> and <code>d</code> registers.  This class is used for instructions

  3073. that return double word results in the <code>ax:dx</code> register pair.  Single

  3074. word values will be allocated either in <code>ax</code> or <code>dx</code>.

  3075. For example on i386 the following implements <code>rdtsc</code>:

  3076. </p>

  3077. <div class="smallexample">

  3078. <pre class="smallexample">unsigned long long rdtsc (void)

  3079. {

  3080.   unsigned long long tick;

  3081.   __asm__ __volatile__(&quot;rdtsc&quot;:&quot;=A&quot;(tick));

  3082.   return tick;

  3083. }

  3084. </pre></div>

  3085. 

  3086. <p>This is not correct on x86-64 as it would allocate tick in either <code>ax</code>

  3087. or <code>dx</code>.  You have to use the following variant instead:

  3088. </p>

  3089. <div class="smallexample">

  3090. <pre class="smallexample">unsigned long long rdtsc (void)

  3091. {

  3092.   unsigned int tickl, tickh;

  3093.   __asm__ __volatile__(&quot;rdtsc&quot;:&quot;=a&quot;(tickl),&quot;=d&quot;(tickh));

  3094.   return ((unsigned long long)tickh &lt;&lt; 32)|tickl;

  3095. }

  3096. </pre></div>

  3097. 

  3098. </dd>

  3099. <dt><code>U</code></dt>

  3100. <dd><p>The call-clobbered integer registers.

  3101. </p>

  3102. </dd>

  3103. <dt><code>f</code></dt>

  3104. <dd><p>Any 80387 floating-point (stack) register.

  3105. </p>

  3106. </dd>

  3107. <dt><code>t</code></dt>

  3108. <dd><p>Top of 80387 floating-point stack (<code>%st(0)</code>).

  3109. </p>

  3110. </dd>

  3111. <dt><code>u</code></dt>

  3112. <dd><p>Second from top of 80387 floating-point stack (<code>%st(1)</code>).

  3113. </p>

  3114. </dd>

  3115. <dt><code>Yk</code></dt>

  3116. <dd><p>Any mask register that can be used as a predicate, i.e. <code>k1-k7</code>.

  3117. </p>

  3118. </dd>

  3119. <dt><code>k</code></dt>

  3120. <dd><p>Any mask register.

  3121. </p>

  3122. </dd>

  3123. <dt><code>y</code></dt>

  3124. <dd><p>Any MMX register.

  3125. </p>

  3126. </dd>

  3127. <dt><code>x</code></dt>

  3128. <dd><p>Any SSE register.

  3129. </p>

  3130. </dd>

  3131. <dt><code>v</code></dt>

  3132. <dd><p>Any EVEX encodable SSE register (<code>%xmm0-%xmm31</code>).

  3133. </p>

  3134. </dd>

  3135. <dt><code>w</code></dt>

  3136. <dd><p>Any bound register.

  3137. </p>

  3138. </dd>

  3139. <dt><code>Yz</code></dt>

  3140. <dd><p>First SSE register (<code>%xmm0</code>).

  3141. </p>

  3142. </dd>

  3143. <dt><code>Yi</code></dt>

  3144. <dd><p>Any SSE register, when SSE2 and inter-unit moves are enabled.

  3145. </p>

  3146. </dd>

  3147. <dt><code>Yj</code></dt>

  3148. <dd><p>Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled.

  3149. </p>

  3150. </dd>

  3151. <dt><code>Ym</code></dt>

  3152. <dd><p>Any MMX register, when inter-unit moves are enabled.

  3153. </p>

  3154. </dd>

  3155. <dt><code>Yn</code></dt>

  3156. <dd><p>Any MMX register, when inter-unit moves from vector registers are enabled.

  3157. </p>

  3158. </dd>

  3159. <dt><code>Yp</code></dt>

  3160. <dd><p>Any integer register when <code>TARGET_PARTIAL_REG_STALL</code> is disabled.

  3161. </p>

  3162. </dd>

  3163. <dt><code>Ya</code></dt>

  3164. <dd><p>Any integer register when zero extensions with <code>AND</code> are disabled.

  3165. </p>

  3166. </dd>

  3167. <dt><code>Yb</code></dt>

  3168. <dd><p>Any register that can be used as the GOT base when calling<br>

  3169. <code>___tls_get_addr</code>: that is, any general register except <code>a</code>

  3170. and <code>sp</code> registers, for <samp>-fno-plt</samp> if linker supports it.

  3171. Otherwise, <code>b</code> register.

  3172. </p>

  3173. </dd>

  3174. <dt><code>Yf</code></dt>

  3175. <dd><p>Any x87 register when 80387 floating-point arithmetic is enabled.

  3176. </p>

  3177. </dd>

  3178. <dt><code>Yr</code></dt>

  3179. <dd><p>Lower SSE register when avoiding REX prefix and all SSE registers otherwise.

  3180. </p>

  3181. </dd>

  3182. <dt><code>Yv</code></dt>

  3183. <dd><p>For AVX512VL, any EVEX-encodable SSE register (<code>%xmm0-%xmm31</code>),

  3184. otherwise any SSE register.

  3185. </p>

  3186. </dd>

  3187. <dt><code>Yh</code></dt>

  3188. <dd><p>Any EVEX-encodable SSE register, that has number factor of four.

  3189. </p>

  3190. </dd>

  3191. <dt><code>Bf</code></dt>

  3192. <dd><p>Flags register operand.

  3193. </p>

  3194. </dd>

  3195. <dt><code>Bg</code></dt>

  3196. <dd><p>GOT memory operand.

  3197. </p>

  3198. </dd>

  3199. <dt><code>Bm</code></dt>

  3200. <dd><p>Vector memory operand.

  3201. </p>

  3202. </dd>

  3203. <dt><code>Bc</code></dt>

  3204. <dd><p>Constant memory operand.

  3205. </p>

  3206. </dd>

  3207. <dt><code>Bn</code></dt>

  3208. <dd><p>Memory operand without REX prefix.

  3209. </p>

  3210. </dd>

  3211. <dt><code>Bs</code></dt>

  3212. <dd><p>Sibcall memory operand.

  3213. </p>

  3214. </dd>

  3215. <dt><code>Bw</code></dt>

  3216. <dd><p>Call memory operand.

  3217. </p>

  3218. </dd>

  3219. <dt><code>Bz</code></dt>

  3220. <dd><p>Constant call address operand.

  3221. </p>

  3222. </dd>

  3223. <dt><code>BC</code></dt>

  3224. <dd><p>SSE constant -1 operand.

  3225. </p>

  3226. </dd>

  3227. <dt><code>I</code></dt>

  3228. <dd><p>Integer constant in the range 0 &hellip; 31, for 32-bit shifts.

  3229. </p>

  3230. </dd>

  3231. <dt><code>J</code></dt>

  3232. <dd><p>Integer constant in the range 0 &hellip; 63, for 64-bit shifts.

  3233. </p>

  3234. </dd>

  3235. <dt><code>K</code></dt>

  3236. <dd><p>Signed 8-bit integer constant.

  3237. </p>

  3238. </dd>

  3239. <dt><code>L</code></dt>

  3240. <dd><p><code>0xFF</code> or <code>0xFFFF</code>, for andsi as a zero-extending move.

  3241. </p>

  3242. </dd>

  3243. <dt><code>M</code></dt>

  3244. <dd><p>0, 1, 2, or 3 (shifts for the <code>lea</code> instruction).

  3245. </p>

  3246. </dd>

  3247. <dt><code>N</code></dt>

  3248. <dd><p>Unsigned 8-bit integer constant (for <code>in</code> and <code>out</code>

  3249. instructions).

  3250. </p>

  3251. </dd>

  3252. <dt><code>O</code></dt>

  3253. <dd><p>Integer constant in the range 0 &hellip; 127, for 128-bit shifts.

  3254. </p>

  3255. </dd>

  3256. <dt><code>G</code></dt>

  3257. <dd><p>Standard 80387 floating point constant.

  3258. </p>

  3259. </dd>

  3260. <dt><code>C</code></dt>

  3261. <dd><p>SSE constant zero operand.

  3262. </p>

  3263. </dd>

  3264. <dt><code>e</code></dt>

  3265. <dd><p>32-bit signed integer constant, or a symbolic reference known

  3266. to fit that range (for immediate operands in sign-extending x86-64

  3267. instructions).

  3268. </p>

  3269. </dd>

  3270. <dt><code>We</code></dt>

  3271. <dd><p>32-bit signed integer constant, or a symbolic reference known

  3272. to fit that range (for sign-extending conversion operations that

  3273. require non-<code>VOIDmode</code> immediate operands).

  3274. </p>

  3275. </dd>

  3276. <dt><code>Wz</code></dt>

  3277. <dd><p>32-bit unsigned integer constant, or a symbolic reference known

  3278. to fit that range (for zero-extending conversion operations that

  3279. require non-<code>VOIDmode</code> immediate operands).

  3280. </p>

  3281. </dd>

  3282. <dt><code>Wd</code></dt>

  3283. <dd><p>128-bit integer constant where both the high and low 64-bit word

  3284. satisfy the <code>e</code> constraint.

  3285. </p>

  3286. </dd>

  3287. <dt><code>Z</code></dt>

  3288. <dd><p>32-bit unsigned integer constant, or a symbolic reference known

  3289. to fit that range (for immediate operands in zero-extending x86-64

  3290. instructions).

  3291. </p>

  3292. </dd>

  3293. <dt><code>Tv</code></dt>

  3294. <dd><p>VSIB address operand.

  3295. </p>

  3296. </dd>

  3297. <dt><code>Ts</code></dt>

  3298. <dd><p>Address operand without segment register.

  3299. </p>

  3300. </dd>

  3301. </dl>

  3302. 

  3303. </dd>

  3304. <dt><em>Xstormy16&mdash;<samp>config/stormy16/stormy16.h</samp></em></dt>

  3305. <dd><dl compact="compact">

  3306. <dt><code>a</code></dt>

  3307. <dd><p>Register r0.

  3308. </p>

  3309. </dd>

  3310. <dt><code>b</code></dt>

  3311. <dd><p>Register r1.

  3312. </p>

  3313. </dd>

  3314. <dt><code>c</code></dt>

  3315. <dd><p>Register r2.

  3316. </p>

  3317. </dd>

  3318. <dt><code>d</code></dt>

  3319. <dd><p>Register r8.

  3320. </p>

  3321. </dd>

  3322. <dt><code>e</code></dt>

  3323. <dd><p>Registers r0 through r7.

  3324. </p>

  3325. </dd>

  3326. <dt><code>t</code></dt>

  3327. <dd><p>Registers r0 and r1.

  3328. </p>

  3329. </dd>

  3330. <dt><code>y</code></dt>

  3331. <dd><p>The carry register.

  3332. </p>

  3333. </dd>

  3334. <dt><code>z</code></dt>

  3335. <dd><p>Registers r8 and r9.

  3336. </p>

  3337. </dd>

  3338. <dt><code>I</code></dt>

  3339. <dd><p>A constant between 0 and 3 inclusive.

  3340. </p>

  3341. </dd>

  3342. <dt><code>J</code></dt>

  3343. <dd><p>A constant that has exactly one bit set.

  3344. </p>

  3345. </dd>

  3346. <dt><code>K</code></dt>

  3347. <dd><p>A constant that has exactly one bit clear.

  3348. </p>

  3349. </dd>

  3350. <dt><code>L</code></dt>

  3351. <dd><p>A constant between 0 and 255 inclusive.

  3352. </p>

  3353. </dd>

  3354. <dt><code>M</code></dt>

  3355. <dd><p>A constant between -255 and 0 inclusive.

  3356. </p>

  3357. </dd>

  3358. <dt><code>N</code></dt>

  3359. <dd><p>A constant between -3 and 0 inclusive.

  3360. </p>

  3361. </dd>

  3362. <dt><code>O</code></dt>

  3363. <dd><p>A constant between 1 and 4 inclusive.

  3364. </p>

  3365. </dd>

  3366. <dt><code>P</code></dt>

  3367. <dd><p>A constant between -4 and -1 inclusive.

  3368. </p>

  3369. </dd>

  3370. <dt><code>Q</code></dt>

  3371. <dd><p>A memory reference that is a stack push.

  3372. </p>

  3373. </dd>

  3374. <dt><code>R</code></dt>

  3375. <dd><p>A memory reference that is a stack pop.

  3376. </p>

  3377. </dd>

  3378. <dt><code>S</code></dt>

  3379. <dd><p>A memory reference that refers to a constant address of known value.

  3380. </p>

  3381. </dd>

  3382. <dt><code>T</code></dt>

  3383. <dd><p>The register indicated by Rx (not implemented yet).

  3384. </p>

  3385. </dd>

  3386. <dt><code>U</code></dt>

  3387. <dd><p>A constant that is not between 2 and 15 inclusive.

  3388. </p>

  3389. </dd>

  3390. <dt><code>Z</code></dt>

  3391. <dd><p>The constant 0.

  3392. </p>

  3393. </dd>

  3394. </dl>

  3395. 

  3396. </dd>

  3397. <dt><em>Xtensa&mdash;<samp>config/xtensa/constraints.md</samp></em></dt>

  3398. <dd><dl compact="compact">

  3399. <dt><code>a</code></dt>

  3400. <dd><p>General-purpose 32-bit register

  3401. </p>

  3402. </dd>

  3403. <dt><code>b</code></dt>

  3404. <dd><p>One-bit boolean register

  3405. </p>

  3406. </dd>

  3407. <dt><code>A</code></dt>

  3408. <dd><p>MAC16 40-bit accumulator register

  3409. </p>

  3410. </dd>

  3411. <dt><code>I</code></dt>

  3412. <dd><p>Signed 12-bit integer constant, for use in MOVI instructions

  3413. </p>

  3414. </dd>

  3415. <dt><code>J</code></dt>

  3416. <dd><p>Signed 8-bit integer constant, for use in ADDI instructions

  3417. </p>

  3418. </dd>

  3419. <dt><code>K</code></dt>

  3420. <dd><p>Integer constant valid for BccI instructions

  3421. </p>

  3422. </dd>

  3423. <dt><code>L</code></dt>

  3424. <dd><p>Unsigned constant valid for BccUI instructions

  3425. </p>

  3426. </dd>

  3427. </dl>

  3428. 

  3429. </dd>

  3430. </dl>

  3431. 

  3432. <hr>

  3433. <div class="header">

  3434. <p>

  3435. Next: <a href="Disable-Insn-Alternatives.html#Disable-Insn-Alternatives" accesskey="n" rel="next">Disable Insn Alternatives</a>, Previous: <a href="Modifiers.html#Modifiers" accesskey="p" rel="prev">Modifiers</a>, Up: <a href="Constraints.html#Constraints" accesskey="u" rel="up">Constraints</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>

  3436. </div>

  3437. 

  3438. 

  3439. 

  3440. </body>

  3441. </html>