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  17. <title>S12Z Addressing Modes (Using as)</title>

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  27. <link href="S12Z-Syntax.html#S12Z-Syntax" rel="up" title="S12Z Syntax">

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  61. <body lang="en">

  62. <a name="S12Z-Addressing-Modes"></a>

  63. <div class="header">

  64. <p>

  65. Next: <a href="S12Z-Register-Notation.html#S12Z-Register-Notation" accesskey="n" rel="next">S12Z Register Notation</a>, Previous: <a href="S12Z-Syntax-Overview.html#S12Z-Syntax-Overview" accesskey="p" rel="prev">S12Z Syntax Overview</a>, Up: <a href="S12Z-Syntax.html#S12Z-Syntax" accesskey="u" rel="up">S12Z Syntax</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>

  66. </div>

  67. <hr>

  68. <a name="Addressing-Modes-3"></a>

  69. <h4 class="subsubsection">9.24.2.2 Addressing Modes</h4>

  70. <a name="index-S12Z-addressing-modes"></a>

  71. <a name="index-addressing-modes_002c-S12Z"></a>

  72. 

  73. <p>The following addressing modes are understood for the S12Z.

  74. </p><dl compact="compact">

  75. <dt><em>Immediate</em></dt>

  76. <dd><p>&lsquo;<samp>#<var>number</var></samp>&rsquo;

  77. </p>

  78. </dd>

  79. <dt><em>Immediate Bit Field</em></dt>

  80. <dd><p>&lsquo;<samp>#<var>width</var>:<var>offset</var></samp>&rsquo;

  81. </p>

  82. <p>Bit field instructions in the immediate mode require the width and offset to

  83. be specified.

  84. The <var>width</var> parameter specifies the number of bits in the field.

  85. It should be a number in the range [1,32].

  86. <var>Offset</var> determines the position within the field where the operation

  87. should start.

  88. It should be a number in the range [0,31].

  89. </p>

  90. </dd>

  91. <dt><em>Relative</em></dt>

  92. <dd><p>&lsquo;<samp>*<var>symbol</var></samp>&rsquo;, or &lsquo;<samp>*[+-]<var>digits</var></samp>&rsquo;

  93. </p>

  94. <p>Program counter relative addresses have a width of 15 bits.

  95. Thus, they must be within the range [-32768, 32767].

  96. </p>

  97. </dd>

  98. <dt><em>Register</em></dt>

  99. <dd><p>&lsquo;<samp><var>reg</var></samp>&rsquo;

  100. </p>

  101. <a name="index-register-names_002c-S12Z"></a>

  102. <p>Some instructions accept a register as an operand.

  103. In general, <var>reg</var> may be a

  104. data register (&lsquo;<samp>D0</samp>&rsquo;, &lsquo;<samp>D1</samp>&rsquo; &hellip; &lsquo;<samp>D7</samp>&rsquo;),

  105. the &lsquo;<samp>X</samp>&rsquo; register or the &lsquo;<samp>Y</samp>&rsquo; register.

  106. </p>

  107. <p>A few instructions accept as an argument the stack pointer

  108. register (&lsquo;<samp>S</samp>&rsquo;), and/or the program counter (&lsquo;<samp>P</samp>&rsquo;).

  109. </p>

  110. <p>Some very special instructions accept arguments which refer to the

  111. condition code register.  For these arguments the  syntax is

  112. &lsquo;<samp>CCR</samp>&rsquo;, &lsquo;<samp>CCH</samp>&rsquo; or &lsquo;<samp>CCL</samp>&rsquo; which refer to the complete

  113. condition code register, the condition code register high byte

  114. and the condition code register low byte respectively.

  115. </p>

  116. 

  117. </dd>

  118. <dt><em>Absolute Direct</em></dt>

  119. <dd><p>&lsquo;<samp><var>symbol</var></samp>&rsquo;, or &lsquo;<samp><var>digits</var></samp>&rsquo;

  120. </p>

  121. </dd>

  122. <dt><em>Absolute Indirect</em></dt>

  123. <dd><p>&lsquo;<samp>[<var>symbol</var></samp>&rsquo;, or &lsquo;<samp><var>digits</var>]</samp>&rsquo;

  124. </p>

  125. 

  126. </dd>

  127. <dt><em>Constant Offset Indexed</em></dt>

  128. <dd><p>&lsquo;<samp>(<var>number</var>,<var>reg</var>)</samp>&rsquo;

  129. </p>

  130. <p><var>Reg</var> may be either &lsquo;<samp>X</samp>&rsquo;, &lsquo;<samp>Y</samp>&rsquo;, &lsquo;<samp>S</samp>&rsquo; or

  131. &lsquo;<samp>P</samp>&rsquo; or one of the data registers &lsquo;<samp>D0</samp>&rsquo;, &lsquo;<samp>D1</samp>&rsquo; &hellip;

  132. &lsquo;<samp>D7</samp>&rsquo;.

  133. If any of the registers &lsquo;<samp>D2</samp>&rsquo; &hellip; &lsquo;<samp>D5</samp>&rsquo; are specified, then the

  134. register value is treated as a signed value.

  135. Otherwise it is treated as unsigned.

  136. <var>Number</var> may be any integer in the range [-8388608,8388607].

  137. </p>

  138. </dd>

  139. <dt><em>Offset Indexed Indirect</em></dt>

  140. <dd><p>&lsquo;<samp>[<var>number</var>,<var>reg</var>]</samp>&rsquo;

  141. </p>

  142. <p><var>Reg</var> may be either &lsquo;<samp>X</samp>&rsquo;, &lsquo;<samp>Y</samp>&rsquo;, &lsquo;<samp>S</samp>&rsquo; or

  143. &lsquo;<samp>P</samp>&rsquo;.

  144. <var>Number</var> may be any integer in the range [-8388608,8388607].

  145. </p>

  146. </dd>

  147. <dt><em>Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement</em></dt>

  148. <dd><p>&lsquo;<samp>-<var>reg</var></samp>&rsquo;,

  149. &lsquo;<samp>+<var>reg</var></samp>&rsquo;,

  150. &lsquo;<samp><var>reg</var>-</samp>&rsquo; or

  151. &lsquo;<samp><var>reg</var>+</samp>&rsquo;

  152. </p>

  153. <p>This addressing mode is typically used to access a value at an address,

  154. and simultaneously to increment/decrement the register pointing to that

  155. address.

  156. Thus <var>reg</var> may be any of the 24 bit registers &lsquo;<samp>X</samp>&rsquo;, &lsquo;<samp>Y</samp>&rsquo;, or

  157. &lsquo;<samp>S</samp>&rsquo;.

  158. Pre-increment and post-decrement are not available for

  159. register &lsquo;<samp>S</samp>&rsquo; (only post-increment and pre-decrement are available).

  160. </p>

  161. </dd>

  162. <dt><em>Register Offset Direct</em></dt>

  163. <dd><p>&lsquo;<samp>(<var>data-reg</var>,<var>reg</var>)</samp>&rsquo;

  164. </p>

  165. <p><var>Reg</var> can be either &lsquo;<samp>X</samp>&rsquo;, &lsquo;<samp>Y</samp>&rsquo;, or &lsquo;<samp>S</samp>&rsquo;.

  166. <var>Data-reg</var>

  167. must be one of the data registers &lsquo;<samp>D0</samp>&rsquo;, &lsquo;<samp>D1</samp>&rsquo; &hellip; &lsquo;<samp>D7</samp>&rsquo;.

  168. If any of the registers &lsquo;<samp>D2</samp>&rsquo; &hellip; &lsquo;<samp>D5</samp>&rsquo; are specified, then

  169. the register value is treated as a signed value.

  170. Otherwise it is treated as unsigned.

  171. </p>

  172. </dd>

  173. <dt><em>Register Offset Indirect</em></dt>

  174. <dd><p>&lsquo;<samp>[<var>data-reg</var>,<var>reg</var>]</samp>&rsquo;

  175. </p>

  176. <p><var>Reg</var> can be either &lsquo;<samp>X</samp>&rsquo; or &lsquo;<samp>Y</samp>&rsquo;.

  177. <var>Data-reg</var>

  178. must be one of the data registers &lsquo;<samp>D0</samp>&rsquo;, &lsquo;<samp>D1</samp>&rsquo; &hellip; &lsquo;<samp>D7</samp>&rsquo;.

  179. If any of the registers &lsquo;<samp>D2</samp>&rsquo; &hellip; &lsquo;<samp>D5</samp>&rsquo; are specified, then

  180. the register value is treated as a signed value.

  181. Otherwise it is treated as unsigned.

  182. </p></dd>

  183. </dl>

  184. 

  185. <p>For example:

  186. </p>

  187. <div class="smallexample">

  188. <pre class="smallexample">	trap    #197        ;; Immediate mode

  189. 	bra     *+49        ;; Relative mode

  190. 	bra     .L0         ;;     ditto

  191. 	jmp     0xFE0034    ;; Absolute direct mode

  192. 	jmp     [0xFD0012]  ;; Absolute indirect mode

  193. 	inc.b   (4,x)       ;; Constant offset indexed mode

  194. 	jsr     (45, d0)    ;;     ditto

  195. 	dec.w   [4,y]       ;; Constant offset indexed indirect mode

  196. 	clr.p   (-s)        ;; Pre-decrement mode

  197. 	neg.l   (d0, s)     ;; Register offset direct mode

  198. 	com.b   [d1, x]     ;; Register offset indirect mode

  199. 	psh     cch         ;; Register mode

  200. </pre></div>

  201. 

  202. <hr>

  203. <div class="header">

  204. <p>

  205. Next: <a href="S12Z-Register-Notation.html#S12Z-Register-Notation" accesskey="n" rel="next">S12Z Register Notation</a>, Previous: <a href="S12Z-Syntax-Overview.html#S12Z-Syntax-Overview" accesskey="p" rel="prev">S12Z Syntax Overview</a>, Up: <a href="S12Z-Syntax.html#S12Z-Syntax" accesskey="u" rel="up">S12Z Syntax</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>

  206. </div>

  207. 

  208. 

  209. 

  210. </body>

  211. </html>