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- <title>PowerPC Features (Debugging with GDB)</title>
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- <a name="PowerPC-Features"></a>
- <div class="header">
- <p>
- Next: <a href="RISC_002dV-Features.html#RISC_002dV-Features" accesskey="n" rel="next">RISC-V Features</a>, Previous: <a href="OpenRISC-1000-Features.html#OpenRISC-1000-Features" accesskey="p" rel="prev">OpenRISC 1000 Features</a>, Up: <a href="Standard-Target-Features.html#Standard-Target-Features" accesskey="u" rel="up">Standard Target Features</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Concept-Index.html#Concept-Index" title="Index" rel="index">Index</a>]</p>
- </div>
- <hr>
- <a name="PowerPC-Features-1"></a>
- <h4 class="subsection">G.5.11 PowerPC Features</h4>
- <a name="index-target-descriptions_002c-PowerPC-features"></a>
-
- <p>The ‘<samp>org.gnu.gdb.power.core</samp>’ feature is required for PowerPC
- targets. It should contain registers ‘<samp>r0</samp>’ through ‘<samp>r31</samp>’,
- ‘<samp>pc</samp>’, ‘<samp>msr</samp>’, ‘<samp>cr</samp>’, ‘<samp>lr</samp>’, ‘<samp>ctr</samp>’, and
- ‘<samp>xer</samp>’. They may be 32-bit or 64-bit depending on the target.
- </p>
- <p>The ‘<samp>org.gnu.gdb.power.fpu</samp>’ feature is optional. It should
- contain registers ‘<samp>f0</samp>’ through ‘<samp>f31</samp>’ and ‘<samp>fpscr</samp>’.
- </p>
- <p>The ‘<samp>org.gnu.gdb.power.altivec</samp>’ feature is optional. It should
- contain registers ‘<samp>vr0</samp>’ through ‘<samp>vr31</samp>’, ‘<samp>vscr</samp>’, and
- ‘<samp>vrsave</samp>’. <small>GDB</small> will define pseudo-registers ‘<samp>v0</samp>’
- through ‘<samp>v31</samp>’ as aliases for the corresponding ‘<samp>vrX</samp>’
- registers.
- </p>
- <p>The ‘<samp>org.gnu.gdb.power.vsx</samp>’ feature is optional. It should
- contain registers ‘<samp>vs0h</samp>’ through ‘<samp>vs31h</samp>’. <small>GDB</small> will
- combine these registers with the floating point registers (‘<samp>f0</samp>’
- through ‘<samp>f31</samp>’) and the altivec registers (‘<samp>vr0</samp>’ through
- ‘<samp>vr31</samp>’) to present the 128-bit wide registers ‘<samp>vs0</samp>’ through
- ‘<samp>vs63</samp>’, the set of vector-scalar registers for POWER7.
- Therefore, this feature requires both ‘<samp>org.gnu.gdb.power.fpu</samp>’ and
- ‘<samp>org.gnu.gdb.power.altivec</samp>’.
- </p>
- <p>The ‘<samp>org.gnu.gdb.power.spe</samp>’ feature is optional. It should
- contain registers ‘<samp>ev0h</samp>’ through ‘<samp>ev31h</samp>’, ‘<samp>acc</samp>’, and
- ‘<samp>spefscr</samp>’. SPE targets should provide 32-bit registers in
- ‘<samp>org.gnu.gdb.power.core</samp>’ and provide the upper halves in
- ‘<samp>ev0h</samp>’ through ‘<samp>ev31h</samp>’. <small>GDB</small> will combine
- these to present registers ‘<samp>ev0</samp>’ through ‘<samp>ev31</samp>’ to the
- user.
- </p>
- <p>The ‘<samp>org.gnu.gdb.power.ppr</samp>’ feature is optional. It should
- contain the 64-bit register ‘<samp>ppr</samp>’.
- </p>
- <p>The ‘<samp>org.gnu.gdb.power.dscr</samp>’ feature is optional. It should
- contain the 64-bit register ‘<samp>dscr</samp>’.
- </p>
- <p>The ‘<samp>org.gnu.gdb.power.tar</samp>’ feature is optional. It should
- contain the 64-bit register ‘<samp>tar</samp>’.
- </p>
- <p>The ‘<samp>org.gnu.gdb.power.ebb</samp>’ feature is optional. It should
- contain registers ‘<samp>bescr</samp>’, ‘<samp>ebbhr</samp>’ and ‘<samp>ebbrr</samp>’, all
- 64-bit wide.
- </p>
- <p>The ‘<samp>org.gnu.gdb.power.linux.pmu</samp>’ feature is optional. It should
- contain registers ‘<samp>mmcr0</samp>’, ‘<samp>mmcr2</samp>’, ‘<samp>siar</samp>’, ‘<samp>sdar</samp>’
- and ‘<samp>sier</samp>’, all 64-bit wide. This is the subset of the isa 2.07
- server PMU registers provided by <small>GNU</small>/Linux.
- </p>
- <p>The ‘<samp>org.gnu.gdb.power.htm.spr</samp>’ feature is optional. It should
- contain registers ‘<samp>tfhar</samp>’, ‘<samp>texasr</samp>’ and ‘<samp>tfiar</samp>’, all
- 64-bit wide.
- </p>
- <p>The ‘<samp>org.gnu.gdb.power.htm.core</samp>’ feature is optional. It should
- contain the checkpointed general-purpose registers ‘<samp>cr0</samp>’ through
- ‘<samp>cr31</samp>’, as well as the checkpointed registers ‘<samp>clr</samp>’ and
- ‘<samp>cctr</samp>’. These registers may all be either 32-bit or 64-bit
- depending on the target. It should also contain the checkpointed
- registers ‘<samp>ccr</samp>’ and ‘<samp>cxer</samp>’, which should both be 32-bit
- wide.
- </p>
- <p>The ‘<samp>org.gnu.gdb.power.htm.fpu</samp>’ feature is optional. It should
- contain the checkpointed 64-bit floating-point registers ‘<samp>cf0</samp>’
- through ‘<samp>cf31</samp>’, as well as the checkpointed 64-bit register
- ‘<samp>cfpscr</samp>’.
- </p>
- <p>The ‘<samp>org.gnu.gdb.power.htm.altivec</samp>’ feature is optional. It
- should contain the checkpointed altivec registers ‘<samp>cvr0</samp>’ through
- ‘<samp>cvr31</samp>’, all 128-bit wide. It should also contain the
- checkpointed registers ‘<samp>cvscr</samp>’ and ‘<samp>cvrsave</samp>’, both 32-bit
- wide.
- </p>
- <p>The ‘<samp>org.gnu.gdb.power.htm.vsx</samp>’ feature is optional. It should
- contain registers ‘<samp>cvs0h</samp>’ through ‘<samp>cvs31h</samp>’. <small>GDB</small>
- will combine these registers with the checkpointed floating point
- registers (‘<samp>cf0</samp>’ through ‘<samp>cf31</samp>’) and the checkpointed
- altivec registers (‘<samp>cvr0</samp>’ through ‘<samp>cvr31</samp>’) to present the
- 128-bit wide checkpointed vector-scalar registers ‘<samp>cvs0</samp>’ through
- ‘<samp>cvs63</samp>’. Therefore, this feature requires both
- ‘<samp>org.gnu.gdb.power.htm.altivec</samp>’ and
- ‘<samp>org.gnu.gdb.power.htm.fpu</samp>’.
- </p>
- <p>The ‘<samp>org.gnu.gdb.power.htm.ppr</samp>’ feature is optional. It should
- contain the 64-bit checkpointed register ‘<samp>cppr</samp>’.
- </p>
- <p>The ‘<samp>org.gnu.gdb.power.htm.dscr</samp>’ feature is optional. It should
- contain the 64-bit checkpointed register ‘<samp>cdscr</samp>’.
- </p>
- <p>The ‘<samp>org.gnu.gdb.power.htm.tar</samp>’ feature is optional. It should
- contain the 64-bit checkpointed register ‘<samp>ctar</samp>’.
- </p>
-
- <hr>
- <div class="header">
- <p>
- Next: <a href="RISC_002dV-Features.html#RISC_002dV-Features" accesskey="n" rel="next">RISC-V Features</a>, Previous: <a href="OpenRISC-1000-Features.html#OpenRISC-1000-Features" accesskey="p" rel="prev">OpenRISC 1000 Features</a>, Up: <a href="Standard-Target-Features.html#Standard-Target-Features" accesskey="u" rel="up">Standard Target Features</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Concept-Index.html#Concept-Index" title="Index" rel="index">Index</a>]</p>
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