Add T4 ADC_ETC definitions for bits plus structure

Decided to go to the format that is closer to the the manual to
and use names like: chain_1_0, chain_3_2...

Add structure to make it easer to use ADC objects,

Plus updated defines to use the structure.
Left in my own define for structure location as a trigger to not define it in my own code when running older version of core...

Also added defines for XBAR, such that we can hopefully not have to use magic numbers to say, map PID1 to ADC_ETC1_...

The TX and RX values were reversed.
That is for example on Serial1 (LPUART6)
Before we had:
```
```
now we have
```
```
So for example trying to get WS2812Serial library to work was failing, to output anything.

Needed to implement Quad encoder library.

Current naming is confusing since it differs between GTP1 and GTP2. The GTP2 version is compatible to the naming in the data sheet. So I suggest to adjust the naming for  GPT1

I suggest to explicitely delcare a (say)  IMXRT_TMR_CH_t struct which collects the registers for a TMR  channel instead of implicitely defining this struct in the declaration of IMXRT_TMR_t.

This would allow for an easier definition of user classes modelling a TMR channel.
Not a big deal, could also do that mayself the class code but it would be more convenient if this would be done in imxrt.h

Moved from my flexio_t4 library.
Libary was updated to see if already defined before it now defines it.

The FlexIO registers are 32 bits, the masks were all setup for 16 bits so the high word of registers were not updated

I created a structure IMXRT_LPSPI_t
like what was done for UARTS.

I hopefully got all of the unused fields in properly to get the registers on the correct addresses.
Note: I did not update the other #define LPSPIn_ values but left them, likewise, I create a new define for each of the addresses.

That way we can double check I have everything properly aligned

Tempsense2 address correction and added analogreadaveraging code.

- comment SRC_GPR1..SRC_GPR10 (used by the ROM code)